mirror of https://github.com/lnis-uofu/SOFA.git
Updating interface definition for QL k4_N8 device
This commit is contained in:
Lalit Sharma
parent
e82d2bf0d1
commit
8f1bdc2e87
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@ -76,11 +76,22 @@
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<equivalent_sites>
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<equivalent_sites>
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<site pb_type="io"/>
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<site pb_type="io"/>
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</equivalent_sites>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<!--input name="a2f_i" num_pins="1"/-->
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<input name="f2a_i" num_pins="1"/>
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<output name="a2f_o" num_pins="1"/>
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<!--output name="f2a_o" num_pins="1"/-->
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<input name="sc_in" num_pins="1"/>
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<output name="sc_out" num_pins="1"/>
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<input name="reset" num_pins="1" is_non_clock_global="true"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
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<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
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<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
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<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
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</fc>
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<pinlocations pattern="custom">
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<pinlocations pattern="custom">
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<loc side="bottom">io_top.outpad io_top.inpad</loc>
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<loc side="bottom">io_top.a2f_o io_top.f2a_i io_top.clk io_top.sc_in io_top.sc_out io_top.reset</loc>
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</pinlocations>
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</pinlocations>
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</tile>
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</tile>
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<!-- Right-side has 1 I/O per tile -->
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<!-- Right-side has 1 I/O per tile -->
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@ -88,11 +99,20 @@
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<equivalent_sites>
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<equivalent_sites>
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<site pb_type="io"/>
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<site pb_type="io"/>
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</equivalent_sites>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<input name="f2a_i" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<output name="a2f_o" num_pins="1"/>
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<input name="sc_in" num_pins="1"/>
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<output name="sc_out" num_pins="1"/>
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<input name="reset" num_pins="1" is_non_clock_global="true"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
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<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
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<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
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<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
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</fc>
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<pinlocations pattern="custom">
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<pinlocations pattern="custom">
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<loc side="left">io_right.outpad io_right.inpad</loc>
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<loc side="left">io_right.a2f_o io_right.f2a_i io_right.clk io_right.sc_in io_right.sc_out io_right.reset</loc>
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</pinlocations>
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</pinlocations>
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</tile>
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</tile>
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<!-- Bottom-side has 9 I/O per tile -->
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<!-- Bottom-side has 9 I/O per tile -->
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@ -100,11 +120,20 @@
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<equivalent_sites>
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<equivalent_sites>
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<site pb_type="io"/>
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<site pb_type="io"/>
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</equivalent_sites>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<input name="f2a_i" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<output name="a2f_o" num_pins="1"/>
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<input name="sc_in" num_pins="1"/>
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<output name="sc_out" num_pins="1"/>
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<input name="reset" num_pins="1" is_non_clock_global="true"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
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<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
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<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
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<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
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</fc>
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<pinlocations pattern="custom">
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<pinlocations pattern="custom">
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<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
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<loc side="top">io_bottom.a2f_o io_bottom.f2a_i io_bottom.clk io_bottom.sc_in io_bottom.sc_out io_bottom.reset</loc>
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</pinlocations>
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</pinlocations>
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</tile>
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</tile>
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<!-- Left-side has 1 I/O per tile -->
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<!-- Left-side has 1 I/O per tile -->
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@ -112,11 +141,20 @@
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<equivalent_sites>
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<equivalent_sites>
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<site pb_type="io"/>
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<site pb_type="io"/>
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</equivalent_sites>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<input name="f2a_i" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<output name="a2f_o" num_pins="1"/>
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<input name="sc_in" num_pins="1"/>
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<output name="sc_out" num_pins="1"/>
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<input name="reset" num_pins="1" is_non_clock_global="true"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
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<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
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<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
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<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
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</fc>
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<pinlocations pattern="custom">
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<pinlocations pattern="custom">
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<loc side="right">io_left.outpad io_left.inpad</loc>
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<loc side="right">io_left.a2f_o io_left.f2a_i io_left.clk io_left.sc_in io_left.sc_out io_left.reset</loc>
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</pinlocations>
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</pinlocations>
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</tile>
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</tile>
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<!-- CLB has most pins on the top and right sides -->
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<!-- CLB has most pins on the top and right sides -->
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@ -275,56 +313,130 @@
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<complexblocklist>
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<complexblocklist>
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<!-- Define input pads begin -->
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<!-- Define input pads begin -->
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<pb_type name="io">
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<pb_type name="io">
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<input name="outpad" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<!--input name="a2f_i" num_pins="1"/-->
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<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
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<input name="f2a_i" num_pins="1"/>
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If you need to register the I/O, define clocks in the circuit models
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<output name="a2f_o" num_pins="1"/>
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These clocks can be handled in back-end
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<!--output name="f2a_o" num_pins="1"/-->
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-->
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<input name="sc_in" num_pins="1"/>
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<!-- A mode denotes the physical implementation of an I/O
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<output name="sc_out" num_pins="1"/>
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This mode will be not packable but is mainly used for fabric verilog generation
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<input name="reset" num_pins="1" is_non_clock_global="true"/>
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-->
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<!-- Physical mode definition begin (physical implementation of the io) -->
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<mode name="physical" disabled_in_pack="true">
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<mode name="physical" disabled_in_pack="true">
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<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
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<pb_type name="iopad" num_pb="1">
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<input name="outpad" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<!--input name="a2f_i" num_pins="1"/-->
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<input name="f2a_i" num_pins="1"/>
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<output name="a2f_o" num_pins="1"/>
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<!--output name="f2a_o" num_pins="1"/-->
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<input name="sc_in" num_pins="1"/>
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<input name="reset" num_pins="1"/>
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<output name="sc_out" num_pins="1"/>
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<pb_type name="ff" blif_model=".subckt scff" num_pb="2">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="DI" num_pins="1"/>
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<input name="reset" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_setup value="66e-12" port="ff.DI" clock="clk"/>
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<T_setup value="66e-12" port="ff.reset" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<pb_type name="pad" blif_model=".subckt io" num_pb="1">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="ff[0:0]-clk" input="iopad.clk" output="ff[0:0].clk"/>
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<direct name="ff[1:1]-clk" input="iopad.clk" output="ff[1:1].clk"/>
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<direct name="ff[0:0]-D" input="iopad.f2a_i" output="ff[0:0].D" />
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<!--direct name="ff[1:1]-D" input="iopad.a2f_i" output="ff[1:1].D" /-->
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<direct name="ff[1:1]-D" input="pad.inpad" output="ff[1:1].D"/>
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<direct name="ff[0:0]-DI" input="iopad.sc_in" output="ff[0:0].DI"/>
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<direct name="ff[1:1]-DI" input="ff[0:0].Q" output="ff[1:1].DI"/>
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<direct name="iopad-sc_out" input="ff[1:1].Q" output="iopad.sc_out"/>
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<complete name="complete1" input="iopad.reset" output="ff[1:0].reset"/>
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<mux name="mux1" input="iopad.f2a_i ff[0:0].Q" output="pad.outpad">
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<delay_constant max="25e-12" in_port="iopad.f2a_i" out_port="pad.outpad"/>
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<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="pad.outpad"/>
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</mux>
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<mux name="mux2" input="pad.inpad ff[1:1].Q" output="iopad.a2f_o">
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<delay_constant max="25e-12" in_port="pad.inpad" out_port="iopad.a2f_o"/>
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<delay_constant max="45e-12" in_port="ff[1:1].Q" out_port="iopad.a2f_o"/>
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</mux>
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</interconnect>
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</pb_type>
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</pb_type>
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<interconnect>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="iopad.outpad">
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<direct name="direct1" input="io.clk" output="iopad.clk"/>
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
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<!--direct name="direct2" input="io.a2f_i" output="iopad.a2f_i"/-->
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</direct>
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<direct name="direct3" input="io.f2a_i" output="iopad.f2a_i"/>
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<direct name="inpad" input="iopad.inpad" output="io.inpad">
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<direct name="direct4" input="iopad.a2f_o" output="io.a2f_o"/>
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<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
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<!--direct name="direct5" input="iopad.f2a_o" output="io.f2a_o"/-->
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</direct>
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<direct name="direct6" input="io.sc_in" output="iopad.sc_in"/>
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<direct name="direct7" input="iopad.sc_out" output="io.sc_out"/>
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<direct name="direct8" input="io.reset" output="iopad.reset"/>
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</interconnect>
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</interconnect>
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</mode>
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</mode>
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<!-- Physical mode definition end (physical implementation of the io) -->
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<!-- IOs can operate as either inputs or outputs.
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<mode name="io_output">
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Delays below come from Ian Kuon. They are small, so they should be interpreted as
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<pb_type name="io_output" num_pb="1">
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the delays to and from registers in the I/O (and generally I/Os are registered
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<clock name="clk" num_pins="1"/>
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today and that is when you timing analyze them.
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<input name="f2a_i" num_pins="1"/>
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-->
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<mode name="inpad">
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<input name="D" num_pins="1" port_class="D"/>
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="Q" num_pins="1" port_class="Q"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="ff-clk" input="io_output.clk" output="ff.clk"/>
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<direct name="ff-D" input="io_output.f2a_i" output="ff.D"/>
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<mux name="mux1" input="ff.Q io_output.f2a_i" output="outpad.outpad">
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<pack_pattern name="pack-OREG" in_port="ff.Q" out_port="outpad.outpad"/>
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<delay_constant max="25e-12" in_port="io_output.f2a_i" out_port="outpad.outpad"/>
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<delay_constant max="45e-12" in_port="ff.Q" out_port="outpad.outpad"/>
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</mux>
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</interconnect>
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</pb_type>
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</pb_type>
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<interconnect>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<direct name="io_output-clk" input="io.clk" output="io_output.clk"/>
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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<direct name="io_output-f2a_i" input="io.f2a_i" output="io_output.f2a_i"/>
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</direct>
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</interconnect>
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</interconnect>
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</mode>
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</mode>
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<mode name="outpad">
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<mode name="io_input">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<pb_type name="io_input" num_pb="1">
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<input name="outpad" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<output name="a2f_o" num_pins="1"/>
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="ff-clk" input="io_input.clk" output="ff.clk"/>
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<direct name="ff-D" input="inpad.inpad" output="ff.D"/>
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<mux name="mux2" input="inpad.inpad ff.Q" output="io_input.a2f_o">
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<pack_pattern name="pack-IREG" in_port="ff.Q" out_port="io_input.a2f_o"/>
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<delay_constant max="25e-12" in_port="inpad.inpad" out_port="io_input.a2f_o"/>
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<delay_constant max="45e-12" in_port="ff.Q" out_port="io_input.a2f_o"/>
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</mux>
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</interconnect>
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</pb_type>
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</pb_type>
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<interconnect>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<direct name="io-a2f_o" input="io_input.a2f_o" output="io.a2f_o"/>
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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<direct name="io_input-clk" input="io.clk" output="io_input.clk"/>
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</direct>
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</interconnect>
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</interconnect>
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</mode>
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</mode>
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<power method="ignore"/>
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</pb_type>
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</pb_type>
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<!-- Define I/O pads ends -->
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<!-- Define I/O pads ends -->
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<!-- Define general purpose logic block (CLB) begin -->
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<!-- Define general purpose logic block (CLB) begin -->
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