From 8e9a5e1c71e374bd5fb73c850d44b6e923a722d4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Oct 2020 22:17:00 -0600 Subject: [PATCH] [Documentation] Update README frontpage --- README.md | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/README.md b/README.md index 1a5538c..1fa4be0 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,20 @@ # skywater-openfpga FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA + +* Keep this folder clean and organized as follows + - DOC: documentation of the project + - ARCH: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists + - BENCHMARK: Benchmarks to be tested on the FPGA fabric + - HDL: Hardware description netlists for the FPGA fabrics + - SDC: design constraints + - SCRIPT: Scripts to setup, run OpenFPGA etc. + - TESTBENCH: Verilog testbenches generated by OpenFPGA + - PDK: Technology files linked from skywater opensource pdk + - SNPS\_ICC2: scripts and workspace of Synopsys IC Compiler 2 + Keep a README inside the folder about the ICC2 version and how-to-use. + - MSIM: scripts and workspace of verification using Mentor ModelSim + +* Note: + - Please **ONLY** place folders under this directory + README should be the ONLY file under this directory + - Each EDA tool should have independent workspace in a separated directory