[Doc] Update documentation about I/O resources

DOC/source/arch/clb.rst

@@ -1,5 +1,7 @@
-Configurable Logic Block User Guide
+.. _clb:
------------------------------------
+
+Configurable Logic Block
+------------------------
 
 Each Configurable Logic Block (CLB) consists of 8 logic elements as shown in :numref:`fig_fle_arch`.
 

DOC/source/arch/index.rst

@@ -4,4 +4,6 @@
 .. toctree::
    :maxdepth: 2
 
+   io_resource
+
    clb

DOC/source/arch/io_resource.rst

@@ -0,0 +1,66 @@
+.. _io_resource:
+
+I/O Resources
+-------------
+
+.. _io_resource_overview:
+
+Overview
+~~~~~~~~
+
+The *High-Density* (HD) FPGA IP has 144 I/O pins as shown in :numref:`fig_fpga_io_switch`.
+
+Among the 144 I/Os, 
+
+- **30 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs).
+
+- **114 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`io_resoure_debug` and :ref:`io_resource_accelerator` for details. 
+
+.. note:: The connectivity of the 114 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes. 
+
+.. _fig_fpga_io_switch:
+
+.. figure:: ./figures/fpga_io_switch.png
+  :scale: 20%
+  :alt: I/O arrangement of FPGA IP
+
+  I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface
+
+
+.. _io_resource_accelerator:
+
+Accelerator Mode
+~~~~~~~~~~~~~~~~
+
+When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
+:numref:`fig_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations. 
+
+.. note:: Not all the 114 internal I/Os are used by the Wishbone interface. Especially, the I/O[122:131] are not connected.
+
+.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.
+
+.. _fig_fpga_io_map_wishbone_mode:
+
+.. figure:: ./figures/fpga_io_map_wishbone_mode.png
+  :scale: 20%
+  :alt: I/O arrangement of FPGA IP when interfacing wishbone bus
+
+  I/O arrangement of *High-Density* (HD) FPGA IP when interfacing wishbone bus
+
+.. _io_resource_debug:
+
+Debug Mode
+~~~~~~~~~~
+
+When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor.
+:numref:`fig_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations. 
+
+.. note:: The logic analyzer is 128-bit, while 114 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose.
+
+.. _fig_fpga_io_map_logic_analyzer_mode:
+
+.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.png
+  :scale: 20%
+  :alt: I/O arrangement of FPGA IP when interfacing logic analyzer
+
+  I/O arrangement of *High-Density* (HD) FPGA IP when interfacing logic analyzer

DOC/source/dc_ac_character.rst

@@ -1,7 +1,9 @@
+.. _dc_ac_character:
+
 DC and AC Characteristics
 -------------------------
 
-Each FPGA device contains 37 I/O pins, whose details are summarized in the following tables.
+Each FPGA device contains 37 external I/O pins, whose details are summarized in the following tables.
 
 I/O usage and port information
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

DOC/source/device_family.rst

@@ -1,5 +1,7 @@
-Device Overview
+.. _device_family:
----------------
+
+Overview
+--------
 
 All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII.
 All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK. 
@@ -25,7 +27,7 @@ We aims to empower embedded applications with its low-cost design approach but h
   +--------------------------+------------+
   | Max. Operating Speed     |   TBD      |
   +--------------------------+------------+
-  | User I/O Pins            |   30       |
+  | User I/O Pins            |   144      |
   +--------------------------+------------+
   | Max. I/O Speed           |   TBD      |
   +--------------------------+------------+

DOC/source/index.rst

@@ -3,13 +3,13 @@
    You can adapt this file completely to your liking, but it should at least
    contain the root `toctree` directive.
 
-Welcome to FROG's documentation!
+Welcome to SKywater-OpenFPGA documentation!
-====================================
+===========================================
 
 .. toctree::
    :caption: Device
 
-   technical_highlights
+   device_family
 
    dc_ac_character
 
@@ -29,7 +29,9 @@ Welcome to FROG's documentation!
 
 For more information on the OpenFPGA see openfpga_doc_ or openfpga_github_
 
-For more information on the original FPGA architecture description language see xml_vtr_
+For more information on the VPR architecture description language see xml_vtr_
+
+For more information on the Skywater 130nm PDK see skywater_pdk_github_
 
 Indices and tables
 ==================
@@ -41,3 +43,4 @@ Indices and tables
 .. _openfpga_doc: https://docs.verilogtorouting.org/en/latest/
 .. _openfpga_github: https://github.com/verilog-to-routing/vtr-verilog-to-routing
 .. _xml_vtr: https://docs.verilogtorouting.org/en/latest/arch/reference/
+.. _skywater_pdk_github: https://github.com/google/skywater-pdk