From 23ac6af11ff2de2ecde6fd1339597106823347ec Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 1 Nov 2020 15:45:41 -0700
Subject: [PATCH 01/14] [Arch] Bug fix on the wrong verilog netlist path

---
 ...scan_chain_skywater130nm_fdhd_cc_openfpga.xml | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
index ae31d83..806c518 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
@@ -31,7 +31,7 @@
     </variation_library>
   </technology_library>
   <circuit_library>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v">
+    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v">
       <design_technology type="cmos" topology="inverter" size="1"/>
       <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" lib_name="A" size="1"/>
@@ -43,7 +43,7 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
+    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
       <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
       <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" lib_name="A" size="1"/>
@@ -55,7 +55,7 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v">
+    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v">
       <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
       <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" lib_name="A" size="1"/>
@@ -67,7 +67,7 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
+    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
       <design_technology type="cmos" topology="buffer" size="1"/>
       <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" lib_name="A" size="1"/>
@@ -79,7 +79,7 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
+    <circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
       <design_technology type="cmos" topology="OR"/>
       <device_technology device_model_name="logic"/>
       <input_buffer exist="false"/>
@@ -101,7 +101,7 @@
          If your standard cell provider does not offer the exact truth table,
          you can simply swap the inputs as shown in the example below
       -->
-    <circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
+    <circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
       <design_technology type="cmos" topology="MUX2"/>
       <device_technology device_model_name="logic"/>
       <input_buffer exist="false"/>
@@ -148,7 +148,7 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxbp_1" prefix="sky130_fd_sc_hd__sdfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v">
+    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxbp_1" prefix="sky130_fd_sc_hd__sdfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
@@ -174,7 +174,7 @@
       <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sky130_fd_sc_hd__dfxbp_1" prefix="sky130_fd_sc_hd__dfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrbp/sky130_fd_sc_hd__dfxbp_1.v">
+    <circuit_model type="ccff" name="sky130_fd_sc_hd__dfxbp_1" prefix="sky130_fd_sc_hd__dfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrbp/sky130_fd_sc_hd__dfxbp_1.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>

From bff4fdfdc125e422552328551d63c7ac6c829331 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 2 Nov 2020 11:27:44 -0700
Subject: [PATCH 02/14] [Arch] Update pin equivalence for the non-LR non-adder
 k4 arch

---
 ...n_chain_skywater130nm_fdhd_cc_openfpga.xml |   2 +-
 ...egister_scan_chain_nonLR_skywater130nm.xml | 126 ++++++++++++------
 2 files changed, 83 insertions(+), 45 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
index 806c518..e4b1313 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
@@ -174,7 +174,7 @@
       <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sky130_fd_sc_hd__dfxbp_1" prefix="sky130_fd_sc_hd__dfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrbp/sky130_fd_sc_hd__dfxbp_1.v">
+    <circuit_model type="ccff" name="sky130_fd_sc_hd__dfxbp_1" prefix="sky130_fd_sc_hd__dfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
index 5d865fd..1d28d35 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
@@ -78,14 +78,22 @@
       <equivalent_sites>
         <site pb_type="clb"/>
       </equivalent_sites>
-      <input name="I0" num_pins="4" equivalent="full"/>
-      <input name="I1" num_pins="4" equivalent="full"/>
-      <input name="I2" num_pins="4" equivalent="full"/>
-      <input name="I3" num_pins="4" equivalent="full"/>
-      <input name="I4" num_pins="4" equivalent="full"/>
-      <input name="I5" num_pins="4" equivalent="full"/>
-      <input name="I6" num_pins="4" equivalent="full"/>
-      <input name="I7" num_pins="4" equivalent="full"/>
+      <input name="I0" num_pins="3" equivalent="full"/>
+      <input name="I0i" num_pins="1" equivalent="none"/>
+      <input name="I1" num_pins="3" equivalent="full"/>
+      <input name="I1i" num_pins="1" equivalent="none"/>
+      <input name="I2" num_pins="3" equivalent="full"/>
+      <input name="I2i" num_pins="1" equivalent="none"/>
+      <input name="I3" num_pins="3" equivalent="full"/>
+      <input name="I3i" num_pins="1" equivalent="none"/>
+      <input name="I4" num_pins="3" equivalent="full"/>
+      <input name="I4i" num_pins="1" equivalent="none"/>
+      <input name="I5" num_pins="3" equivalent="full"/>
+      <input name="I5i" num_pins="1" equivalent="none"/>
+      <input name="I6" num_pins="3" equivalent="full"/>
+      <input name="I6i" num_pins="1" equivalent="none"/>
+      <input name="I7" num_pins="3" equivalent="full"/>
+      <input name="I7i" num_pins="1" equivalent="none"/>
       <input name="regin" num_pins="1"/>
       <input name="scin" num_pins="1"/>
       <output name="O" num_pins="16" equivalent="none"/>
@@ -102,8 +110,8 @@
       <pinlocations pattern="custom">
         <loc side="left">clb.clk</loc>
         <loc side="top">clb.regin clb.scin</loc>
-        <loc side="right">clb.O[7:0] clb.I0 clb.I1 clb.I2 clb.I3</loc>
-        <loc side="bottom">clb.regout clb.scout clb.O[15:8] clb.I4 clb.I5 clb.I6 clb.I7</loc>
+        <loc side="right">clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i </loc>
+        <loc side="bottom">clb.regout clb.scout clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
       </pinlocations>
     </tile>
   </tiles>
@@ -276,24 +284,28 @@
     </pb_type>
     <!-- Define I/O pads ends -->
     <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
+    <!-- -Due to the absence of local routing, 
+         the 4 inputs of fracturable LUT4 are no longer equivalent, 
+         because the 4th input can not be switched when the dual-LUT3 modes are used.
+         So pin equivalence should be applied to the first 3 inputs only
+	  -->
     <pb_type name="clb">
-      <input name="I0" num_pins="4" equivalent="full"/>
-      <input name="I1" num_pins="4" equivalent="full"/>
-      <input name="I2" num_pins="4" equivalent="full"/>
-      <input name="I3" num_pins="4" equivalent="full"/>
-      <input name="I4" num_pins="4" equivalent="full"/>
-      <input name="I5" num_pins="4" equivalent="full"/>
-      <input name="I6" num_pins="4" equivalent="full"/>
-      <input name="I7" num_pins="4" equivalent="full"/>
+      <input name="I0" num_pins="3" equivalent="full"/>
+      <input name="I0i" num_pins="1" equivalent="none"/>
+      <input name="I1" num_pins="3" equivalent="full"/>
+      <input name="I1i" num_pins="1" equivalent="none"/>
+      <input name="I2" num_pins="3" equivalent="full"/>
+      <input name="I2i" num_pins="1" equivalent="none"/>
+      <input name="I3" num_pins="3" equivalent="full"/>
+      <input name="I3i" num_pins="1" equivalent="none"/>
+      <input name="I4" num_pins="3" equivalent="full"/>
+      <input name="I4i" num_pins="1" equivalent="none"/>
+      <input name="I5" num_pins="3" equivalent="full"/>
+      <input name="I5i" num_pins="1" equivalent="none"/>
+      <input name="I6" num_pins="3" equivalent="full"/>
+      <input name="I6i" num_pins="1" equivalent="none"/>
+      <input name="I7" num_pins="3" equivalent="full"/>
+      <input name="I7i" num_pins="1" equivalent="none"/>
       <input name="regin" num_pins="1"/>
       <input name="scin" num_pins="1"/>
       <output name="O" num_pins="16" equivalent="none"/>
@@ -534,30 +546,56 @@
         <!-- Define shift register end --> 
       </pb_type>
       <interconnect>
-        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
-		     The delays below come from Stratix IV. the delay through a connection block
-		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-		     delay within the crossbar is 95 ps. 
-		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-		     to get the part that should be marked on the crossbar.	 -->
-        <direct name="direct_fle0" input="clb.I0" output="fle[0:0].in">
+        <!-- We use direct connections to reduce the area to the most
+             The global local routing is going to compensate the loss in routability
+          -->
+        <direct name="direct_fle0" input="clb.I0" output="fle[0:0].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle1" input="clb.I1" output="fle[1:1].in">
+        <direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle2" input="clb.I2" output="fle[2:2].in">
+        <direct name="direct_fle1" input="clb.I1" output="fle[1:1].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle3" input="clb.I3" output="fle[3:3].in">
+        <direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle4" input="clb.I4" output="fle[4:4].in">
+        <direct name="direct_fle2" input="clb.I2" output="fle[2:2].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle5" input="clb.I5" output="fle[5:5].in">
+        <direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle6" input="clb.I6" output="fle[6:6].in">
+        <direct name="direct_fle3" input="clb.I3" output="fle[3:3].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
-        <direct name="direct_fle7" input="clb.I7" output="fle[7:7].in">
+        <direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle4" input="clb.I4" output="fle[4:4].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle5" input="clb.I5" output="fle[5:5].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle6" input="clb.I6" output="fle[6:6].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle7" input="clb.I7" output="fle[7:7].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>
         <complete name="clks" input="clb.clk" output="fle[7:0].clk">
         </complete>

From 3f10b49eebecdc820f4d06dd9a4944069fcbc1c9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 2 Nov 2020 11:28:29 -0700
Subject: [PATCH 03/14] [PDK] Add standard cell wrapper

---
 PDK/sc_verilog/std_cell_extract.v | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 PDK/sc_verilog/std_cell_extract.v

diff --git a/PDK/sc_verilog/std_cell_extract.v b/PDK/sc_verilog/std_cell_extract.v
new file mode 100644
index 0000000..be56f7f
--- /dev/null
+++ b/PDK/sc_verilog/std_cell_extract.v
@@ -0,0 +1,29 @@
+`timescale 1ns/1ps
+
+//
+//
+//
+//
+//
+//
+
+//
+//
+//
+
+module GPIO (A, IE, OE, Y, in, out, mem_out);
+    output A;
+    output IE;
+    output OE;
+    output Y;
+    input in;
+    output out;
+    input mem_out;
+
+    assign A = in;
+    assign out = Y;
+    assign IE = mem_out;
+    sky130_fd_sc_hd__inv_1 ie_oe_inv (
+        .A	(mem_out),
+        .Y	(OE) );
+endmodule

From c26f8a5aacabfbe2e923272fb2513e62a8904233 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 2 Nov 2020 19:55:40 -0700
Subject: [PATCH 04/14] [Arch] Add architecture files for embedded FPGA IP

---
 ...dded_io_skywater130nm_fdhd_cc_openfpga.xml | 250 +++++++
 ..._chain_nonLR_embedded_io_skywater130nm.xml | 646 ++++++++++++++++++
 2 files changed, 896 insertions(+)
 create mode 100644 ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
 create mode 100644 ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
new file mode 100644
index 0000000..0a43ff1
--- /dev/null
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -0,0 +1,250 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k4_frac_cc_sky130nm.xml
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+     - Skywater 130nm PDK
+       - circuit models are binded to the opensource skywater
+         foundry middle-speed (ms) standard cell library
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" lib_name="A" size="1"/>
+      <port type="output" prefix="out" lib_name="Y" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" lib_name="A" size="1"/>
+      <port type="output" prefix="out" lib_name="X" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" lib_name="A" size="1"/>
+      <port type="output" prefix="out" lib_name="X" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
+      <design_technology type="cmos" topology="buffer" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" lib_name="A" size="1"/>
+      <port type="output" prefix="out" lib_name="Y" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
+      <design_technology type="cmos" topology="OR"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" lib_name="A" size="1"/>
+      <port type="input" prefix="b" lib_name="B" size="1"/>
+      <port type="output" prefix="out" lib_name="X" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <!-- Define a circuit model for the standard cell MUX2
+         OpenFPGA requires the following truth table for the MUX2
+         When the select signal sel is enabled, the first input, i.e., in0
+         will be propagated to the output, i.e., out
+         If your standard cell provider does not offer the exact truth table,
+         you can simply swap the inputs as shown in the example below
+      -->
+    <circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
+      <design_technology type="cmos" topology="MUX2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in0" lib_name="A1" size="1"/>
+      <port type="input" prefix="in1" lib_name="A0" size="1"/>
+      <port type="input" prefix="sel" lib_name="S" size="1"/>
+      <port type="output" prefix="out" lib_name="X" size="1"/>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
+      <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/>
+      <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
+      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxbp_1" prefix="sky130_fd_sc_hd__sdfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
+      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
+      <port type="input" prefix="D" size="1"/>
+      <port type="input" prefix="DI" lib_name="SCD" size="1"/>
+      <port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
+      <!-- <port type="input" prefix="reset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true"/> -->
+      <port type="output" prefix="Q" size="1"/>
+      <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
+      <lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
+      <lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
+      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
+      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
+      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="16"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sky130_fd_sc_hd__dfxbp_1" prefix="sky130_fd_sc_hd__dfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
+      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
+      <port type="input" prefix="D" size="1"/>
+      <port type="output" prefix="Q" size="1"/>
+      <port type="output" prefix="Q_N" size="1"/>
+      <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIN" prefix="GPIN" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
+      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
+      <port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" />
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
+      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
+      <port type="inout" prefix="PAD" lib_name="Y" size="1" is_global="true" is_io="true" />
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" num_regions="1"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
+    <switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
+    <switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L1" circuit_model_name="chan_segment"/>
+    <segment name="L2" circuit_model_name="chan_segment"/>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="gp_inpad.inpad" circuit_model_name="GPIN"/>
+    <pb_type name="gp_outpad.outpad" circuit_model_name="GPOUT"/>
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfxbp_1"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:2]"/>
+      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble4' -->
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- Binding operating pb_types in mode 'shift_register' -->
+    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
new file mode 100644
index 0000000..4a0f049
--- /dev/null
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
@@ -0,0 +1,646 @@
+<!-- 
+  Low-cost homogeneous FPGA Architecture.
+
+  - Skywater 130 nm technology
+  - General purpose logic block: 
+    K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture:
+      - 10% L = 1, fc_in = 0.15, Fc_out = 0.10
+      - 10% L = 2, fc_in = 0.15, Fc_out = 0.10
+      - 80% L = 4, fc_in = 0.15, Fc_out = 0.10
+      - 100 routing tracks per channel
+
+  Authors: Xifan Tang
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut4">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut3_out"/>
+        <port name="lut4_out"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
+    <model name="scff">
+      <input_ports>
+        <port name="D" clock="clk"/>
+        <port name="DI" clock="clk"/>
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="gp_inpad" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="gp_inpad"/>
+      </equivalent_sites>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">gp_inpad.inpad</loc>
+        <loc side="top">gp_inpad.inpad</loc>
+        <loc side="right">gp_inpad.inpad</loc>
+        <loc side="bottom">gp_inpad.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="gp_outpad" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="gp_outpad"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">gp_outpad.outpad</loc>
+        <loc side="top">gp_outpad.outpad</loc>
+        <loc side="right">gp_outpad.outpad</loc>
+        <loc side="bottom">gp_outpad.outpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I0" num_pins="3" equivalent="full"/>
+      <input name="I0i" num_pins="1" equivalent="none"/>
+      <input name="I1" num_pins="3" equivalent="full"/>
+      <input name="I1i" num_pins="1" equivalent="none"/>
+      <input name="I2" num_pins="3" equivalent="full"/>
+      <input name="I2i" num_pins="1" equivalent="none"/>
+      <input name="I3" num_pins="3" equivalent="full"/>
+      <input name="I3i" num_pins="1" equivalent="none"/>
+      <input name="I4" num_pins="3" equivalent="full"/>
+      <input name="I4i" num_pins="1" equivalent="none"/>
+      <input name="I5" num_pins="3" equivalent="full"/>
+      <input name="I5i" num_pins="1" equivalent="none"/>
+      <input name="I6" num_pins="3" equivalent="full"/>
+      <input name="I6i" num_pins="1" equivalent="none"/>
+      <input name="I7" num_pins="3" equivalent="full"/>
+      <input name="I7i" num_pins="1" equivalent="none"/>
+      <input name="regin" num_pins="1"/>
+      <input name="scin" num_pins="1"/>
+      <output name="O" num_pins="16" equivalent="none"/>
+      <output name="regout" num_pins="1"/>
+      <output name="scout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="regin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="regout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="scin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="scout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.regin clb.scin</loc>
+        <loc side="right">clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i </loc>
+        <loc side="bottom">clb.regout clb.scout clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <auto_layout aspect_ratio="1.0">
+      <!-- On each side, general-purpose inpad and outpad are interleaved -->
+      <!-- On top side, I/Os are organized as inpad, outpad, inpad, outpad, ... -->
+      <region type="gp_inpad" priority="100" startx="1" endx="W-1" incrx="2" starty="H-1" endy="H-1"/>
+      <region type="gp_outpad" priority="100" startx="2" endx="W-1" incrx="2" starty="H-1" endy="H-1"/>
+      <!-- On right side, I/Os are organized as 
+           inpad 
+           outpad
+           ...
+           inpad
+           outpad
+           This is to avoid unroutable conditions when FPGA size is too small (only gp_inpad is available)
+           -->
+      <region type="gp_outpad" priority="100" startx="W-1" endx="W-1" starty="1" endy="H-1" incry="2"/>
+      <region type="gp_inpad" priority="100" startx="W-1" endx="W-1" starty="2" endy="H-1" incry="2"/>
+      <!-- On top side, I/Os are organized as inpad, outpad, inpad, outpad, ... -->
+      <region type="gp_inpad" priority="100" startx="1" endx="W-1" incrx="2" starty="0" endy="0"/>
+      <region type="gp_outpad" priority="100" startx="2" endx="W-1" incrx="2" starty="0" endy="0"/>
+      <corners type="EMPTY" priority="101"/>
+      <!-- On left side, I/Os are organized as 
+           inpad 
+           outpad
+           ...
+           inpad
+           outpad
+           This is to avoid unroutable conditions when FPGA size is too small (only gp_inpad is available)
+           -->
+      <region type="gp_outpad" priority="100" startx="0" endx="0" starty="1" endy="H-1" incry="2"/>
+      <region type="gp_inpad" priority="100" startx="0" endx="0" starty="2" endy="H-1" incry="2"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
+    <fixed_layout name="2x2" width="4" height="4">
+      <!-- On each side, general-purpose inpad and outpad are interleaved -->
+      <!-- On top side, I/Os are organized as inpad, outpad, inpad, outpad, ... -->
+      <region type="gp_inpad" priority="100" startx="1" endx="W-1" incrx="2" starty="H-1" endy="H-1"/>
+      <region type="gp_outpad" priority="100" startx="2" endx="W-1" incrx="2" starty="H-1" endy="H-1"/>
+      <!-- On right side, I/Os are organized as 
+           inpad 
+           outpad
+           ...
+           inpad
+           outpad
+           This is to avoid unroutable conditions when FPGA size is too small (only gp_inpad is available)
+           -->
+      <region type="gp_outpad" priority="100" startx="W-1" endx="W-1" starty="1" endy="H-1" incry="2"/>
+      <region type="gp_inpad" priority="100" startx="W-1" endx="W-1" starty="2" endy="H-1" incry="2"/>
+      <!-- On top side, I/Os are organized as inpad, outpad, inpad, outpad, ... -->
+      <region type="gp_inpad" priority="100" startx="1" endx="W-1" incrx="2" starty="0" endy="0"/>
+      <region type="gp_outpad" priority="100" startx="2" endx="W-1" incrx="2" starty="0" endy="0"/>
+      <corners type="EMPTY" priority="101"/>
+      <!-- On left side, I/Os are organized as 
+           inpad 
+           outpad
+           ...
+           inpad
+           outpad
+           This is to avoid unroutable conditions when FPGA size is too small (only gp_inpad is available)
+           -->
+      <region type="gp_outpad" priority="100" startx="0" endx="0" starty="1" endy="H-1" incry="2"/>
+      <region type="gp_inpad" priority="100" startx="0" endx="0" starty="2" endy="H-1" incry="2"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="L1_mux"/>
+      <sb type="pattern">1 1</sb>
+      <cb type="pattern">1</cb>
+    </segment>
+    <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="L2_mux"/>
+      <sb type="pattern">1 1 1</sb>
+      <cb type="pattern">1 1</cb>
+    </segment>
+    <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="L4_mux"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="shift_register" from_pin="clb.regout" to_pin="clb.regin" x_offset="0" y_offset="-1" z_offset="0"/>
+    <direct name="scan_chain" from_pin="clb.scout" to_pin="clb.scin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Different from GPIOs, embedded I/O interfaces can afford splitting
+         input and output pin. Therefore, the input pad and output pad are defined
+         as different blocks
+	   -->
+    <!-- Define input pads begin -->
+    <pb_type name="gp_inpad">
+      <output name="inpad" num_pins="1"/>
+      <pb_type name="inpad" blif_model=".input" num_pb="1">
+        <output name="inpad" num_pins="1"/>
+      </pb_type>
+      <interconnect>
+        <direct name="inpad" input="inpad.inpad" output="gp_inpad.inpad">
+          <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="gp_inpad.inpad"/>
+        </direct>
+      </interconnect>
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define input pads end -->
+    <!-- Define output pads begin -->
+    <pb_type name="gp_outpad">
+      <input name="outpad" num_pins="1"/>
+      <pb_type name="outpad" blif_model=".output" num_pb="1">
+        <input name="outpad" num_pins="1"/>
+      </pb_type>
+      <interconnect>
+        <direct name="outpad" input="gp_outpad.outpad" output="outpad.outpad">
+          <delay_constant max="1.394e-11" in_port="gp_outpad.outpad" out_port="outpad.outpad"/>
+        </direct>
+      </interconnect>
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define output pads end -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!-- -Due to the absence of local routing, 
+         the 4 inputs of fracturable LUT4 are no longer equivalent, 
+         because the 4th input can not be switched when the dual-LUT3 modes are used.
+         So pin equivalence should be applied to the first 3 inputs only
+	  -->
+    <pb_type name="clb">
+      <input name="I0" num_pins="3" equivalent="full"/>
+      <input name="I0i" num_pins="1" equivalent="none"/>
+      <input name="I1" num_pins="3" equivalent="full"/>
+      <input name="I1i" num_pins="1" equivalent="none"/>
+      <input name="I2" num_pins="3" equivalent="full"/>
+      <input name="I2i" num_pins="1" equivalent="none"/>
+      <input name="I3" num_pins="3" equivalent="full"/>
+      <input name="I3i" num_pins="1" equivalent="none"/>
+      <input name="I4" num_pins="3" equivalent="full"/>
+      <input name="I4i" num_pins="1" equivalent="none"/>
+      <input name="I5" num_pins="3" equivalent="full"/>
+      <input name="I5i" num_pins="1" equivalent="none"/>
+      <input name="I6" num_pins="3" equivalent="full"/>
+      <input name="I6i" num_pins="1" equivalent="none"/>
+      <input name="I7" num_pins="3" equivalent="full"/>
+      <input name="I7i" num_pins="1" equivalent="none"/>
+      <input name="regin" num_pins="1"/>
+      <input name="scin" num_pins="1"/>
+      <output name="O" num_pins="16" equivalent="none"/>
+      <output name="regout" num_pins="1"/>
+      <output name="scout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="8">
+        <input name="in" num_pins="4"/>
+        <input name="regin" num_pins="1"/>
+        <input name="scin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="regout" num_pins="1"/>
+        <output name="scout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <input name="regin" num_pins="1"/>
+            <input name="scin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="regout" num_pins="1"/>
+            <output name="scout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
+                <input name="in" num_pins="4"/>
+                <output name="lut3_out" num_pins="2"/>
+                <output name="lut4_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
+                <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop with scan-chain capability, DI is the scan-chain data input -->
+            <pb_type name="ff" blif_model=".subckt scff" num_pb="2">
+              <input name="D" num_pins="1"/>
+              <input name="DI" num_pins="1"/>
+              <output name="Q" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_setup value="66e-12" port="ff.DI" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="fabric.scin" output="ff[0].DI"/>
+              <direct name="direct3" input="ff[0].Q" output="ff[1].DI"/>
+              <direct name="direct4" input="ff[1].Q" output="fabric.scout"/>
+              <direct name="direct5" input="ff[1].Q" output="fabric.regout"/>
+              <direct name="direct6" input="frac_logic.out[1:1]" output="ff[1:1].D"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="frac_logic.out[0:0] fabric.regin" output="ff[0:0].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
+                <delay_constant max="45e-12" in_port="fabric.regin" out_port="ff[0:0].D"/>
+              </mux>
+              <mux name="mux2" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux3" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct3" input="fle.regin" output="fabric.regin"/>
+            <direct name="direct4" input="fle.scin" output="fabric.scin"/>
+            <direct name="direct5" input="fabric.out" output="fle.out"/>
+            <direct name="direct7" input="fabric.regout" output="fle.regout"/>
+            <direct name="direct8" input="fabric.scout" output="fle.scout"/>
+            <direct name="direct9" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 3-LUT mode definition begin -->
+        <mode name="n2_lut3">
+          <pb_type name="lut3inter" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble3" num_pb="2">
+              <input name="in" num_pins="3"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="3" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
+                <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
+              <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
+              <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
+              <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
+            <direct name="direct2" input="lut3inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 3-LUT mode definition end -->
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 4-LUT mode definition end -->
+        <!-- Define shift register begin -->
+        <mode name="shift_register">
+          <pb_type name="shift_reg" num_pb="1">
+            <input name="regin" num_pins="1"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="shift_reg.regin" output="ff[0].D"/>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
+              <direct name="direct3" input="ff[1].Q" output="shift_reg.regout"/>
+              <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.regin" output="shift_reg.regin"/>
+            <direct name="direct2" input="shift_reg.regout" output="fle.regout"/>
+            <direct name="direct3" input="fle.clk" output="shift_reg.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define shift register end --> 
+      </pb_type>
+      <interconnect>
+        <!-- We use direct connections to reduce the area to the most
+             The global local routing is going to compensate the loss in routability
+          -->
+        <direct name="direct_fle0" input="clb.I0" output="fle[0:0].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle1" input="clb.I1" output="fle[1:1].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle2" input="clb.I2" output="fle[2:2].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle3" input="clb.I3" output="fle[3:3].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle4" input="clb.I4" output="fle[4:4].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle5" input="clb.I5" output="fle[5:5].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle6" input="clb.I6" output="fle[6:6].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle7" input="clb.I7" output="fle[7:7].in[0:2]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">
+          <!-- TODO: Timing should be backannotated from post-PnR results -->
+        </direct>
+        <complete name="clks" input="clb.clk" output="fle[7:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[3:0].out[0:1]" output="clb.O[7:0]"/>
+        <direct name="clbouts2" input="fle[7:4].out[0:1]" output="clb.O[15:8]"/>
+        <!-- Shift register chain links -->
+        <direct name="shift_register_in" input="clb.regin" output="fle[0:0].regin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
+          <!--pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/-->
+        </direct>
+        <direct name="shift_register_out" input="fle[7:7].regout" output="clb.regout">
+          <!--pack_pattern name="chain" in_port="fle[7:7].regout" out_port="clb.regout"/-->
+        </direct>
+        <direct name="shift_register_link" input="fle[6:0].regout" output="fle[7:1].regin">
+          <!--pack_pattern name="chain" in_port="fle[6:0].regout" out_port="fle[7:1].regin"/-->
+        </direct>
+        <!-- Scan chain links -->
+        <direct name="scan_chain_in" input="clb.scin" output="fle[0:0].scin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.scin" out_port="fle[0:0].scin"/>
+        </direct>
+        <direct name="scan_chain_out" input="fle[7:7].scout" output="clb.scout">
+        </direct>
+        <direct name="scan_chain_link" input="fle[6:0].scout" output="fle[7:1].scin">
+        </direct>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From 0958d9c50f505b9112d3bed05862330a7fe730e5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 2 Nov 2020 20:09:35 -0700
Subject: [PATCH 05/14] [Script] Add openfpga task run for embedded
 architecture

---
 .../generate_fabric/config/task_template.conf | 37 +++++++++++++++++++
 .../generate_sdc/config/task_template.conf    | 36 ++++++++++++++++++
 .../config/task_template.conf                 | 37 +++++++++++++++++++
 3 files changed, 110 insertions(+)
 create mode 100644 SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_fabric/config/task_template.conf
 create mode 100644 SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_sdc/config/task_template.conf
 create mode 100644 SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_testbench/config/task_template.conf

diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_fabric/config/task_template.conf
new file mode 100644
index 0000000..b02676b
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_fabric/config/task_template.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc
+openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_sdc/config/task_template.conf
new file mode 100644
index 0000000..9d1bbfa
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_sdc/config/task_template.conf
@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_testbench/config/task_template.conf
new file mode 100644
index 0000000..ecb57ea
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_testbench/config/task_template.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc
+openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=

From b67896a225e1b11c2bcec72170dcfd4900be91b3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 3 Nov 2020 09:05:20 -0700
Subject: [PATCH 06/14] [HDL] Add embedded I/O HDL wrapper using the high
 density cells

---
 PDK/sc_verilog/std_cell_extract.v | 37 ++++++++++++++++++++++---------
 1 file changed, 26 insertions(+), 11 deletions(-)

diff --git a/PDK/sc_verilog/std_cell_extract.v b/PDK/sc_verilog/std_cell_extract.v
index be56f7f..5267d22 100644
--- a/PDK/sc_verilog/std_cell_extract.v
+++ b/PDK/sc_verilog/std_cell_extract.v
@@ -1,16 +1,5 @@
 `timescale 1ns/1ps
 
-//
-//
-//
-//
-//
-//
-
-//
-//
-//
-
 module GPIO (A, IE, OE, Y, in, out, mem_out);
     output A;
     output IE;
@@ -27,3 +16,29 @@ module GPIO (A, IE, OE, Y, in, out, mem_out);
         .A	(mem_out),
         .Y	(OE) );
 endmodule
+
+//-----------------------------------------------------
+// Function    : A minimum input pad
+//-----------------------------------------------------
+module GPIN (
+  inout A, // External PAD signal
+  output Y // Data input
+);
+  // Assume a 4x buf is enough to drive the global routing
+  sky130_fd_sc_hd__buf_4 in_buf (
+        .A	(A),
+        .X	(Y) );
+endmodule
+
+//-----------------------------------------------------
+// Function    : A minimum output pad
+//-----------------------------------------------------
+module GPOUT (
+  inout Y, // External PAD signal
+  input A // Data output
+);
+  // Assume a 4x buf is enough to drive the block outside FPGA
+  sky130_fd_sc_hd__buf_4 in_buf (
+        .A	(A),
+        .X	(Y) );
+endmodule

From 40ca8dfbe32effe75cc63f5f774edbbe32d419d2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 3 Nov 2020 09:14:47 -0700
Subject: [PATCH 07/14] [Arch] Update architecture files to use the wrapper
 files

---
 ..._scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml | 4 ++--
 ..._N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
index 0a43ff1..5810d79 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -183,14 +183,14 @@
       <port type="output" prefix="Q_N" size="1"/>
       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="GPIN" prefix="GPIN" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
+    <circuit_model type="iopad" name="GPIN" prefix="GPIN" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" />
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
+    <circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
index e4b1313..16707e5 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
@@ -184,7 +184,7 @@
       <port type="output" prefix="Q_N" size="1"/>
       <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/sc_verilog/std_cell_extract.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>

From b5c781f555c700267dd67e38e649df654c4a0be3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 3 Nov 2020 09:17:22 -0700
Subject: [PATCH 08/14] [Arch] Patch the HDL netlist name to differetiate
 between cell types

---
 ..._scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml | 4 ++--
 ..._N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
index 5810d79..9e99389 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -183,14 +183,14 @@
       <port type="output" prefix="Q_N" size="1"/>
       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="GPIN" prefix="GPIN" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io.v">
+    <circuit_model type="iopad" name="GPIN" prefix="GPIN" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" />
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io.v">
+    <circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
index 16707e5..9cd985a 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
@@ -184,7 +184,7 @@
       <port type="output" prefix="Q_N" size="1"/>
       <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="GPIO" prefix="GPIO" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>

From 12881d7a311d0da0e7594be2a41b34710cda40ad Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 3 Nov 2020 09:19:43 -0700
Subject: [PATCH 09/14] [HDL] Move verilog wrapper to HDL directory

---
 PDK/sc_verilog/std_cell_extract.v => HDL/common/digital_io_hd.v | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename PDK/sc_verilog/std_cell_extract.v => HDL/common/digital_io_hd.v (100%)

diff --git a/PDK/sc_verilog/std_cell_extract.v b/HDL/common/digital_io_hd.v
similarity index 100%
rename from PDK/sc_verilog/std_cell_extract.v
rename to HDL/common/digital_io_hd.v

From 8702073354c35fa4917f38630f377297a93a3290 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 3 Nov 2020 09:23:33 -0700
Subject: [PATCH 10/14] [Doc] Add readme for HDL directory

---
 HDL/README.md | 4 ++++
 1 file changed, 4 insertions(+)
 create mode 100644 HDL/README.md

diff --git a/HDL/README.md b/HDL/README.md
new file mode 100644
index 0000000..3ec3d31
--- /dev/null
+++ b/HDL/README.md
@@ -0,0 +1,4 @@
+# Skywater PDK
+This directory contains the HDL netlists for FPGA fabrics that are automatically generated by OpenFPGA.
+It also includes necessary wrappers to enable the netlist generation.
+The custom netlists are place in the `common` directory.

From a46d1bd49248ca9b1f9eecb411dfc8045d2fdd2e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 3 Nov 2020 09:27:06 -0700
Subject: [PATCH 11/14] [Doc] Add README to SDC and Testbench directories

---
 SDC/README.md       | 5 +++++
 TESTBENCH/README.md | 5 +++++
 2 files changed, 10 insertions(+)
 create mode 100644 SDC/README.md
 create mode 100644 TESTBENCH/README.md

diff --git a/SDC/README.md b/SDC/README.md
new file mode 100644
index 0000000..d4fa921
--- /dev/null
+++ b/SDC/README.md
@@ -0,0 +1,5 @@
+# Skywater PDK
+This directory contains the design constraints for FPGA fabrics that are automatically generated by OpenFPGA or tuned for a specific FPGA fabric.
+Please keep this directory clean and organize as follows:
+- Each set of design constraints should be placed in a separated directory
+- READMD is the only file allowed in the directory, others should be sub-directories.
diff --git a/TESTBENCH/README.md b/TESTBENCH/README.md
new file mode 100644
index 0000000..5b27814
--- /dev/null
+++ b/TESTBENCH/README.md
@@ -0,0 +1,5 @@
+# Skywater PDK
+This directory contains the testbenches for FPGA fabrics that are automatically generated by OpenFPGA or tuned for a specific FPGA fabric.
+Please keep this directory clean and organize as follows:
+- Each testbench should be placed in a separated directory
+- READMD is the only file allowed in the directory, others should be sub-directories.

From 533a6ab90f09168daa781ef1ad27d90c1a34f9af Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 3 Nov 2020 09:53:16 -0700
Subject: [PATCH 12/14] [Arch] Use an exact fit scan-chain flip-flop in the
 architectures

---
 ...can_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
index 9e99389..5e1045d 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -148,7 +148,7 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxbp_1" prefix="sky130_fd_sc_hd__sdfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v">
+    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxtp_1" prefix="sky130_fd_sc_hd__sdfxtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxtp_1.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
@@ -181,7 +181,7 @@
       <port type="input" prefix="D" size="1"/>
       <port type="output" prefix="Q" size="1"/>
       <port type="output" prefix="Q_N" size="1"/>
-      <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
+      <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
     <circuit_model type="iopad" name="GPIN" prefix="GPIN" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
       <design_technology type="cmos"/>
@@ -228,7 +228,7 @@
     <!-- physical mode will be the default mode if not specified -->
     <pb_type name="clb.fle" physical_mode_name="physical"/>
     <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfxbp_1"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfxtp_1"/>
     <!-- Binding operating pb_type to physical pb_type -->
     <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
       <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

From 48d8f8b664b5d9e8f07a5cd100108d72366acc98 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 3 Nov 2020 09:54:30 -0700
Subject: [PATCH 13/14] [Arch] Same patch on the scff on another arch

---
 ..._N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
index 9cd985a..590c34d 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
@@ -148,7 +148,7 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxbp_1" prefix="sky130_fd_sc_hd__sdfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v">
+    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxtp_1" prefix="sky130_fd_sc_hd__sdfxtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxtp_1.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
@@ -233,7 +233,7 @@
     </pb_type>
     <pb_type name="clb.fle" physical_mode_name="physical"/>
     <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfxbp_1"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfxtp_1"/>
     <!-- Binding operating pb_type to physical pb_type -->
     <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
       <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

From 1264054caba03f6497c43c8fe19ccb42530d8e7f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 3 Nov 2020 09:57:25 -0700
Subject: [PATCH 14/14] [Arch] Bug fix in netlist path

---
 ...er_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml | 2 +-
 ...ac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
index 5e1045d..186a4d1 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -148,7 +148,7 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxtp_1" prefix="sky130_fd_sc_hd__sdfxtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxtp_1.v">
+    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxtp_1" prefix="sky130_fd_sc_hd__sdfxtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
index 590c34d..6242733 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
@@ -148,7 +148,7 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxtp_1" prefix="sky130_fd_sc_hd__sdfxtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxtp_1.v">
+    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxtp_1" prefix="sky130_fd_sc_hd__sdfxtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>