diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
new file mode 100644
index 0000000..186a4d1
--- /dev/null
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -0,0 +1,250 @@
+
+
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+ 10e-12
+
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+ 10e-12
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+
+
+ 10e-12
+
+
+ 10e-12
+
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+ 10e-12
+
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+ 10e-12
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+ 10e-12
+
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+ 10e-12
+
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+ 10e-12 5e-12
+
+
+ 10e-12 5e-12
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diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
index ae31d83..6242733 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
@@ -31,7 +31,7 @@
-
+
@@ -43,7 +43,7 @@
10e-12
-
+
@@ -55,7 +55,7 @@
10e-12
-
+
@@ -67,7 +67,7 @@
10e-12
-
+
@@ -79,7 +79,7 @@
10e-12
-
+
@@ -101,7 +101,7 @@
If your standard cell provider does not offer the exact truth table,
you can simply swap the inputs as shown in the example below
-->
-
+
@@ -148,7 +148,7 @@
-
+
@@ -174,7 +174,7 @@
-
+
@@ -184,7 +184,7 @@
-
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@@ -233,7 +233,7 @@
-
+
diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
new file mode 100644
index 0000000..4a0f049
--- /dev/null
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
@@ -0,0 +1,646 @@
+
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+ gp_inpad.inpad
+ gp_inpad.inpad
+ gp_inpad.inpad
+ gp_inpad.inpad
+
+
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+
+
+ gp_outpad.outpad
+ gp_outpad.outpad
+ gp_outpad.outpad
+ gp_outpad.outpad
+
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+ clb.clk
+ clb.regin clb.scin
+ clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i
+ clb.regout clb.scout clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i
+
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+ 1
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+ 1 1
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+ 1 1 1 1 1
+ 1 1 1 1
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+ 235e-12
+ 235e-12
+ 235e-12
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+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
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diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
index 5d865fd..1d28d35 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
@@ -78,14 +78,22 @@
-
-
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@@ -102,8 +110,8 @@
clb.clk
clb.regin clb.scin
- clb.O[7:0] clb.I0 clb.I1 clb.I2 clb.I3
- clb.regout clb.scout clb.O[15:8] clb.I4 clb.I5 clb.I6 clb.I7
+ clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i
+ clb.regout clb.scout clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i
@@ -276,24 +284,28 @@
-
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@@ -534,30 +546,56 @@
-
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diff --git a/HDL/README.md b/HDL/README.md
new file mode 100644
index 0000000..3ec3d31
--- /dev/null
+++ b/HDL/README.md
@@ -0,0 +1,4 @@
+# Skywater PDK
+This directory contains the HDL netlists for FPGA fabrics that are automatically generated by OpenFPGA.
+It also includes necessary wrappers to enable the netlist generation.
+The custom netlists are place in the `common` directory.
diff --git a/HDL/common/digital_io_hd.v b/HDL/common/digital_io_hd.v
new file mode 100644
index 0000000..5267d22
--- /dev/null
+++ b/HDL/common/digital_io_hd.v
@@ -0,0 +1,44 @@
+`timescale 1ns/1ps
+
+module GPIO (A, IE, OE, Y, in, out, mem_out);
+ output A;
+ output IE;
+ output OE;
+ output Y;
+ input in;
+ output out;
+ input mem_out;
+
+ assign A = in;
+ assign out = Y;
+ assign IE = mem_out;
+ sky130_fd_sc_hd__inv_1 ie_oe_inv (
+ .A (mem_out),
+ .Y (OE) );
+endmodule
+
+//-----------------------------------------------------
+// Function : A minimum input pad
+//-----------------------------------------------------
+module GPIN (
+ inout A, // External PAD signal
+ output Y // Data input
+);
+ // Assume a 4x buf is enough to drive the global routing
+ sky130_fd_sc_hd__buf_4 in_buf (
+ .A (A),
+ .X (Y) );
+endmodule
+
+//-----------------------------------------------------
+// Function : A minimum output pad
+//-----------------------------------------------------
+module GPOUT (
+ inout Y, // External PAD signal
+ input A // Data output
+);
+ // Assume a 4x buf is enough to drive the block outside FPGA
+ sky130_fd_sc_hd__buf_4 in_buf (
+ .A (A),
+ .X (Y) );
+endmodule
diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_fabric/config/task_template.conf
new file mode 100644
index 0000000..b02676b
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_fabric/config/task_template.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc
+openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_sdc/config/task_template.conf
new file mode 100644
index 0000000..9d1bbfa
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_sdc/config/task_template.conf
@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_testbench/config/task_template.conf
new file mode 100644
index 0000000..ecb57ea
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_testbench/config/task_template.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc
+openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SDC/README.md b/SDC/README.md
new file mode 100644
index 0000000..d4fa921
--- /dev/null
+++ b/SDC/README.md
@@ -0,0 +1,5 @@
+# Skywater PDK
+This directory contains the design constraints for FPGA fabrics that are automatically generated by OpenFPGA or tuned for a specific FPGA fabric.
+Please keep this directory clean and organize as follows:
+- Each set of design constraints should be placed in a separated directory
+- READMD is the only file allowed in the directory, others should be sub-directories.
diff --git a/TESTBENCH/README.md b/TESTBENCH/README.md
new file mode 100644
index 0000000..5b27814
--- /dev/null
+++ b/TESTBENCH/README.md
@@ -0,0 +1,5 @@
+# Skywater PDK
+This directory contains the testbenches for FPGA fabrics that are automatically generated by OpenFPGA or tuned for a specific FPGA fabric.
+Please keep this directory clean and organize as follows:
+- Each testbench should be placed in a separated directory
+- READMD is the only file allowed in the directory, others should be sub-directories.