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[HDL] Rename por of I/O cell to be consistent with documentation

This commit is contained in:
tangxifan 2020-11-17 19:33:53 -07:00
parent b1ce66e8ce
commit 8803b30b26
1 changed files with 2 additions and 2 deletions
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4
HDL/common/digital_io_hd.v
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@ -28,10 +28,10 @@ module EMBEDDED_IO_HD (
output FPGA_IN, // Input data to FPGA output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA input FPGA_OUT, // Output data from FPGA
input FPGA_DIR, // direction control input FPGA_DIR, // direction control
input ISOL_N // Isolation enable signal input IO_ISOL_N // Isolation enable signal
); );
sky130_fd_sc_hd__and2_0 ISOL_EN_GATE (.A(ISOL_N), sky130_fd_sc_hd__and2_0 ISOL_EN_GATE (.A(IO_ISOL_N),
.B(FPGA_DIR), .B(FPGA_DIR),
.X(SOC_DIR) .X(SOC_DIR)
); );