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[CI] Add wrapper generator examples to CI

This commit is contained in:
tangxifan 2020-12-01 11:32:27 -07:00
parent 0eb1b68bee
commit 83bd343f70
1 changed files with 5 additions and 0 deletions
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5
.github/workflows/quick_test.sh vendored
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@ -12,6 +12,11 @@ set -e
# - Run FPGA tasks to validate netlist generations # - Run FPGA tasks to validate netlist generations
python3 SCRIPT/repo_setup.py --openfpga_root_path ./OpenFPGA python3 SCRIPT/repo_setup.py --openfpga_root_path ./OpenFPGA
##############################################
# Generate wrapper HDL codes to bridge Caravel I/Os and FPGA I/Os
python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.0.v
python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.1.v
############################################## ##############################################
# Generate post-PnR testbenches # Generate post-PnR testbenches
python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json