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[HDL] Digital I/O of embedded FPGA is now lib independent

This commit is contained in:
tangxifan 2020-11-13 10:00:30 -07:00
parent be33082faf
commit 80655c5869
1 changed files with 2 additions and 8 deletions
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10
HDL/common/digital_io_hd.v
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@ -24,10 +24,7 @@ module GPIN (
inout A, // External PAD signal inout A, // External PAD signal
output Y // Data input output Y // Data input
); );
// Assume a 4x buf is enough to drive the global routing assign Y = A;
sky130_fd_sc_hd__buf_4 in_buf (
.A (A),
.X (Y) );
endmodule endmodule
//----------------------------------------------------- //-----------------------------------------------------
@ -37,10 +34,7 @@ module GPOUT (
inout Y, // External PAD signal inout Y, // External PAD signal
input A // Data output input A // Data output
); );
// Assume a 4x buf is enough to drive the block outside FPGA assign Y = A;
sky130_fd_sc_hd__buf_4 in_buf (
.A (A),
.X (Y) );
endmodule endmodule
//----------------------------------------------------- //-----------------------------------------------------