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Merge remote-tracking branch 'origin/master' into ganesh_dev

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Ganesh Gore 2020-11-22 16:37:36 -07:00
parent c54cdcd3ef 36a512123a
commit 8053d7e626
62 changed files with 338559 additions and 943 deletions
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4
BENCHMARK/and2_or2/and2_or2.act Normal file
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a 0.5 0.5
b 0.5 0.5
c 0.25 0.25
d 0.25 0.25

11
BENCHMARK/and2_or2/and2_or2.blif Normal file
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.model and2_or2
.inputs a b
.outputs c d
.names a b c
11 1
.names a b d
00 0
.end

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BENCHMARK/and2_or2/and2_or2.v Normal file
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/////////////////////////////////////////
// Functionality: 2-input AND + 2-input OR
// This benchmark is designed to test fracturable LUTs
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module and2_or2(
a,
b,
c,
d);
input wire a;
input wire b;
output wire c;
output wire d;
assign c = a & b;
assign d = a | b;
endmodule

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BENCHMARK/bin2bcd/bin2bcd.v Normal file
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//-------------------------------------------------------------------
// Function: Binary to Decimal converter
// Source:
// https://verilogcodes.blogspot.com/2015/10/verilog-code-for-8-bit-binary-to-bcd.html
//-------------------------------------------------------------------
module bin2bcd(
bin,
bcd
);
//input ports and their sizes
input [7:0] bin;
//output ports and, their size
output [11:0] bcd;
//Internal variables
reg [11 : 0] bcd;
reg [3:0] i;
//Always block - implement the Double Dabble algorithm
always @(bin)
begin
bcd = 0; //initialize bcd to zero.
for (i = 0; i < 8; i = i+1) //run for 8 iterations
begin
bcd = {bcd[10:0],bin[7-i]}; //concatenation
//if a hex digit of 'bcd' is more than 4, add 3 to it.
if(i < 7 && bcd[3:0] > 4)
bcd[3:0] = bcd[3:0] + 3;
if(i < 7 && bcd[7:4] > 4)
bcd[7:4] = bcd[7:4] + 3;
if(i < 7 && bcd[11:8] > 4)
bcd[11:8] = bcd[11:8] + 3;
end
end
endmodule

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BENCHMARK/bin2bcd/bin2bcd_tb.v Normal file
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//-------------------------------------------------------------------
// Function: Testbench for the Binary to Decimal converter
// Source:
// https://verilogcodes.blogspot.com/2015/10/verilog-code-for-8-bit-binary-to-bcd.html
module tb_bin2bcd;
// Input
reg [7:0] bin;
// Output
wire [11:0] bcd;
// Extra variables
reg [8:0] i;
// Instantiate the Unit Under Test (UUT)
bin2bcd uut (
.bin(bin),
.bcd(bcd)
);
//Simulation - Apply inputs
initial begin
//A for loop for checking all the input combinations.
for(i=0;i<256;i=i+1)
begin
bin = i;
#10; //wait for 10 ns.
end
$finish; //system function for stoping the simulation.
end
endmodule

18
BENCHMARK/counter/counter.v
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@ -1,16 +1,16 @@
module counter(clk_counter, q_counter, rst_counter);
module counter(clk, q, rst);
input clk_counter;
input rst_counter;
output [7:0] q_counter;
reg [7:0] q_counter;
input clk;
input rst;
output [7:0] q;
reg [7:0] q;
always @ (posedge clk_counter)
always @ (posedge clk)
begin
if(rst_counter)
q_counter <= 8'b00000000;
if(rst)
q <= 8'b00000000;
else
q_counter <= q_counter + 1;
q <= q + 1;
end
endmodule

10
BENCHMARK/routing_test/routing_test.act Executable file
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IN0 0.505000 0.204400
IN1 0.491000 0.206000
IN2 0.472000 0.204400
clk 0.500000 2.000000
OUT1 0.491000 0.206000
OUT0 0.505000 0.204400
OUT2 0.472000 0.204400
n15 0.491000 0.101146
n18 0.505000 0.103222
n21 0.472000 0.096477

16
BENCHMARK/routing_test/routing_test.blif Executable file
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# Benchmark "routing_test" written by ABC on Tue Apr 21 18:25:21 2020
.model routing_test
.inputs IN0 IN1 IN2 clk
.outputs OUT0 OUT1 OUT2
.latch n15 OUT1 re clk 2
.latch n18 OUT0 re clk 2
.latch n21 OUT2 re clk 2
.names IN1 n15
1 1
.names IN0 n18
1 1
.names IN2 n21
1 1
.end

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BENCHMARK/routing_test/routing_test.v Normal file
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module routing_test(IN0,IN1,IN2, clk, OUT0,OUT1,OUT2);
input wire IN0,IN1,IN2,clk;
output reg OUT0, OUT1, OUT2;
always @(posedge clk)
begin
OUT0 <= IN0;
OUT1 <= IN1;
OUT2 <= IN2;
end
endmodule

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BENCHMARK/rs_decoder/rtl/rs_decoder.v Normal file
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4
BENCHMARK/simon_bit_serial/README.txt Normal file
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Disclaimer:
The use of this code is at your own risk. Of course, we do made every effort to ensure
that the reference files are free of bugs and issues. We also tested the design on FPGAs
to make sure that it actually works.

225
BENCHMARK/simon_bit_serial/rtl/Simon_bit_serial_datapath_FPGA.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Team: Virginia Tech Secure Embedded Systems (SES) Lab
// Implementer: Ege Gulcan
//
// Create Date: 17:21:26 11/13/2013
// Design Name:
// Module Name: simon_datapath_shiftreg
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module simon_datapath_shiftreg(clk,data_in,data_rdy,key_in,cipher_out,round_counter,bit_counter);
input clk,data_in,key_in;
input [1:0] data_rdy;
input round_counter;
output cipher_out;
output [5:0] bit_counter;
reg [55:0] shifter1;
reg [63:0] shifter2;
reg shift_in1,shift_in2;
wire shift_out1,shift_out2;
reg shifter_enable1,shifter_enable2;
reg fifo_ff63,fifo_ff62,fifo_ff61,fifo_ff60,fifo_ff59,fifo_ff58,fifo_ff57,fifo_ff56;
reg lut_ff63,lut_ff62,lut_ff61,lut_ff60,lut_ff59,lut_ff58,lut_ff57,lut_ff56;
reg lut_ff_input,fifo_ff_input;
reg lut_rol1,lut_rol2,lut_rol8;
reg s1,s4,s5,s6,s7;
reg [1:0] s3;
reg [5:0] bit_counter;
wire lut_out;
// Shift Register1 FIFO 56x1 Begin
// 56x1 Shift register to store the upper word
always @(posedge clk)
begin
if(shifter_enable1)
begin
shifter1 <= {shift_in1, shifter1[55:1]};
end
end
assign shift_out1 = shifter1[0];
// Shift Register1 End
// Shift Register2 FIFO 64x1 Begin
// 64x1 Shift register to store the lower word
always @(posedge clk)
begin
if(shifter_enable2)
begin
shifter2 <= {shift_in2, shifter2[63:1]};
end
end
assign shift_out2 = shifter2[0];
// Shift Register2 End
// 8 Flip-Flops to store the most significant 8 bits of the upper word at even rounds
// Denoted as Shift Register Up (SRU) in Figure 5
always@(posedge clk)
begin
if(shifter_enable1)
begin
fifo_ff63 <= fifo_ff_input;
fifo_ff62 <= fifo_ff63;
fifo_ff61 <= fifo_ff62;
fifo_ff60 <= fifo_ff61;
fifo_ff59 <= fifo_ff60;
fifo_ff58 <= fifo_ff59;
fifo_ff57 <= fifo_ff58;
fifo_ff56 <= fifo_ff57;
end
end
// 8 Flip-Flops to store the most significant 8 bits of the upper word at odd rounds
// Denoted as Shift Register Down (SRD) in Figure 5
always@(posedge clk)
begin
lut_ff63 <= lut_ff_input;
lut_ff62 <= lut_ff63;
lut_ff61 <= lut_ff62;
lut_ff60 <= lut_ff61;
lut_ff59 <= lut_ff60;
lut_ff58 <= lut_ff59;
lut_ff57 <= lut_ff58;
lut_ff56 <= lut_ff57;
end
// FIFO 64x1 Input MUX
// Input of the lower FIFO is always the output of the upper FIFO
always@(*)
begin
shift_in2 = shift_out1;
end
// FIFO 56x1 Input MUX
// Input of the upper FIFO depends on the select line S1
always@(*)
begin
if(s1==0)
shift_in1 = lut_ff56;
else
shift_in1 = fifo_ff56;
end
// FIFO FF Input MUX
// The input of FIFO_FF can be the input plaintext, output of 56x1 FIFO or the output of LUT
always@(*)
begin
if(s3==0)
fifo_ff_input = data_in;
else if(s3==1)
fifo_ff_input = shift_out1;
else if(s3==2)
fifo_ff_input = lut_out;
else
fifo_ff_input = 1'bx; // Debugging
end
// LUT FF Input MUX
// The input of the LUT_FF is either the output of 56x1 FIFO or the output of LUT
always@(*)
begin
if(s5==0)
lut_ff_input = shift_out1;
else
lut_ff_input = lut_out;
end
// LUT Input MUX
always@(*)
begin
if(s7==0)
lut_rol1 = fifo_ff63;
else
lut_rol1 = lut_ff63;
if(s4==0)
lut_rol2 = fifo_ff62;
else
lut_rol2 = lut_ff62;
if(s6==0)
lut_rol8 = fifo_ff56;
else
lut_rol8 = lut_ff56;
end
//Selection MUX
always@(*)
begin
// For the first 8 bits of each even round OR for all the bits after the first 8 bits in odd rounds OR loading the plaintext
if((round_counter==0 && bit_counter<8)||(round_counter==1 && bit_counter>7)||(data_rdy==1))
s1 = 1;
else
s1 = 0;
if(data_rdy==1) // Loading plaintext
s3 = 0;
else if(round_counter==0) // Even rounds
s3 = 1;
else if(round_counter==1) // Odd rounds
s3 = 2;
else
s3 = 1'bx; // For debugging
if(round_counter==0) // Even rounds
s6 = 0;
else
s6 = 1;
s4 = s6;
s7 = s6;
s5 = ~s6;
end
// SHIFTER ENABLES
// Two shift registers are enabled when the plaintext is being loaded (1) or when the block cipher is running (3)
always@(*)
begin
if(data_rdy==1 || data_rdy==3)
begin
shifter_enable1 = 1;
shifter_enable2 = 1;
end
else
begin
shifter_enable1 = 0;
shifter_enable2 = 0;
end
end
// The bit_counter value is incremented in each clock cycle when the block cipher is running
always@(posedge clk)
begin
if(data_rdy==0)
bit_counter <= 0;
else if(data_rdy==3)
bit_counter <= bit_counter + 1;
else
bit_counter <= bit_counter;
end
// The new computed value
assign lut_out = (lut_rol1 & lut_rol8) ^ shift_out2 ^ lut_rol2 ^ key_in;
// The global output that gives the ciphertext value
assign cipher_out = lut_out;
endmodule

241
BENCHMARK/simon_bit_serial/rtl/Simon_bit_serial_key_expansion_FPGA.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Team: Virginia Tech Secure Embedded Systems (SES) Lab
// Implementer: Ege Gulcan
//
// Create Date: 16:55:06 11/12/2013
// Design Name:
// Module Name: simon_key_expansion_shiftreg
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module simon_key_expansion_shiftreg(clk,data_in,key_out,data_rdy,bit_counter,round_counter_out);
input clk;
input data_in;
input [1:0] data_rdy;
input [5:0] bit_counter;
output key_out;
output round_counter_out;
reg [59:0] shifter1;
reg [63:0] shifter2;
reg shift_in1,shift_in2;
wire shift_out1,shift_out2;
reg shifter_enable1,shifter_enable2;
reg lut_ff_enable,fifo_ff_enable;
wire lut_out;
reg lut_in3;
reg s2,s3;
reg [1:0] s1;
reg [6:0] round_counter;
reg z_value;
reg fifo_ff0,fifo_ff1,fifo_ff2,fifo_ff3;
//(* shreg_extract = "no" *)
reg lut_ff0,lut_ff1,lut_ff2,lut_ff3;
//Constant value Z ROM
reg [0:67] Z = 68'b10101111011100000011010010011000101000010001111110010110110011101011;
reg c;
/////////////////////////////////////////
//// BEGIN CODE ////////////////////////
///////////////////////////////////////
// Least bit of the round counter is sent to the datapath to check if it is even or odd
assign round_counter_out = round_counter[0];
// Shift Register1 FIFO 60x1 Begin
// 60x1 shift register storing the 60 most significant bits of the upper word of the key
always @(posedge clk)
begin
if(shifter_enable1)
begin
shifter1 <= {shift_in1, shifter1[59:1]};
end
end
assign shift_out1 = shifter1[0];
// Shift Register1 End
// Shift Register2 FIFO 64x1 Begin
// 64x1 shift register storing the lower word of the key
always @(posedge clk)
begin
if(shifter_enable2)
begin
shifter2 <= {shift_in2, shifter2[63:1]};
end
end
assign shift_out2 = shifter2[0];
// Shift Register2 End
// 4 flip-flops storing the least significant 4 bits of the upper word in the first round
always @(posedge clk)
begin
if(fifo_ff_enable)
begin
fifo_ff3 <= shift_out1;
fifo_ff2 <= fifo_ff3;
fifo_ff1 <= fifo_ff2;
fifo_ff0 <= fifo_ff1;
end
end
// 4 flip-flops storing the least significant 4 bits of the upper word after the first round
always@(posedge clk)
begin
if(lut_ff_enable)
begin
lut_ff3 <= lut_out;
lut_ff2 <= lut_ff3;
lut_ff1 <= lut_ff2;
lut_ff0 <= lut_ff1;
end
end
//FIFO 64x1 Input MUX
always@(*)
begin
if(data_rdy==2)
shift_in2 = fifo_ff0;
else if(data_rdy==3 && (round_counter<1 || bit_counter>3))
shift_in2 = fifo_ff0;
else if(data_rdy==3 && bit_counter<4 && round_counter>0)
shift_in2 = lut_ff0;
else
shift_in2 = 1'bx;
end
//LUT >>3 Input MUX
always@(*)
begin
if(s2==0)
lut_in3 = fifo_ff3;
else
lut_in3 = lut_ff3;
end
//FIFO 60x1 Input MUX
always@(*)
begin
if(s1==0)
shift_in1 = fifo_ff0;
else if(s1==1)
shift_in1 = data_in;
else if(s1==2)
shift_in1 = lut_out;
else if(s1==3)
shift_in1 = lut_ff0;
else
shift_in1 = 1'bx;
end
//S2 MUX
always@(*)
begin
if(bit_counter==0 && round_counter!=0)
s2 = 1;
else
s2 = 0;
end
//S1 MUX
always@(*)
begin
if(data_rdy==2)
s1 = 1;
else if(data_rdy==3 && bit_counter<4 && round_counter==0)
s1 = 0;
else if(data_rdy==3 && bit_counter<4 && round_counter>0)
s1 = 3;
else
s1 = 2;
end
// LUT FF ENABLE MUX
// LUT FFs are used only at the first four clock cycles of each round
always@(*)
begin
if(data_rdy==3 && bit_counter<4)
lut_ff_enable = 1;
else
lut_ff_enable = 0;
end
//FIFO FF ENABLE MUX
always@(*)
begin
if(data_rdy==2 || data_rdy==3)
fifo_ff_enable = 1;
else
fifo_ff_enable = 0;
end
//SHIFTER ENABLES
// Shifters are enabled when the key is loaded or block cipher is running
always@(*)
begin
if(data_rdy==2 || data_rdy==3)
shifter_enable1 = 1;
else
shifter_enable1 = 0;
if(data_rdy==2 || data_rdy==3)
shifter_enable2 = 1;
else
shifter_enable2 = 0;
end
//Round Counter
always@(posedge clk)
begin
if(data_rdy==3 && bit_counter==63)
round_counter <= round_counter + 1;
else if(data_rdy==0)
round_counter <= 0;
else
round_counter <= round_counter;
end
// The necessary bit of the constant Z is selected by the round counter
always @(*)
begin
if(bit_counter==0)
z_value = Z[round_counter];
else
z_value = 0;
end
// The value of c is 1 at the first two cycles of each round only
always @(*)
begin
if(bit_counter==0 || bit_counter==1)
c = 0;
else
c = 1;
end
// New computed key bit
assign lut_out = shift_out2 ^ lut_in3 ^ shift_out1 ^ z_value ^ c;
// Output key bit that is connected to the datapath
assign key_out = shift_out2;
endmodule

45
BENCHMARK/simon_bit_serial/rtl/Simon_bit_serial_top_module_FPGA.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Team: Virginia Tech Secure Embedded Systems (SES) Lab
// Implementer: Ege Gulcan
//
// Create Date: 19:14:37 11/13/2013
// Design Name:
// Module Name: top_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_module(clk,data_in,data_rdy,cipher_out);
input clk,data_in;
input [1:0] data_rdy;
output cipher_out;
wire key;
wire [5:0] bit_counter;
wire round_counter_out;
/*
data_rdy=0 -> Reset, Idle
data_rdy=1 -> Load Plaintext
data_rdy=2 -> Load Key
data_rdy=3 -> Run (keep at 3 while the block cipher is running)
*/
simon_datapath_shiftreg datapath(.clk(clk), .data_in(data_in), .data_rdy(data_rdy), .key_in(key),
. cipher_out(cipher_out), .round_counter(round_counter_out), .bit_counter(bit_counter));
simon_key_expansion_shiftreg key_exp(.clk(clk), .data_in(data_in), .data_rdy(data_rdy), .key_out(key), .bit_counter(bit_counter),
.round_counter_out(round_counter_out));
endmodule

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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Team: Virginia Tech Secure Embedded Systems (SES) Lab
// Implementer: Ege Gulcan
//
// Create Date: 19:49:46 11/13/2013
// Design Name: top_module
// Module Name: top_module_test.v
// Project Name: SIMON
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_module_test;
// Inputs
reg clk;
reg data_in;
reg [1:0] data_rdy;
// Outputs
wire cipher_out;
// Plaintext and key from the NSA Simon and Speck paper
reg [127:0] plaintext = 128'h63736564207372656c6c657661727420;
reg [127:0] key = 128'h0f0e0d0c0b0a09080706050403020100;
integer i;
// Instantiate the Unit Under Test (UUT)
top_module uut (
.clk(clk),
.data_in(data_in),
.data_rdy(data_rdy),
.cipher_out(cipher_out)
);
initial begin
// Initialize Inputs
clk = 0;
data_in = 0;
data_rdy = 0;
#110;
#5;
//Set data_rdy=1 to load plaintext
data_rdy=1;
//Loads the plaintext one bit per clock cycle for 128 cycles
for(i=0;i<128;i = i+1)
begin
data_in = plaintext[i];
#20;
end
//Set data_rdy=2 to load key
data_rdy = 2;
//Loads the key one bit per clock cycle for 128 cycles
for(i=0;i<128;i = i+1)
begin
data_in = key[i];
#20;
end
//Set data_rdy=0 after loading is done
data_rdy = 0;
#20;
//Keep data_rdy=3 while the cipher is running
data_rdy = 3;
end
always #10 clk = ~clk;
endmodule

4
DOC/source/arch/clb_arch.rst
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@ -14,7 +14,7 @@ Feedback connections between LEs are implemented by the global routing architect
.. _fig_clb_arch:
.. figure:: ./figures/clb_arch.png
.. figure:: ./figures/clb_arch.svg
:scale: 20%
:alt: Configurable Logic Block schematic
@ -32,7 +32,7 @@ As shown in :numref:`fig_fle_arch`, each Logic Element (LE) consists of
.. _fig_fle_arch:
.. figure:: ./figures/fle_arch.png
.. figure:: ./figures/fle_arch.svg
:scale: 30%
:alt: Logic element schematic

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<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="7.121094" y="15">Caravel</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="34">GPIO[25]</tspan>
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<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.328125" y="15">Caravel Wishbone clk_i</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="3.1015625" y="34">Caravel Wishbone rst_i</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.765625" y="53">Caravel Wishbone stb_i</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="72">Caravel Wishbone cyc_i</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.7734375" y="91">Caravel Wishbone we_i</tspan>
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<text transform="translate(307.16846 1318.4707)" fill="#ff2600">
<tspan font-family="Times" font-size="16" font-weight="400" fill="#ff2600" x="0" y="15">Mode switch truth table:</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="#ff2600" x="0" y="34">- When Caravel GPIO[25] is logic ‘1’, FPGA is interfacing the Wishbone bus</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="#ff2600" x="0" y="53">- When Caravel GPIO[25] is logic ‘0’, FPGA is interfacing the logic analyzer</tspan>
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<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="15">CCFF_HEAD &lt;- Caravel GPIO[12]</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="30.023438" y="34">SC_TAIL -&gt; Caravel GPIO[11]</tspan>
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<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="15">IO_ISOL_N -&gt; Caravel GPIO[1]</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="12.445312" y="34">TEST_EN &lt;- Caravel GPIO[0]</tspan>
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<tspan font-family="Times" font-size="16" font-style="italic" font-weight="400" fill="black" x="0" y="15">106 bit</tspan>
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<text transform="translate(671.4629 1181.4697)" fill="black">
<tspan font-family="Times" font-size="16" font-style="italic" font-weight="400" fill="black" x="0" y="15">115 bit</tspan>
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<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="6.6640625" y="15">Caravel Wishbone sel_i[3:0]</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.7773438" y="34">Caravel Wishbone dat_i[31:0]</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.3359375" y="53">Caravel Wishbone adr_i[31:0]</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="18.222656" y="72">Caravel Wishbone ack_o</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="91">Caravel Wishbone dat_o[31:0]</tspan>
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4
DOC/source/arch/fpga_arch.rst
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@ -14,7 +14,7 @@ I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RIS
.. _fig_fpga_arch:
.. figure:: ./figures/fpga_arch.png
.. figure:: ./figures/fpga_arch.svg
:scale: 25%
:alt: Tile-based FPGA architecture
@ -72,7 +72,7 @@ When `Test_en` signal is active, users can
.. _fig_fabric_scan_chain:
.. figure:: ./figures/fabric_scan_chain.png
.. figure:: ./figures/fabric_scan_chain.svg
:scale: 25%
:alt: Built-in scan-chain across FPGA

12
DOC/source/arch/io_resource.rst
View File

@ -20,9 +20,11 @@ Among the 144 I/Os,
.. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes.
.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_fpga_io_switch`.
.. _fig_fpga_io_switch:
.. figure:: ./figures/fpga_io_switch.png
.. figure:: ./figures/fpga_io_switch.svg
:scale: 20%
:alt: I/O arrangement of FPGA IP
@ -37,13 +39,13 @@ Accelerator Mode
When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
:numref:`fig_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations.
.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:30] are not connected.
.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:29] are not connected.
.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.
.. _fig_fpga_io_map_wishbone_mode:
.. figure:: ./figures/fpga_io_map_wishbone_mode.png
.. figure:: ./figures/fpga_io_map_wishbone_mode.svg
:scale: 20%
:alt: I/O arrangement of FPGA IP when interfacing wishbone bus
@ -66,7 +68,7 @@ When the logic analyzer interface is enabled, the FPGA can operate in debug mode
.. _fig_fpga_io_map_logic_analyzer_mode:
.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.png
.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.svg
:scale: 20%
:alt: I/O arrangement of FPGA IP when interfacing logic analyzer
@ -98,7 +100,7 @@ The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC,
.. _fig_embedded_io_schematic:
.. figure:: ./figures/embedded_io_schematic.png
.. figure:: ./figures/embedded_io_schematic.svg
:scale: 30%
:alt: Schematic of embedded I/O cell used in FPGA

259
HDL/common/caravel_fpga_wrapper_hd.v
View File

@ -68,6 +68,12 @@ module fpga_top (
// Switch between wishbone and logic analyzer
wire wb_la_switch;
wire wb_la_switch_b;
// Inverted switch signal to drive tri-state buffers
// Use drive strength 8 as we will have 33 output pins which is driven by
// the buffers
sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(la_wb_switch), .Y(la_wb_switch_b));
// Wire-bond TOP side I/O of FPGA to LEFT-side of Caravel interface
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24];
@ -106,218 +112,251 @@ module fpga_top (
// Wire-bond RIGHT, BOTTOM, LEFT side I/O of FPGA to BOTTOM-side of Caravel interface
// Autogenerate code start
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(la_wb_switch), .A1(wb_rst_i), .A0(la_data_in[13]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(wb_la_switch), .A1(wb_clk_i), .A0(la_data_in[13]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135]));
assign la_data_out[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] = la_data_in[14];
assign wbs_ack_o = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_133_MUX (.S(la_wb_switch), .A1(wbs_cyc_i), .A0(la_data_in[15]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133]));
assign la_data_out[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(la_wb_switch), .A1(wbs_stb_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX (.S(wb_la_switch), .A1(wb_rst_i), .A0(la_data_in[14]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134]));
assign la_data_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[15];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(wbs_ack_o));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(la_data_out[15]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(wb_la_switch), .A1(wbs_cyc_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132]));
assign la_data_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(la_wb_switch), .A1(wbs_we_i), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(wb_la_switch), .A1(wbs_stb_i), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131]));
assign la_data_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(la_wb_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(wb_la_switch), .A1(wbs_we_i), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130]));
assign la_data_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(la_wb_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(wb_la_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129]));
assign la_data_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(la_wb_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(wb_la_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128]));
assign la_data_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(la_wb_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(wb_la_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127]));
assign la_data_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(la_wb_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(wb_la_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126]));
assign la_data_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(la_wb_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(wb_la_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125]));
assign la_data_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(la_wb_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(wb_la_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124]));
assign la_data_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(la_wb_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(wb_la_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123]));
assign la_data_out[25] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(la_wb_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(wb_la_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122]));
assign la_data_out[26] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(la_wb_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(wb_la_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121]));
assign la_data_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(la_wb_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(wb_la_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120]));
assign la_data_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(la_wb_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(wb_la_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119]));
assign la_data_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(la_wb_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(wb_la_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118]));
assign la_data_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(la_wb_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(wb_la_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117]));
assign la_data_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(la_wb_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(wb_la_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116]));
assign la_data_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(la_wb_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(wb_la_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115]));
assign la_data_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(la_wb_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(wb_la_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114]));
assign la_data_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(la_wb_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(wb_la_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113]));
assign la_data_out[35] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(la_wb_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(wb_la_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112]));
assign la_data_out[36] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(la_wb_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(wb_la_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111]));
assign la_data_out[37] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(la_wb_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(wb_la_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110]));
assign la_data_out[38] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(la_wb_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(wb_la_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109]));
assign la_data_out[39] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(la_wb_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(wb_la_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108]));
assign la_data_out[40] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(la_wb_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(wb_la_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107]));
assign la_data_out[41] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(la_wb_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(wb_la_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106]));
assign la_data_out[42] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(la_wb_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(wb_la_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105]));
assign la_data_out[43] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(la_wb_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(wb_la_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104]));
assign la_data_out[44] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(la_wb_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(wb_la_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103]));
assign la_data_out[45] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(la_wb_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(wb_la_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102]));
assign la_data_out[46] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(la_wb_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(wb_la_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101]));
assign la_data_out[47] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(la_wb_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(wb_la_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100]));
assign la_data_out[48] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(la_wb_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(wb_la_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99]));
assign la_data_out[49] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(la_wb_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(wb_la_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98]));
assign la_data_out[50] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(la_wb_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(wb_la_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97]));
assign la_data_out[51] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(la_wb_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(wb_la_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96]));
assign la_data_out[52] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(la_wb_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(wb_la_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95]));
assign la_data_out[53] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(la_wb_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(wb_la_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94]));
assign la_data_out[54] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(la_wb_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(wb_la_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93]));
assign la_data_out[55] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(la_wb_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(wb_la_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92]));
assign la_data_out[56] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(la_wb_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(wb_la_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91]));
assign la_data_out[57] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(la_wb_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(wb_la_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90]));
assign la_data_out[58] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(la_wb_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(wb_la_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89]));
assign la_data_out[59] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(la_wb_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(wb_la_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88]));
assign la_data_out[60] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(la_wb_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(wb_la_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87]));
assign la_data_out[61] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(la_wb_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(wb_la_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86]));
assign la_data_out[62] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(la_wb_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(wb_la_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85]));
assign la_data_out[63] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(la_wb_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(wb_la_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84]));
assign la_data_out[64] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(la_wb_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(wb_la_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83]));
assign la_data_out[65] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(la_wb_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(wb_la_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82]));
assign la_data_out[66] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(la_wb_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(wb_la_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81]));
assign la_data_out[67] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(la_wb_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(wb_la_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80]));
assign la_data_out[68] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(la_wb_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(wb_la_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79]));
assign la_data_out[69] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(la_wb_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(wb_la_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78]));
assign la_data_out[70] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(la_wb_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(wb_la_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77]));
assign la_data_out[71] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(la_wb_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(wb_la_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76]));
assign la_data_out[72] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(la_wb_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(wb_la_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75]));
assign la_data_out[73] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(la_wb_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(wb_la_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74]));
assign la_data_out[74] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(la_wb_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(wb_la_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73]));
assign la_data_out[75] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(la_wb_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(wb_la_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72]));
assign la_data_out[76] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(la_wb_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(wb_la_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71]));
assign la_data_out[77] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(la_wb_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(wb_la_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70]));
assign la_data_out[78] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(la_wb_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(wb_la_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69]));
assign la_data_out[79] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(la_wb_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(wb_la_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68]));
assign la_data_out[80] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(la_wb_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(wb_la_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67]));
assign la_data_out[81] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(la_wb_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(wb_la_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66]));
assign la_data_out[82] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(la_wb_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(wb_la_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65]));
assign la_data_out[83] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(la_wb_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(wb_la_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64]));
assign la_data_out[84] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(la_wb_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[85]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(wb_la_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[85]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63]));
assign la_data_out[85] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] = la_data_in[86];
assign wbs_dat_o[0] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX (.S(wb_la_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[86]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62]));
assign la_data_out[86] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[87];
assign wbs_dat_o[1] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(wbs_dat_o[0]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(la_data_out[87]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[88];
assign wbs_dat_o[2] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(wbs_dat_o[1]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(la_data_out[88]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[89];
assign wbs_dat_o[3] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(wbs_dat_o[2]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(la_data_out[89]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[90];
assign wbs_dat_o[4] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(wbs_dat_o[3]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(la_data_out[90]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[91];
assign wbs_dat_o[5] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(wbs_dat_o[4]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(la_data_out[91]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[92];
assign wbs_dat_o[6] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(wbs_dat_o[5]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(la_data_out[92]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[93];
assign wbs_dat_o[7] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(wbs_dat_o[6]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(la_data_out[93]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[94];
assign wbs_dat_o[8] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(wbs_dat_o[7]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(la_data_out[94]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[95];
assign wbs_dat_o[9] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(wbs_dat_o[8]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(la_data_out[95]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[96];
assign wbs_dat_o[10] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(wbs_dat_o[9]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(la_data_out[96]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[97];
assign wbs_dat_o[11] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(wbs_dat_o[10]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(la_data_out[97]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[98];
assign wbs_dat_o[12] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(wbs_dat_o[11]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(la_data_out[98]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[99];
assign wbs_dat_o[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(wbs_dat_o[12]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(la_data_out[99]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[100];
assign wbs_dat_o[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(wbs_dat_o[13]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(la_data_out[100]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[101];
assign wbs_dat_o[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(wbs_dat_o[14]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(la_data_out[101]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[102];
assign wbs_dat_o[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(wbs_dat_o[15]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(la_data_out[102]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[103];
assign wbs_dat_o[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(wbs_dat_o[16]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(la_data_out[103]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[104];
assign wbs_dat_o[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(wbs_dat_o[17]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(la_data_out[104]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[105];
assign wbs_dat_o[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(wbs_dat_o[18]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(la_data_out[105]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[106];
assign wbs_dat_o[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(wbs_dat_o[19]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(la_data_out[106]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[107];
assign wbs_dat_o[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(wbs_dat_o[20]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(la_data_out[107]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[108];
assign wbs_dat_o[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(wbs_dat_o[21]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(la_data_out[108]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[109];
assign wbs_dat_o[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(wbs_dat_o[22]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(la_data_out[109]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[110];
assign wbs_dat_o[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(wbs_dat_o[23]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(la_data_out[110]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[111];
assign wbs_dat_o[25] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(wbs_dat_o[24]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(la_data_out[111]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[112];
assign wbs_dat_o[26] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(wbs_dat_o[25]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(la_data_out[112]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[113];
assign wbs_dat_o[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(wbs_dat_o[26]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(la_data_out[113]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[114];
assign wbs_dat_o[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(wbs_dat_o[27]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(la_data_out[114]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[115];
assign wbs_dat_o[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(wbs_dat_o[28]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(la_data_out[115]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[116];
assign wbs_dat_o[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(wbs_dat_o[29]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(la_data_out[116]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[117];
assign wbs_dat_o[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(wbs_dat_o[30]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(la_data_out[117]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[118];
assign la_data_out[118] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(wbs_dat_o[31]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(la_data_out[118]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[119];
assign la_data_out[119] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[120];
@ -344,7 +383,7 @@ module fpga_top (
assign io_oeb[37] = 1'b1;
// FPGA clock port can be driven by either wishbone clock or an GPIO
sky130_fd_sc_hd__mux2_1 FPGA_CLK_MUX (.S(la_wb_switch), .A1(wb_clk_i), .A0(io_in[36]), .X(clk));
assign clk = io_in[36];
assign io_out[36] = 1'b0;
assign io_oeb[36] = 1'b1;

8
HDL/common/caravel_fpga_wrapper_hd_template.v
View File

@ -68,6 +68,12 @@ module fpga_top (
// Switch between wishbone and logic analyzer
wire wb_la_switch;
wire wb_la_switch_b;
// Inverted switch signal to drive tri-state buffers
// Use drive strength 8 as we will have 33 output pins which is driven by
// the buffers
sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(la_wb_switch), .Y(la_wb_switch_b));
// Wire-bond TOP side I/O of FPGA to LEFT-side of Caravel interface
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24];
@ -114,7 +120,7 @@ module fpga_top (
assign io_oeb[37] = 1'b1;
// FPGA clock port can be driven by either wishbone clock or an GPIO
sky130_fd_sc_hd__mux2_1 FPGA_CLK_MUX (.S(la_wb_switch), .A1(wb_clk_i), .A0(io_in[36]), .X(clk));
assign clk = io_in[36];
assign io_out[36] = 1'b0;
assign io_oeb[36] = 1'b1;

46
HDL/common/digital_io_behavorial.v
View File

@ -1,46 +0,0 @@
//-----------------------------------------------------
// This file includes behavorial modeling
// for digital I/O cells
// These cells may not be directly used for physical design
// Synthesis tools may be needed
//-----------------------------------------------------
`timescale 1ns/1ps
//-----------------------------------------------------
// Function : A minimum input pad
//-----------------------------------------------------
module GPIN (
inout A, // External PAD signal
output Y // Data input
);
assign Y = A;
endmodule
//-----------------------------------------------------
// Function : A minimum output pad
//-----------------------------------------------------
module GPOUT (
inout Y, // External PAD signal
input A // Data output
);
assign Y = A;
endmodule
//-----------------------------------------------------
// Function : A minimum embedded I/O
// just an overlay to interface other components
//-----------------------------------------------------
module EMBEDDED_IO (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output SOC_DIR, // Output the directionality
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_DIR // direction control
);
assign FPGA_IN = SOC_IN;
assign SOC_OUT = FPGA_OUT;
assign SOC_DIR = FPGA_DIR;
endmodule

24
HDL/common/digital_io_hd.v
View File

@ -31,22 +31,26 @@ module EMBEDDED_IO_HD (
input IO_ISOL_N // Isolation enable signal
);
sky130_fd_sc_hd__and2_0 ISOL_EN_GATE (.A(IO_ISOL_N),
.B(FPGA_DIR),
wire SOC_DIR_N;
// Use drive-strength 4 for a high fan-out from SoC components
sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N),
.A(FPGA_DIR),
.X(SOC_DIR)
);
// Use drive-strength 4 for a high fan-out from global routing architecture
sky130_fd_sc_hd__and2_4 IN_PROTECT_GATE (.A(SOC_DIR),
.B(SOC_IN),
.X(FPGA_IN)
);
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (.TE_B(SOC_DIR_N),
.A(SOC_IN),
.Z(FPGA_IN)
);
// Use drive-strength 4 for a potential high fan-out from SoC components
sky130_fd_sc_hd__and2b_4 OUT_PROTECT_GATE (.A_N(SOC_DIR),
.B(FPGA_OUT),
.X(SOC_OUT)
);
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR),
.A(FPGA_OUT),
.Z(SOC_OUT)
);
endmodule

51
HDL/common/wrapper_lines_generator.py
View File

@ -1,8 +1,9 @@
#####################################################################
# Python script to adapt an OpenFPGA architecture file
# Python script generate Verilog codes for the Caravel wrapper
# which interface the FPGA fabric and other SoC components
# This script will
# - Convert the ${SKYWATER_OPENFPGA_HOME} to the absolute path of current directory
#
# - generate the Verilog codes to connect FPGA inputs to Wishbone and Logic analyzer
# - generate the Verilog codes to connect FPGA outputs to Wishbone and Logic analyzer
#####################################################################
import os
@ -34,7 +35,8 @@ args = parser.parse_args()
# The list start from left-side of the wrapper to the right side
# Target FPGA gpio start from 135, 134 ...
#####################################################################
wishbone_pins = ['wb_rst_i', 'wbs_ack_o', 'wbs_cyc_i',
wishbone_pins = ['wb_clk_i', 'wb_rst_i',
'wbs_ack_o', 'wbs_cyc_i',
'wbs_stb_i', 'wbs_we_i']
wishbone_pins.extend([f"wbs_sel_i[{i}]" for i in range(4)])
@ -73,25 +75,58 @@ for ipin in range(0, num_gpio_pins):
# If this is an input pin of wishbone interface, whose postfix is '_i', we use MUX
# otherwise, this is an output pin, we just wire the input to logic analyzer
if ((wishbone_pins[ipin].endswith("_i")) or (re.search(r'_i\[\d+\]$', wishbone_pins[ipin], re.M | re.I))):
curr_line = " " + "sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_" + str(135 - ipin) + "_MUX (.S(la_wb_switch), .A1(" + str(
##############################################################
# SOC INPUT will be directly driven by either
# - the Wishbone input
# or
# - the logic analyzer input
# through a multiplexer controlled by the signal 'wb_la_switch
curr_line = " " + "sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_" + str(135 - ipin) + "_MUX (.S(wb_la_switch), .A1(" + str(
wishbone_pins[ipin]) + "), .A0(" + str(logic_analyzer_pins[ipin][0]) + "), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[" + str(135 - ipin) + "]));"
netlist_lines.append(curr_line + "\n")
##############################################################
# SOC OUTPUT will drive an output of logic analyzer
# since this I/O is going to interface a Wishbone input only
curr_line = " " + "assign " + \
str(logic_analyzer_pins[ipin][1]) + \
" = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "];"
netlist_lines.append(curr_line + "\n")
elif ((wishbone_pins[ipin].endswith("_o")) or (re.search(r'_o\[\d+\]$', wishbone_pins[ipin], re.M | re.I))):
##############################################################
# SOC INPUT will be directly driven by logic analyzer
# since this I/O is going to interface a Wishbone output only
curr_line = " " + "assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[" + str(
135 - ipin) + "] = " + str(logic_analyzer_pins[ipin][0]) + ";"
netlist_lines.append(curr_line + "\n")
curr_line = " " + "assign " + \
str(wishbone_pins[ipin]) + \
" = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "];"
##############################################################
# SOC OUTPUT will drive the Wishbone output through a tri-state buffer
# As the buffer is enabled by logic '0', we use the inverted 'wb_la_switch'
curr_line = " " + "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(135 - ipin) + "_DEMUX_WB (" + \
".TE_B(wb_la_switch_b), " + \
".A(" + "gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "]), " + \
".Z(" + str(wishbone_pins[ipin]) + ")" + \
");"
netlist_lines.append(curr_line + "\n")
##############################################################
# SOC OUTPUT will also drive the Logic Analyzer output through a tri-state buffer
# As the buffer is enabled by logic '0', we use the 'wb_la_switch'
curr_line = " " + "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(135 - ipin) + "_DEMUX_LA (" + \
".TE_B(wb_la_switch), " + \
".A(" + "gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "]), " + \
".Z(" + str(logic_analyzer_pins[ipin][1]) + ")" + \
");"
netlist_lines.append(curr_line + "\n")
elif ((ipin >= num_wishbone_pins) and (ipin < num_logic_analyzer_pins)):
##############################################################
# SOC INPUT will be directly driven by logic analyzer
# since this I/O is going to interface logic analyzer input only
curr_line = " " + "assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[" + str(
135 - ipin) + "] = " + str(logic_analyzer_pins[ipin][0]) + ";"
netlist_lines.append(curr_line + "\n")
##############################################################
# SOC OUTPUT will directly drive logic analyzer
# since this I/O is going to interface logic analyzer output only
curr_line = " " + "assign " + \
str(logic_analyzer_pins[ipin][1]) + \
" = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "];"

14
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
View File

@ -31,10 +31,24 @@ arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_
[BENCHMARKS]
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

1
TESTBENCH/README.md
View File

@ -2,4 +2,5 @@
This directory contains the testbenches for FPGA fabrics that are automatically generated by OpenFPGA or tuned for a specific FPGA fabric.
Please keep this directory clean and organize as follows:
- Each testbench should be placed in a separated directory
- **common**: include commonly used testbench template for post-PnR verification mainly
- READMD is the only file allowed in the directory, others should be sub-directories.

11
TESTBENCH/common/README.md Normal file
View File

@ -0,0 +1,11 @@
# Skywater PDK
This directory contains the commonly used testbench template for FPGA verificatio
* **post\_pnr\_fpga\_cells.v**: The netlist that includes all the standard cells used by the post-PnRed FPGA fabric
* Pre-PnR testbenches
- **pre\_pnr\_ccff\_test.v**: The template testbench for post-PnR verification on the configuration chain
* Post-PnR testbenches
- **post\_pnr\_ccff\_test.v**: The template testbench for post-PnR verification on the configuration chain
- **post\_pnr\_scff\_test.v**: The template testbench for post-PnR verification on the scan chain

26
TESTBENCH/common/post_pnr_ccff_test.v
View File

@ -54,6 +54,7 @@ wire [0:0] IO_ISOL_N;
// ----- Counters for error checking -----
integer num_prog_cycles = 0;
integer num_errors = 0;
integer num_checked_points = 0;
// Indicate when configuration should be finished
reg config_done = 0;
@ -134,9 +135,9 @@ initial
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.sc_head(sc_head[0]),
@ -168,11 +169,24 @@ initial
// Check the ccff_tail when configuration is done
if (1'b1 == config_done) begin
if (sc_tail != 1'b1) begin
$display("Error: sc_tail = %b", sc_tail);
num_errors = num_errors + 1;
// The tail should spit a pulse after configuration is done
// So it should be at logic '1' and then pulled down to logic '0'
if (0 == num_checked_points) begin
if (ccff_tail !== 1'b1) begin
$display("Error: ccff_tail = %b", sc_tail);
num_errors = num_errors + 1;
end
end
if (1 <= num_checked_points) begin
if (ccff_tail !== 1'b0) begin
$display("Error: ccff_tail = %b", sc_tail);
num_errors = num_errors + 1;
end
end
num_checked_points = num_checked_points + 1;
end
if (2 < num_checked_points) begin
$display("Simulation finish with %d errors", num_errors);
// End simulation

48
TESTBENCH/common/post_pnr_fpga_cells.v Normal file
View File

@ -0,0 +1,48 @@
// Include Skywater cell netlists that are used in post PnRed FPGA netlists
// Cells already used pre-PnR
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
// Cells added due to their use in PnR
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_4.v"

30
TESTBENCH/common/post_pnr_scff_test.v
View File

@ -54,6 +54,7 @@ wire [0:0] IO_ISOL_N;
// ----- Counters for error checking -----
integer num_clock_cycles = 0;
integer num_errors = 0;
integer num_checked_points = 0;
// Indicate when configuration should be finished
reg scan_done = 0;
@ -130,14 +131,14 @@ initial
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.sc_head(sc_head[0]),
.sc_tail(sc_tail[0])
//.IO_ISOL_N(IO_ISOL_N)
.sc_tail(sc_tail[0]),
.IO_ISOL_N(IO_ISOL_N)
);
// ----- Force constant '0' to FPGA I/O as this testbench only check
@ -164,11 +165,24 @@ initial
// Check the tail of scan-chain when configuration is done
if (1'b1 == scan_done) begin
if (sc_tail != 1'b1) begin
$display("Error: sc_tail = %b", sc_tail);
num_errors = num_errors + 1;
// The tail should spit a pulse after configuration is done
// So it should be at logic '1' and then pulled down to logic '0'
if (0 == num_checked_points) begin
if (sc_tail !== 1'b1) begin
$display("Error: sc_tail = %b", sc_tail);
num_errors = num_errors + 1;
end
end
if (1 <= num_checked_points) begin
if (sc_tail !== 1'b0) begin
$display("Error: sc_tail = %b", sc_tail);
num_errors = num_errors + 1;
end
end
num_checked_points = num_checked_points + 1;
end
if (2 < num_checked_points) begin
$display("Simulation finish with %d errors", num_errors);
// End simulation

605
TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v
View File

@ -3,7 +3,7 @@
// Description: FPGA Verilog Testbench for Top-level netlist of Design: and2_latch
// Author: Xifan TANG
// Organization: University of Utah
// Date: Tue Nov 17 15:03:02 2020
// Date: Tue Nov 17 19:54:57 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
@ -12,14 +12,15 @@ module and2_latch_autocheck_top_tb;
// ----- Local wires for global ports of FPGA fabric -----
wire [0:0] prog_clk;
wire [0:0] Test_en;
wire [0:0] IO_ISOL_N;
wire [0:0] clk;
// ----- Local wires for I/Os of FPGA fabric -----
wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_IN;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_OUT;
wire [0:143] gfpga_pad_EMBEDDED_IO_SOC_DIR;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
reg [0:0] config_done;
wire [0:0] prog_clock;
@ -141,321 +142,325 @@ initial
assign prog_clk[0] = prog_clock[0];
assign clk[0] = op_clock[0];
assign Test_en[0] = 1'b0;
assign IO_ISOL_N[0] = 1'b1;
assign sc_head[0] = 1'b0;
// ----- End connecting global ports of FPGA fabric to stimuli -----
// ----- FPGA top-level module to be capsulated -----
fpga_core FPGA_DUT (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.IO_ISOL_N(IO_ISOL_N[0]),
.clk(clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:143]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:143]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:143]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:143]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:143]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:143]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.sc_head(sc_head[0]),
.sc_tail(sc_tail[0])
);
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[11] -----
assign gfpga_pad_EMBEDDED_IO_SOC_IN[11] = a[0];
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] -----
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = a[0];
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[12] -----
assign gfpga_pad_EMBEDDED_IO_SOC_IN[12] = b[0];
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] -----
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = b[0];
// ----- Blif Benchmark input clk is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[42] -----
assign gfpga_pad_EMBEDDED_IO_SOC_IN[42] = clk[0];
// ----- Blif Benchmark input clk is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] -----
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = clk[0];
// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_OUT[13] -----
assign out_c_fpga[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[13];
// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] -----
assign out_c_fpga[0] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13];
// ----- Blif Benchmark output out_d is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_OUT[10] -----
assign out_d_fpga[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[10];
// ----- Blif Benchmark output out_d is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] -----
assign out_d_fpga[0] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10];
// ----- Wire unused FPGA I/Os to constants -----
assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[1] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[2] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[3] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[4] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[5] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[6] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[7] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[8] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[9] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[10] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[13] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[14] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[15] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[16] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[17] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[18] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[19] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[20] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[21] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[22] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[23] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[24] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[25] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[26] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[27] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[28] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[29] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[30] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[31] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[32] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[33] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[34] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[35] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[36] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[37] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[38] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[39] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[40] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[41] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[43] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[44] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[45] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[46] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[47] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[48] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[49] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[50] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[51] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[52] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[53] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[54] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[55] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[56] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[57] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[58] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[59] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[60] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[61] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[62] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[63] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[64] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[65] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[66] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[67] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[68] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[69] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[70] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[71] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[72] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[73] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[74] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[75] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[76] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[77] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[78] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[79] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[80] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[81] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[82] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[83] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[84] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[85] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[86] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[87] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[88] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[89] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[90] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[91] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[92] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[93] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[94] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[95] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[96] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[97] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[98] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[99] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[100] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[101] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[102] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[103] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[104] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[105] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[106] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[107] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[108] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[109] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[110] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[111] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[112] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[113] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[114] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[115] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[116] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[117] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[118] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[119] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[120] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[121] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[122] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[123] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[124] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[125] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[126] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[127] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[128] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[129] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[130] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[131] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[132] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[133] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[134] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[135] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[136] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[137] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[138] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[139] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[140] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[141] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[142] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_IN[143] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[1] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[2] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[3] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[4] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[5] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[6] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[7] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[8] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[9] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[11] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[12] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[14] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[15] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[16] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[17] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[18] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[19] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[20] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[21] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[22] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[23] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[24] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[25] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[26] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[27] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[28] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[29] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[30] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[31] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[32] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[33] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[34] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[35] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[36] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[37] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[38] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[39] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[40] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[41] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[42] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[43] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[44] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[45] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[46] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[47] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[48] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[49] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[50] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[51] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[52] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[53] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[54] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[55] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[56] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[57] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[58] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[59] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[60] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[61] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[62] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[63] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[64] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[65] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[66] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[67] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[68] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[69] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[70] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[71] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[72] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[73] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[74] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[75] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[76] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[77] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[78] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[79] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[80] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[81] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[82] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[83] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[84] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[85] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[86] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[87] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[88] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[89] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[90] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[91] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[92] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[93] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[94] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[95] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[96] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[97] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[98] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[99] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[100] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[101] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[102] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[103] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[104] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[105] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[106] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[107] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[108] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[109] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[110] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[111] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[112] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[113] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[114] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[115] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[116] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[117] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[118] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[119] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[120] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[121] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[122] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[123] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[124] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[125] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[126] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[127] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[128] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[129] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[130] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[131] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[132] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[133] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[134] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[135] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[136] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[137] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[138] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[139] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[140] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[141] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[142] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[143] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = 1'b0;
`ifdef AUTOCHECKED_SIMULATION
// ----- Reference Benchmark Instanication -------

44
TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
View File

@ -14,51 +14,11 @@
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
// ------ Include Skywater cell netlists -----
// Cells already used pre-PnR
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
// Cells added due to their use in PnR
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "and2_latch_output_verilog.v"

66234
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@ -0,0 +1,30 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Sun Nov 22 13:37:06 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include simulation defines -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
// ------ Include Skywater cell netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "and2_or2_output_verilog.v"
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v"
`endif

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TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
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@ -14,51 +14,11 @@
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
// ------ Include Skywater cell netlists -----
// Cells already used pre-PnR
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
// Cells added due to their use in PnR
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "and2_output_verilog.v"

66460
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@ -0,0 +1,30 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Fri Nov 20 15:48:46 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include simulation defines -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
// ------ Include Skywater cell netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "bin2bcd_output_verilog.v"
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_autocheck_top_tb.v"
`endif

46
TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
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@ -9,7 +9,7 @@
`timescale 1ns / 1ps
// Design parameter for FPGA I/O sizes
`define FPGA_IO_SIZE 108
`define FPGA_IO_SIZE 144
// Design parameter for FPGA bitstream sizes
`define FPGA_BITSTREAM_SIZE 65656
@ -20,50 +20,10 @@
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
// ------ Include Skywater cell netlists -----
// Cells already used pre-PnR
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
// Cells added due to their use in PnR
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_ccff_test.v"

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@ -0,0 +1,29 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Fri Nov 20 15:48:45 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include simulation defines -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
// ------ Include Skywater cell netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "counter_output_verilog.v"
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/counter_post_pnr_autocheck_top_tb.v"
`endif

66262
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@ -0,0 +1,30 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Fri Nov 20 15:48:54 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include simulation defines -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
// ------ Include Skywater cell netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "routing_test_output_verilog.v"
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v"
`endif

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@ -9,7 +9,7 @@
`timescale 1ns / 1ps
// Design parameter for FPGA I/O sizes
`define FPGA_IO_SIZE 108
`define FPGA_IO_SIZE 144
// Design parameter for FPGA bitstream sizes
`define FPGA_SCANCHAIN_SIZE 2304
@ -20,50 +20,10 @@
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
// ------ Include Skywater cell netlists -----
// Cells already used pre-PnR
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
// Cells added due to their use in PnR
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_scff_test.v"

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@ -0,0 +1,30 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Fri Nov 20 15:49:05 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include simulation defines -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
// ------ Include Skywater cell netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "top_module_output_verilog.v"
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/top_module_post_pnr_autocheck_top_tb.v"
`endif