From 804d96bf50e306873023825a609c8e1e69fd13ec Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 17 Nov 2020 13:45:55 -0700 Subject: [PATCH] [Testbench] Rename post-pnr testbenches to dedicated directories --- .../verilog_testbench/and2_post_pnr_autocheck_top_tb.v | 0 .../verilog_testbench/and2_post_pnr_include_netlists.v | 4 ++-- .../verilog_testbench/and2_post_pnr_autocheck_top_tb.v | 0 .../verilog_testbench/and2_post_pnr_include_netlists.v | 4 ++-- 4 files changed, 4 insertions(+), 4 deletions(-) rename TESTBENCH/{k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc => k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr}/verilog_testbench/and2_post_pnr_autocheck_top_tb.v (100%) rename TESTBENCH/{k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc => k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr}/verilog_testbench/and2_post_pnr_include_netlists.v (97%) rename TESTBENCH/{k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc => k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr}/verilog_testbench/and2_post_pnr_autocheck_top_tb.v (100%) rename TESTBENCH/{k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc => k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr}/verilog_testbench/and2_post_pnr_include_netlists.v (97%) diff --git a/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v similarity index 100% rename from TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v rename to TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v diff --git a/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v similarity index 97% rename from TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v rename to TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 6e71490..099b963 100644 --- a/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -9,7 +9,7 @@ `timescale 1ns / 1ps // ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/define_simulation.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/define_simulation.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" @@ -65,6 +65,6 @@ `endif `ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" `endif diff --git a/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v b/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v similarity index 100% rename from TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v rename to TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v diff --git a/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v similarity index 97% rename from TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v rename to TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 554c65c..5c95b31 100644 --- a/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -9,7 +9,7 @@ `timescale 1ns / 1ps // ------ Include preprocessing flags ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/define_simulation.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" @@ -59,5 +59,5 @@ `endif `ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" `endif