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+# Skywater PDK
+This directory is the workspace for running Synopsys Design Compiler for FPGA primitives
+This required to synthesis decoders in FPGA fabrics
+Please keep this directory clean and organize as follows:
+- **HDL**: Any HDL to synthesis
+- **SCRIPT**: Scripts to enable Design Compile runs
+- **RPT**: Report files from Design Compiler runs 
+- **TEMP**: workspace for Design Compiler projects
+- READMD is the only file allowed in the directory, others should be sub-directories.
+