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[Testbench] Add include netlist for caravel testbench

This commit is contained in:
tangxifan 2020-12-17 20:20:39 -07:00
parent 187364ebc3
commit 7ea8f77038
1 changed files with 18 additions and 0 deletions
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_caravel_include_netlists.v Normal file
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//-------------------------------------------
// A file to include all the dependency HDL codes
// required by Caravel gate-level netlists
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// Design parameter for FPGA bitstream sizes
`define FPGA_BITSTREAM_SIZE 78765
// Include caravel gate-level netlists
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v"
`include "and2_latch_output_verilog.v"
// Include testbench files
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v"
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/spiflash.v"