mirror of https://github.com/lnis-uofu/SOFA.git
[Arch] Use global clock from tile port in caravel architecture
This commit is contained in:
parent
35a64a195c
commit
7dafb7e3b2
|
@ -157,7 +157,7 @@
|
|||
<port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
|
||||
<!-- <port type="input" prefix="reset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true"/> -->
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="true" default_val="0" />
|
||||
<port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" />
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
|
@ -214,6 +214,9 @@
|
|||
<direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||||
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||||
</direct_connection>
|
||||
<tile_annotations>
|
||||
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
|
||||
</tile_annotations>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
|
|
Loading…
Reference in New Issue