diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_frac_dsp18_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_frac_dsp18_skywater130nm_fdhd_cc_openfpga.xml
index 268f885..6d5bb33 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_frac_dsp18_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_frac_dsp18_skywater130nm_fdhd_cc_openfpga.xml
@@ -217,7 +217,7 @@
       <port type="input" prefix="cin" lib_name="S" size="1"/>
       <port type="output" prefix="cout" lib_name="Y" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="mult_18x18" prefix="mult_18x18" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/mult_18x18.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/mult_18x18.v">
+    <circuit_model type="hard_logic" name="frac_mult_18x18" prefix="frac_mult_18x18" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/frac_mult_18x18.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/frac_mult_18x18.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm.xml
index 30e47b9..faeb573 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm.xml
@@ -43,6 +43,15 @@
        that describe them.
   -->
   <models>
+    <model name="mult_9">
+      <input_ports>
+        <port name="A" combinational_sink_ports="Y"/>
+        <port name="B" combinational_sink_ports="Y"/>
+      </input_ports>
+      <output_ports>
+        <port name="Y"/>
+      </output_ports>
+    </model>
     <model name="mult_18">
       <input_ports>
         <port name="A" combinational_sink_ports="Y"/>
@@ -226,8 +235,8 @@
       <pinlocations pattern="custom">
         <loc side="left"></loc>
         <loc side="top" yoffset="1">mult_18.a[0:7] mult_18.b[0:7] mult_18.out[0:7]</loc>
-        <loc side="right" y_offset="1">mult_18.a[8:12] mult_18.b[8:12] mult_18.out[8:21]</loc>
-        <loc side="right" y_offset="0">mult_18.a[13:17] mult_18.b[13:17] mult_18.out[22:35]</loc>
+        <loc side="right" yoffset="1">mult_18.a[8:12] mult_18.b[8:12] mult_18.out[8:21]</loc>
+        <loc side="right" yoffset="0">mult_18.a[13:17] mult_18.b[13:17] mult_18.out[22:35]</loc>
         <loc side="bottom"></loc>
       </pinlocations>
     </tile>