riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Script] Add missing QL synthesis arguments

This commit is contained in:
tangxifan 2021-03-31 11:52:21 -06:00
parent 7643950572
commit 7d8812b844
2 changed files with 4 additions and 0 deletions
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32
generate_sdc/config
task_template.conf
generate_testbench/config
task_template.conf

2
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf
View File

@ -23,6 +23,8 @@ openfpga_vpr_device_layout=32x32
openfpga_vpr_route_chan_width=60 openfpga_vpr_route_chan_width=60
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml
# Yosys parameters
yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
[ARCHITECTURES] [ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml

2
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf
View File

@ -24,6 +24,8 @@ openfpga_vpr_route_chan_width=60
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/prepnr openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/prepnr
openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/SRC/fabric_netlists.v openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/SRC/fabric_netlists.v
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml
# Yosys parameters
yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
[ARCHITECTURES] [ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml