diff --git a/.gitignore b/.gitignore
index 7150d05..80ea0d6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -14,4 +14,5 @@
 */runOpenFPGA
 **/*_task/latest
 **/*_task/run**
-**/*_task/config/task.conf
\ No newline at end of file
+**/*_task/config/task.conf
+.vscode/
diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task.conf b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task.conf
index 66d79ea..5145e73 100644
--- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task.conf
+++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/config/task.conf
@@ -1,4 +1,4 @@
-    # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 # Configuration file for running experiments
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
@@ -8,16 +8,17 @@
 
 [GENERAL]
 run_engine=openfpga_shell
-power_analysis = false
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
 spice_output=false
 verilog_output=true
-timeout_each_job = 20*60
-fpga_flow=vpr_blif
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
 arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
 
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
+openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
 openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
@@ -28,12 +29,10 @@ openfpga_vpr_route_chan_width=60
 arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
 
 [BENCHMARKS]
-bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
+bench0=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
-bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
+bench0_top = counter
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-vpr_fpga_verilog_formal_verification_top_netlist=
+#end_flow_with_test=
diff --git a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga
index 1318a22..1dcf136 100644
--- a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga
+++ b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga
@@ -46,6 +46,7 @@ build_fabric_bitstream --verbose
 
 # Write fabric-dependent bitstream
 write_fabric_bitstream --file fabric_bitstream.xml --format xml
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists