diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml index fc8e81d..b47dbcd 100644 --- a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml +++ b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml @@ -18,9 +18,9 @@ LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 -LUT3_DELAY: 2.31e-9 -LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9 -LUT4_DELAY: 2.6e-9 -LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +LUT3_DELAY: 0.86e-9 +LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9 +LUT4_DELAY: 1.14e-9 +LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9 REGIN_TO_FF0_DELAY: 0.58e-9 FF0_TO_FF1_DELAY: 0.56e-9 diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml index a7eb774..4c4e441 100644 --- a/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml +++ b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml @@ -18,9 +18,9 @@ LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 -LUT3_DELAY: 2.31e-9 -LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9 -LUT4_DELAY: 2.6e-9 -LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +LUT3_DELAY: 0.92e-9 +LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9 +LUT4_DELAY: 1.21e-9 +LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9 REGIN_TO_FF0_DELAY: 1.12e-9 FF0_TO_FF1_DELAY: 0.56e-9 diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg index 8b7cb01..eba2802 100644 --- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg @@ -1,6 +1,6 @@ - + @@ -23,8 +23,8 @@ - Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000 - + Produced by OmniGraffle 7.18.4\n2021-04-03 20:07:23 +0000 + schematic_timing 图层 1 @@ -392,6 +392,11 @@ A + + + B + + diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst index c5cfbf4..7d2745a 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_timing.rst @@ -8,12 +8,12 @@ Timing Annotation Configurable Logic Block ^^^^^^^^^^^^^^^^^^^^^^^^ -The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`. +The path delays in :numref:`fig_qlsofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`. .. _fig_qlsofa_hd_fle_arch_timing: .. figure:: ./figures/qlsofa_hd_fle_arch_timing.svg - :scale: 30% + :width: 80% :alt: Schematic of a logic element used in QLSOFA HD FPGA Schematic of a logic element used in QLSOFA HD FPGA @@ -25,25 +25,27 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:` +-------------------------+------------------------------+ | Path / Delay | TT (unit: ns) | +=========================+==============================+ - | in0 -> LUT3_out[0] [1]_ | 2.31 | + | in0 -> LUT3_out[0] | 0.85 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[0] [1]_ | 2.31 | + | in1 -> LUT3_out[0] | 0.57 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[0] [1]_ | 2.31 | + | in2 -> B | 0.60 | +-------------------------+------------------------------+ - | in0 -> LUT3_out[1] [1]_ | 2.31 | + | B -> LUT3_out[0] | 0.32 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[1] [1]_ | 2.31 | + | in0 -> LUT3_out[1] | 0.90 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[1] [1]_ | 2.31 | + | in1 -> LUT3_out[1] | 0.62 | +-------------------------+------------------------------+ - | in0 -> LUT4_out [1]_ | 2.60 | + | B -> LUT3_out[1] | 0.33 | +-------------------------+------------------------------+ - | in1 -> LUT4_out [1]_ | 2.60 | + | in0 -> LUT4_out | 1.17 | +-------------------------+------------------------------+ - | in2 -> LUT4_out [1]_ | 2.60 | + | in1 -> LUT4_out | 0.89 | +-------------------------+------------------------------+ - | in3 -> LUT4_out [1]_ | 2.60 | + | in2 -> LUT4_out | 1.21 | + +-------------------------+------------------------------+ + | in3 -> LUT4_out | 0.79 | +-------------------------+------------------------------+ | LUT3_out[0] -> A | 0.56 | +-------------------------+------------------------------+ @@ -66,8 +68,6 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:` | FF[0] -> FF[1] | 0.56 | +-------------------------+------------------------------+ -.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. - .. _qlsofa_hd_timing_io: I/O Block diff --git a/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg index 8b7cb01..eba2802 100644 --- a/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg +++ b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_fle_arch_timing.svg @@ -1,6 +1,6 @@ - + @@ -23,8 +23,8 @@ - Produced by OmniGraffle 7.18.4\n2021-04-02 20:35:25 +0000 - + Produced by OmniGraffle 7.18.4\n2021-04-03 20:07:23 +0000 + schematic_timing 图层 1 @@ -392,6 +392,11 @@ A + + + B + + diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst index 65fef7a..d48623a 100644 --- a/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_timing.rst @@ -13,7 +13,7 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref: .. _fig_sofa_chd_fle_arch_timing: .. figure:: ./figures/sofa_chd_fle_arch_timing.svg - :scale: 30% + :width: 80% :alt: Schematic of a logic element used in SOFA CHD FPGA Schematic of a logic element used in SOFA CHD FPGA @@ -25,25 +25,27 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref: +-------------------------+------------------------------+ | Path / Delay | TT (unit: ns) | +=========================+==============================+ - | in0 -> LUT3_out[0] [1]_ | 2.31 | + | in0 -> LUT3_out[0] | 0.85 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[0] [1]_ | 2.31 | + | in1 -> LUT3_out[0] | 0.57 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[0] [1]_ | 2.31 | + | in2 -> B | 0.60 | +-------------------------+------------------------------+ - | in0 -> LUT3_out[1] [1]_ | 2.31 | + | B -> LUT3_out[0] | 0.32 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[1] [1]_ | 2.31 | + | in0 -> LUT3_out[1] | 0.90 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[1] [1]_ | 2.31 | + | in1 -> LUT3_out[1] | 0.62 | +-------------------------+------------------------------+ - | in0 -> LUT4_out [1]_ | 2.60 | + | B -> LUT3_out[1] | 0.33 | +-------------------------+------------------------------+ - | in1 -> LUT4_out [1]_ | 2.60 | + | in0 -> LUT4_out | 1.17 | +-------------------------+------------------------------+ - | in2 -> LUT4_out [1]_ | 2.60 | + | in1 -> LUT4_out | 0.89 | +-------------------------+------------------------------+ - | in3 -> LUT4_out [1]_ | 2.60 | + | in2 -> LUT4_out | 1.21 | + +-------------------------+------------------------------+ + | in3 -> LUT4_out | 0.79 | +-------------------------+------------------------------+ | LUT3_out[0] -> A | 0.56 | +-------------------------+------------------------------+ @@ -66,7 +68,6 @@ The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref: | FF[0] -> FF[1] | 0.56 | +-------------------------+------------------------------+ -.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. .. _sofa_chd_timing_io: diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst index 731eb72..104a7da 100644 --- a/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_timing.rst @@ -13,7 +13,7 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:` .. _fig_sofa_hd_fle_arch_timing: .. figure:: ./figures/sofa_hd_fle_arch_timing.svg - :scale: 30% + :width: 80% :alt: Schematic of a logic element used in SOFA HD FPGA Schematic of a logic element used in SOFA HD FPGA @@ -25,25 +25,25 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:` +-------------------------+------------------------------+ | Path / Delay | TT (unit: ns) | +=========================+==============================+ - | in0 -> LUT3_out[0] [1]_ | 2.31 | + | in0 -> LUT3_out[0] | 0.85 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[0] [1]_ | 2.31 | + | in1 -> LUT3_out[0] | 0.57 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[0] [1]_ | 2.31 | + | in2 -> LUT3_out[0] | 0.30 | +-------------------------+------------------------------+ - | in0 -> LUT3_out[1] [1]_ | 2.31 | + | in0 -> LUT3_out[1] | 0.86 | +-------------------------+------------------------------+ - | in1 -> LUT3_out[1] [1]_ | 2.31 | + | in1 -> LUT3_out[1] | 0.59 | +-------------------------+------------------------------+ - | in2 -> LUT3_out[1] [1]_ | 2.31 | + | in2 -> LUT3_out[1] | 0.31 | +-------------------------+------------------------------+ - | in0 -> LUT4_out [1]_ | 2.60 | + | in0 -> LUT4_out | 1.14 | +-------------------------+------------------------------+ - | in1 -> LUT4_out [1]_ | 2.60 | + | in1 -> LUT4_out | 0.86 | +-------------------------+------------------------------+ - | in2 -> LUT4_out [1]_ | 2.60 | + | in2 -> LUT4_out | 0.58 | +-------------------------+------------------------------+ - | in3 -> LUT4_out [1]_ | 2.60 | + | in3 -> LUT4_out | 0.51 | +-------------------------+------------------------------+ | LUT3_out[0] -> A | 0.56 | +-------------------------+------------------------------+ @@ -66,8 +66,6 @@ The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:` | FF[0] -> FF[1] | 0.56 | +-------------------------+------------------------------+ -.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques. - .. _sofa_hd_timing_io: I/O Block diff --git a/SNPS_PT/SCRIPT/report_timing_cb.tcl b/SNPS_PT/SCRIPT/report_timing_cb.tcl index fd5fb73..ea32e88 100644 --- a/SNPS_PT/SCRIPT/report_timing_cb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_cb.tcl @@ -5,19 +5,23 @@ # ################################## # Define environment variables +# +set DEVICE_NAME "SOFA_HD" +#set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; -set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; - -#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; -set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; -#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; - -#set DEVICE_NAME "SOFA_HD" -set DEVICE_NAME "QLSOFA_HD" -#set DEVICE_NAME "SOFA_CHD" +if {"SOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"SOFA_CHD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; +} set TIMING_REPORT_HOME "../TIMING_REPORTS/"; diff --git a/SNPS_PT/SCRIPT/report_timing_clb.tcl b/SNPS_PT/SCRIPT/report_timing_clb.tcl index 91a7314..f983c50 100644 --- a/SNPS_PT/SCRIPT/report_timing_clb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_clb.tcl @@ -5,19 +5,23 @@ ################################## # Define environment variables +# +set DEVICE_NAME "SOFA_HD" +#set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; -set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; - -#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; -set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; -#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; - -#set DEVICE_NAME "SOFA_HD" -set DEVICE_NAME "QLSOFA_HD" -#set DEVICE_NAME "SOFA_CHD" +if {"SOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"SOFA_CHD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; +} set TIMING_REPORT_HOME "../TIMING_REPORTS/"; @@ -51,12 +55,16 @@ link_design ${DESIGN_NAME} ######################################### # Setup constraints to break combinational loops -if {${DEVICE_NAME} eq "SOFA_HD"} { +if {${DEVICE_NAME} == "SOFA_HD"} { set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q } else { # QLSOFA and SOFA CHD use a LUT with carry logic, the memory is deeper in hierarchy # Also QLSOFA and SOFA CHD use a different FF cell as configuration memory - set_disable_timing */*/*/*/*/*mem/sky*_fd_sc_hd__dfrtp_*_*_/Q + set_disable_timing */*/*/*/*mem*/sky*_fd_sc_hd__dfrtp_*_*_/Q + set_disable_timing */*/*/*/*/*mem*/sky*_fd_sc_hd__dfrtp_*_*_/Q + #Disable cin/cout paths + set_disable_timing logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/frac_logic_cin + set_disable_timing logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/frac_logic_cout } # ########################################## @@ -72,20 +80,46 @@ read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef ################################## # Report timing of Connect block # LUT4 output timing -report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt +set LUT_INPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in" +set LUT4_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out" + +# Walk through all the input pin and output pin paths +for {set ipin 0} {$ipin < 4} {incr ipin} { + if {0 == $ipin} { + report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT4_OUTPUT_PORT_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt + } else { + report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT4_OUTPUT_PORT_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt + } +} + # LUT3 output timing -report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt +set LUT3_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out" + +# Walk through all the input pin and output pin paths +for {set ipin 0} {$ipin < 3} {incr ipin} { + for {set opin 0} {$opin < 2} {incr opin} { + if {0 == $ipin && 0 == $opin} { + report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT3_OUTPUT_PORT_NAME}[$opin] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt + } else { + report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT3_OUTPUT_PORT_NAME}[$opin] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt + } + } +} # Output selector timing -report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt -report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt -report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt -report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt +set FRAC_LOGIC_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]" +set FF_PATH "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff" +set FLE_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out" + +report_timing -from ${FF_PATH}_0/ff_Q[0] -to ${FLE_OUTPUT_PORT_NAME}[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt +report_timing -from ${FRAC_LOGIC_OUTPUT_PORT_NAME}[0] -to ${FLE_OUTPUT_PORT_NAME}[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt +report_timing -from ${FF_PATH}_1/ff_Q[0] -to ${FLE_OUTPUT_PORT_NAME}[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt +report_timing -from ${FRAC_LOGIC_OUTPUT_PORT_NAME}[1] -to ${FLE_OUTPUT_PORT_NAME}[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt # LUT output to FF input timing -report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt -report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt -report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt +report_timing -from ${LUT4_OUTPUT_PORT_NAME} -to ${FF_PATH}_0/ff_D[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt +report_timing -from ${LUT3_OUTPUT_PORT_NAME} -to ${FF_PATH}_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt +report_timing -from ${LUT3_OUTPUT_PORT_NAME} -to ${FF_PATH}_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt # TODO: Carry logic timing diff --git a/SNPS_PT/SCRIPT/report_timing_io.tcl b/SNPS_PT/SCRIPT/report_timing_io.tcl index 5714dfc..095a3a8 100644 --- a/SNPS_PT/SCRIPT/report_timing_io.tcl +++ b/SNPS_PT/SCRIPT/report_timing_io.tcl @@ -5,19 +5,24 @@ ################################## # Define environment variables +# +set DEVICE_NAME "SOFA_HD" +#set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; -set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; +if {"SOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"SOFA_CHD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; +} -#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; -set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; -#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; - -#set DEVICE_NAME "SOFA_HD" -set DEVICE_NAME "QLSOFA_HD" -#set DEVICE_NAME "SOFA_CHD" set TIMING_REPORT_HOME "../TIMING_REPORTS/"; diff --git a/SNPS_PT/SCRIPT/report_timing_sb.tcl b/SNPS_PT/SCRIPT/report_timing_sb.tcl index 9e426b7..72a8c72 100644 --- a/SNPS_PT/SCRIPT/report_timing_sb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_sb.tcl @@ -5,19 +5,23 @@ ################################## # Define environment variables + +set DEVICE_NAME "SOFA_HD" +#set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; -set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; - -#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; -set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; -#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; - -#set DEVICE_NAME "SOFA_HD" -set DEVICE_NAME "QLSOFA_HD" -#set DEVICE_NAME "SOFA_CHD" +if {"SOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"SOFA_CHD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; +} set TIMING_REPORT_HOME "../TIMING_REPORTS/"; # Enable preprocessing in Verilog parser