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Merge remote-tracking branch 'origin/master' into ganesh_dev

This commit is contained in:
Ganesh Gore 2021-04-03 16:27:10 -06:00
parent 78e2a242b3 7c974f48ef
commit 7c0ba0ad94
62 changed files with 1785273 additions and 446 deletions
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270
ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -1,14 +1,14 @@
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block - General purpose logic block
- K = 6, N = 10, I = 40 - K = 6, N = 10, I = 40
- Single mode - Single mode
- Routing architecture - Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1 - L = 4, fc_in = 0.15, fc_out = 0.1
- Skywater 130nm PDK - Skywater 130nm PDK
- circuit models are binded to the opensource skywater - circuit models are binded to the opensource skywater
foundry middle-speed (ms) standard cell library foundry middle-speed (ms) standard cell library
--> -->
<openfpga_architecture> <openfpga_architecture>
<technology_library> <technology_library>
<device_library> <device_library>
@ -43,6 +43,18 @@
10e-12 10e-12
</delay_matrix> </delay_matrix>
</circuit_model> </circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_1" prefix="sky130_fd_sc_hd__buf_1" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v">
<design_technology type="cmos" topology="buffer" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"> <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/> <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
@ -67,6 +79,30 @@
10e-12 10e-12
</delay_matrix> </delay_matrix>
</circuit_model> </circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_8" prefix="sky130_fd_sc_hd__buf_8" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_16" prefix="sky130_fd_sc_hd__buf_16" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"> <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
<design_technology type="cmos" topology="buffer" size="1"/> <design_technology type="cmos" topology="buffer" size="1"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
@ -79,6 +115,35 @@
10e-12 10e-12
</delay_matrix> </delay_matrix>
</circuit_model> </circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_4" prefix="sky130_fd_sc_hd__inv_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v">
<design_technology type="cmos" topology="buffer" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<!-- Trick OpenFPGA to avoid auto-generating TGATE modules, which are not used in PnR -->
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/fd_hd_mux_custom_cells_tt.v">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"> <circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
<design_technology type="cmos" topology="OR"/> <design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
@ -95,12 +160,12 @@
</delay_matrix> </delay_matrix>
</circuit_model> </circuit_model>
<!-- Define a circuit model for the standard cell MUX2 <!-- Define a circuit model for the standard cell MUX2
OpenFPGA requires the following truth table for the MUX2 OpenFPGA requires the following truth table for the MUX2
When the select signal sel is enabled, the first input, i.e., in0 When the select signal sel is enabled, the first input, i.e., in0
will be propagated to the output, i.e., out will be propagated to the output, i.e., out
If your standard cell provider does not offer the exact truth table, If your standard cell provider does not offer the exact truth table,
you can simply swap the inputs as shown in the example below you can simply swap the inputs as shown in the example below
--> -->
<circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"> <circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
<design_technology type="cmos" topology="MUX2"/> <design_technology type="cmos" topology="MUX2"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
@ -118,7 +183,7 @@
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE --> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -127,7 +192,79 @@
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined --> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_1"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf4" prefix="mux_2level_tapbuf4" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf8" prefix="mux_2level_tapbuf8" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_8"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf16" prefix="mux_2level_tapbuf16" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_16"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level" prefix="mux_1level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="1" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_io" prefix="mux_1level_io" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="1" local_encoder="false"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_1"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_fabric" prefix="mux_1level_fabric" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="1" local_encoder="false"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_1"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="1" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_4"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -147,7 +284,6 @@
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/> <port type="sram" prefix="sram" size="1"/>
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="sky130_fd_sc_hd__sdfrtp_1" prefix="sky130_fd_sc_hd__sdfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"> <circuit_model type="ff" name="sky130_fd_sc_hd__sdfrtp_1" prefix="sky130_fd_sc_hd__sdfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
@ -167,33 +303,50 @@
<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/> <lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/> <lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/> <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/> <port type="input" prefix="in" size="4"/>
<port type="output" prefix="lut2_out" size="2" lut_frac_level="2" lut_output_mask="2,3"/> <port type="output" prefix="lut2_out" size="2" lut_frac_level="2" lut_output_mask="2,3"/>
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/> <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!-- new ccFF -->
<circuit_model type="ccff" name="sky130_fd_sc_hd__dfrtp_1" prefix="sky130_fd_sc_hd__dfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"> <circuit_model type="ccff" name="QL_CCFF" prefix="QL_CCFF" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/ql_ccff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="CFG_DONE" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="SI" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="CFGQN" size="1"/>
<port type="output" prefix="CFGQ" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="EMBEDDED_IO_HD" prefix="EMBEDDED_IO_HD" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v"> <!-- dummy stdcell pointer -->
<circuit_model type="inv_buf" name="dummy1" prefix="dummy1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="dummy2" prefix="dummy2" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="dummy3" prefix="dummy3" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_4.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="dummy4" prefix="dummy4" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="iopad" name="IO" prefix="IO" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/ql_iso_io_logic.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/> <port type="input" prefix="A2F" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/> <port type="output" prefix="F2A" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/> <port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/> <port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/> <port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
<port type="input" prefix="CFG_DONE" lib_name="CFG_DONE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="sram" prefix="io_dir" lib_name="FPGA_IO_DIR" size="1" mode_select="true" circuit_model_name="QL_CCFF" default_val="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/sky130_fd_sc_hd_wrapper.v"> <circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/sky130_fd_sc_hd_wrapper.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -207,7 +360,7 @@
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" num_regions="1"/> <organization type="scan_chain" circuit_model_name="QL_CCFF" num_regions="1"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
@ -228,37 +381,60 @@
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/> <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection> </direct_connection>
<tile_annotations> <tile_annotations>
<global_port name="clk" is_clock="true" default_val="0"> <global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk[0:3]" x="-1" y="-1"/> <tile name="clb" port="clk[0:3]" x="-1" y="-1"/>
</global_port> <tile name="io_top" port="clk[0:3]" x="-1" y="-1"/>
<global_port name="Reset" is_reset="true" default_val="1"> <tile name="io_right" port="clk[0:3]" x="-1" y="-1"/>
<tile name="clb" port="reset" x="-1" y="-1"/> <tile name="io_bottom" port="clk[0:3]" x="-1" y="-1"/>
</global_port> <tile name="io_left" port="clk[0:3]" x="-1" y="-1"/>
</global_port>
<global_port name="reset" is_reset="true" default_val="1">
<tile name="clb" port="reset" x="-1" y="-1"/>
<tile name="io_top" port="reset" x="-1" y="-1"/>
<tile name="io_right" port="reset" x="-1" y="-1"/>
<tile name="io_bottom" port="reset" x="-1" y="-1"/>
<tile name="io_left" port="reset" x="-1" y="-1"/>
</global_port>
</tile_annotations> </tile_annotations>
<pb_type_annotations> <pb_type_annotations>
<!-- physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/> <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! --> <!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
<pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/> <pb_type name="io[physical].iopad">
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <interconnect name="mux1" circuit_model_name="mux_1level_io"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <interconnect name="mux2" circuit_model_name="mux_1level_io"/>
<!-- End physical pb_type binding in complex block IO --> </pb_type>
<pb_type name="io[physical].iopad.pad" circuit_model_name="IO" mode_bits="1"/>
<pb_type name="io[io_input].io_input.inpad" physical_pb_type_name="io[physical].iopad.pad" mode_bits="1"/>
<pb_type name="io[io_output].io_output.outpad" physical_pb_type_name="io[physical].iopad.pad" mode_bits="0"/>
<!-- physical pb_type binding in complex block CLB --> <pb_type name="io[physical].iopad.ff" circuit_model_name="sky130_fd_sc_hd__sdfrtp_1"/>
<pb_type name="io[io_input].io_input.ff" physical_pb_type_name="io[physical].iopad.ff" physical_pb_type_index_offset="1"/>
<pb_type name="io[io_output].io_output.ff" physical_pb_type_name="io[physical].iopad.ff" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<pb_type name="clb.fle[physical].fabric">
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
<interconnect name="mux1" circuit_model_name="mux_1level_fabric"/>
<interconnect name="mux2" circuit_model_name="mux_1level_fabric"/>
</pb_type>
<pb_type name="clb.fle[physical].fabric.frac_logic">
<interconnect name="mux2" circuit_model_name="mux_1level_fabric"/>
</pb_type>
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="sky130_fd_sc_hd__mux2_1_wrapper"/> <pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="sky130_fd_sc_hd__mux2_1_wrapper"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfrtp_1"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfrtp_1"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'ble4' --> <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4">
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 --> <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:3]"/> <port name="in" physical_mode_port="in[0:3]"/>
<port name="out" physical_mode_port="lut4_out"/> <port name="out" physical_mode_port="lut4_out"/>
</pb_type> </pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/> <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<!-- Binding operating pb_types in mode 'shift_register' --> <!-- Binding operating pb_types in mode 'shift_register' -->
<pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/> <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations> </pb_type_annotations>

26
ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml Normal file
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@ -0,0 +1,26 @@
L1_SB_MUX_DELAY: 1.61e-9
L2_SB_MUX_DELAY: 1.61e-9
L4_SB_MUX_DELAY: 1.61e-9
CB_MUX_DELAY: 1.38e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 0.86e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.14e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 0.58e-9
FF0_TO_FF1_DELAY: 0.56e-9

26
ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml Normal file
View File

@ -0,0 +1,26 @@
L1_SB_MUX_DELAY: 1.44e-9
L2_SB_MUX_DELAY: 1.44e-9
L4_SB_MUX_DELAY: 1.44e-9
CB_MUX_DELAY: 1.38e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 2.31e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9
LUT4_DELAY: 2.6e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9
REGIN_TO_FF0_DELAY: 1.12e-9
FF0_TO_FF1_DELAY: 0.56e-9

26
ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml Normal file
View File

@ -0,0 +1,26 @@
L1_SB_MUX_DELAY: 1.44e-9
L2_SB_MUX_DELAY: 1.44e-9
L4_SB_MUX_DELAY: 1.44e-9
CB_MUX_DELAY: 1.38e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT3_DELAY: 0.92e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.21e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
REGIN_TO_FF0_DELAY: 1.12e-9
FF0_TO_FF1_DELAY: 0.56e-9

427
ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,27 +1,27 @@
<!-- <!--
Low-cost homogeneous FPGA Architecture. Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology - Skywater 130 nm technology
- General purpose logic block: - General purpose logic block:
K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
with optionally registered outputs with optionally registered outputs
- Routing architecture: - Routing architecture:
- 10% L = 1, fc_in = 0.15, Fc_out = 0.10 - 10% L = 1, fc_in = 0.15, Fc_out = 0.10
- 10% L = 2, fc_in = 0.15, Fc_out = 0.10 - 10% L = 2, fc_in = 0.15, Fc_out = 0.10
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10 - 80% L = 4, fc_in = 0.15, Fc_out = 0.10
- 100 routing tracks per channel - 100 routing tracks per channel
Authors: Xifan Tang Authors: Xifan Tang
--> -->
<architecture> <architecture>
<!-- <!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
@ -36,7 +36,7 @@
<model name="frac_lut4"> <model name="frac_lut4">
<input_ports> <input_ports>
<port name="in"/> <port name="in" combinational_sink_ports="lut2_out lut4_out"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="lut2_out"/> <port name="lut2_out"/>
@ -45,9 +45,9 @@
</model> </model>
<model name="carry_follower"> <model name="carry_follower">
<input_ports> <input_ports>
<port name="a"/> <port name="a" combinational_sink_ports="cout"/>
<port name="b"/> <port name="b" combinational_sink_ports="cout"/>
<port name="cin"/> <port name="cin" combinational_sink_ports="cout"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="cout"/> <port name="cout"/>
@ -68,19 +68,28 @@
</models> </models>
<tiles> <tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<!-- Top-side has 1 I/O per tile --> <!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="16" area="0"> <tile name="io_top" capacity="16" area="0">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <clock name="clk" num_pins="4"/>
<output name="inpad" num_pins="1"/> <input name="f2a_i" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <output name="a2f_o" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc> <loc side="bottom">io_top.a2f_o io_top.f2a_i io_top.clk io_top.sc_in io_top.sc_out io_top.reset</loc>
</pinlocations> </pinlocations>
</tile> </tile>
<!-- Right-side has 1 I/O per tile --> <!-- Right-side has 1 I/O per tile -->
@ -88,11 +97,20 @@
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <clock name="clk" num_pins="4"/>
<output name="inpad" num_pins="1"/> <input name="f2a_i" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <output name="a2f_o" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc> <loc side="left">io_right.a2f_o io_right.f2a_i io_right.clk io_right.sc_in io_right.sc_out io_right.reset</loc>
</pinlocations> </pinlocations>
</tile> </tile>
<!-- Bottom-side has 9 I/O per tile --> <!-- Bottom-side has 9 I/O per tile -->
@ -100,11 +118,20 @@
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <clock name="clk" num_pins="4"/>
<output name="inpad" num_pins="1"/> <input name="f2a_i" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <output name="a2f_o" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc> <loc side="top">io_bottom.a2f_o io_bottom.f2a_i io_bottom.clk io_bottom.sc_in io_bottom.sc_out io_bottom.reset</loc>
</pinlocations> </pinlocations>
</tile> </tile>
<!-- Left-side has 1 I/O per tile --> <!-- Left-side has 1 I/O per tile -->
@ -112,11 +139,20 @@
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <clock name="clk" num_pins="4"/>
<output name="inpad" num_pins="1"/> <input name="f2a_i" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <output name="a2f_o" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc> <loc side="right">io_left.a2f_o io_left.f2a_i io_left.clk io_left.sc_in io_left.sc_out io_left.reset</loc>
</pinlocations> </pinlocations>
</tile> </tile>
<!-- CLB has most pins on the top and right sides --> <!-- CLB has most pins on the top and right sides -->
@ -164,7 +200,7 @@
<col type="io_left" startx="0" priority="100"/> <col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/> <col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
@ -174,7 +210,7 @@
<col type="io_left" startx="0" priority="100"/> <col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/> <col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="12x12" width="14" height="14"> <fixed_layout name="12x12" width="14" height="14">
@ -184,7 +220,7 @@
<col type="io_left" startx="0" priority="100"/> <col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/> <col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="32x32" width="34" height="34"> <fixed_layout name="32x32" width="34" height="34">
@ -194,30 +230,30 @@
<col type="io_left" startx="0" priority="100"/> <col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/> <col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV. lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm). We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm). Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables. by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
@ -228,28 +264,28 @@
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive. buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples. (diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.20" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L1" freq="0.20" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="L1_mux"/> <mux name="L1_mux"/>
@ -275,64 +311,132 @@
<complexblocklist> <complexblocklist>
<!-- Define input pads begin --> <!-- Define input pads begin -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <clock name="clk" num_pins="4"/>
<output name="inpad" num_pins="1"/> <input name="f2a_i" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <output name="a2f_o" num_pins="1"/>
If you need to register the I/O, define clocks in the circuit models <input name="sc_in" num_pins="1"/>
These clocks can be handled in back-end <output name="sc_out" num_pins="1"/>
--> <input name="reset" num_pins="1" is_non_clock_global="true"/>
<!-- A mode denotes the physical implementation of an I/O <!-- Physical mode definition begin (physical implementation of the io) -->
This mode will be not packable but is mainly used for fabric verilog generation
-->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disabled_in_pack="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" num_pb="1">
<input name="outpad" num_pins="1"/> <clock name="clk" num_pins="1"/>
<output name="inpad" num_pins="1"/> <input name="f2a_i" num_pins="1"/>
<output name="a2f_o" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<input name="reset" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<pb_type name="ff" blif_model=".subckt scff" num_pb="2">
<input name="D" num_pins="1" port_class="D"/>
<input name="DI" num_pins="1"/>
<input name="reset" num_pins="1"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/>
<T_setup value="66e-12" port="ff.reset" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<pb_type name="pad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="ff[0:0]-clk" input="iopad.clk" output="ff[0:0].clk"/>
<direct name="ff[1:1]-clk" input="iopad.clk" output="ff[1:1].clk"/>
<direct name="ff[0:0]-D" input="iopad.f2a_i" output="ff[0:0].D" />
<direct name="ff[1:1]-D" input="pad.inpad" output="ff[1:1].D"/>
<direct name="ff[0:0]-DI" input="iopad.sc_in" output="ff[0:0].DI"/>
<direct name="ff[1:1]-DI" input="ff[0:0].Q" output="ff[1:1].DI"/>
<direct name="iopad-sc_out" input="ff[1:1].Q" output="iopad.sc_out"/>
<complete name="complete1" input="iopad.reset" output="ff[1:0].reset"/>
<mux name="mux1" input="iopad.f2a_i ff[0:0].Q" output="pad.outpad">
<delay_constant max="25e-12" in_port="iopad.f2a_i" out_port="pad.outpad"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="pad.outpad"/>
</mux>
<mux name="mux2" input="pad.inpad ff[1:1].Q" output="iopad.a2f_o">
<delay_constant max="25e-12" in_port="pad.inpad" out_port="iopad.a2f_o"/>
<delay_constant max="45e-12" in_port="ff[1:1].Q" out_port="iopad.a2f_o"/>
</mux>
</interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <complete name="clks" input="io.clk" output="iopad.clk"/>
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <direct name="direct3" input="io.f2a_i" output="iopad.f2a_i"/>
</direct> <direct name="direct4" input="iopad.a2f_o" output="io.a2f_o"/>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="direct6" input="io.sc_in" output="iopad.sc_in"/>
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <direct name="direct7" input="iopad.sc_out" output="io.sc_out"/>
</direct> <direct name="direct8" input="io.reset" output="iopad.reset"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Physical mode definition end (physical implementation of the io) -->
<!-- IOs can operate as either inputs or outputs. <mode name="io_output">
Delays below come from Ian Kuon. They are small, so they should be interpreted as <pb_type name="io_output" num_pb="1">
the delays to and from registers in the I/O (and generally I/Os are registered <clock name="clk" num_pins="1"/>
today and that is when you timing analyze them. <input name="f2a_i" num_pins="1"/>
--> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<mode name="inpad"> <input name="D" num_pins="1" port_class="D"/>
<pb_type name="inpad" blif_model=".input" num_pb="1"> <output name="Q" num_pins="1" port_class="Q"/>
<output name="inpad" num_pins="1"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="ff-clk" input="io_output.clk" output="ff.clk"/>
<direct name="ff-D" input="io_output.f2a_i" output="ff.D"/>
<mux name="mux1" input="ff.Q io_output.f2a_i" output="outpad.outpad">
<pack_pattern name="pack-OREG" in_port="ff.Q" out_port="outpad.outpad"/>
<delay_constant max="25e-12" in_port="io_output.f2a_i" out_port="outpad.outpad"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="outpad.outpad"/>
</mux>
</interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <complete name="io_output-clk" input="io.clk" output="io_output.clk"/>
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <direct name="io_output-f2a_i" input="io.f2a_i" output="io_output.f2a_i"/>
</direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="io_input">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="io_input" num_pb="1">
<input name="outpad" num_pins="1"/> <clock name="clk" num_pins="1"/>
<output name="a2f_o" num_pins="1"/>
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="ff-clk" input="io_input.clk" output="ff.clk"/>
<direct name="ff-D" input="inpad.inpad" output="ff.D">
<pack_pattern name="pack-IREG" in_port="inpad.inpad" out_port="ff.D"/>
</direct>
<mux name="mux2" input="inpad.inpad ff.Q" output="io_input.a2f_o">
<delay_constant max="25e-12" in_port="inpad.inpad" out_port="io_input.a2f_o"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="io_input.a2f_o"/>
</mux>
</interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="io-a2f_o" input="io_input.a2f_o" output="io.a2f_o"/>
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <complete name="io_input-clk" input="io.clk" output="io_input.clk"/>
</direct>
</interconnect> </interconnect>
</mode> </mode>
<power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!-- -Due to the absence of local routing, <!-- -Due to the absence of local routing,
the 4 inputs of fracturable LUT4 are no longer equivalent, the 4 inputs of fracturable LUT4 are no longer equivalent,
because the 4th input can not be switched when the dual-LUT3 modes are used. because the 4th input can not be switched when the dual-LUT3 modes are used.
So pin equivalence should be applied to the first 3 inputs only So pin equivalence should be applied to the first 3 inputs only
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="24" equivalent="full"/> <input name="I" num_pins="24" equivalent="full"/>
<input name="reg_in" num_pins="1"/> <input name="reg_in" num_pins="1"/>
@ -345,9 +449,9 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<output name="cout_copy" num_pins="1"/> <output name="cout_copy" num_pins="1"/>
<clock name="clk" num_pins="4"/> <clock name="clk" num_pins="4"/>
<!-- Describe fracturable logic element. <!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered The outputs of the fracturable logic element can be optionally registered
--> -->
<pb_type name="fle" num_pb="8"> <pb_type name="fle" num_pb="8">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
@ -360,7 +464,7 @@
<output name="sc_out" num_pins="1"/> <output name="sc_out" num_pins="1"/>
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disabled_in_pack="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
@ -378,17 +482,39 @@
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1"> <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="lut2_out" num_pins="2"/> <output name="lut2_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/> <output name="lut4_out" num_pins="1"/>
<!-- FIXME: Timing values taken from the pb_type implementing .names.
May require adjustments as delays may differ between lut2_out and lut4_out -->
<delay_matrix type="max" in_port="frac_lut4.in" out_port="frac_lut4.lut2_out">
261e-12
261e-12
261e-12
261e-12
261e-12
261e-12
261e-12
261e-12
</delay_matrix>
<delay_matrix type="max" in_port="frac_lut4.in" out_port="frac_lut4.lut4_out">
261e-12
261e-12
261e-12
261e-12
</delay_matrix>
</pb_type> </pb_type>
<pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1"> <pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1">
<input name="a" num_pins="1"/> <input name="a" num_pins="1"/>
<input name="b" num_pins="1"/> <input name="b" num_pins="1"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<!-- FIXME: Completely fake timing data -->
<delay_constant max="100e-12" in_port="carry_follower.a" out_port="carry_follower.cout"/>
<delay_constant max="100e-12" in_port="carry_follower.b" out_port="carry_follower.cout"/>
<delay_constant max="100e-12" in_port="carry_follower.cin" out_port="carry_follower.cout"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="frac_logic.in[0:1]" output="frac_lut4.in[0:1]"/> <direct name="direct1" input="frac_logic.in[0:1]" output="frac_lut4.in[0:1]"/>
@ -397,7 +523,6 @@
<direct name="direct4" input="frac_lut4.lut2_out[1:1]" output="carry_follower.a"/> <direct name="direct4" input="frac_lut4.lut2_out[1:1]" output="carry_follower.a"/>
<direct name="direct5" input="frac_lut4.lut2_out[0:0]" output="carry_follower.cin"/> <direct name="direct5" input="frac_lut4.lut2_out[0:0]" output="carry_follower.cin"/>
<direct name="direct6" input="carry_follower.cout" output="frac_logic.cout"/> <direct name="direct6" input="carry_follower.cout" output="frac_logic.cout"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<direct name="direct7" input="frac_lut4.lut4_out" output="frac_logic.out"/> <direct name="direct7" input="frac_lut4.lut4_out" output="frac_logic.out"/>
<mux name="mux2" input="frac_logic.cin frac_logic.in[2:2]" output="frac_lut4.in[2:2]"/> <mux name="mux2" input="frac_logic.cin frac_logic.in[2:2]" output="frac_lut4.in[2:2]"/>
</interconnect> </interconnect>
@ -416,8 +541,8 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="fabric.sc_in" output="ff.DI"/> <direct name="direct2" input="fabric.sc_in" output="ff.DI"/>
<direct name="direct3" input="fabric.cin" output="frac_logic.cin"/> <direct name="direct3" input="fabric.cin" output="frac_logic.cin"/>
<direct name="direct4" input="ff.Q" output="fabric.sc_out"/> <direct name="direct4" input="ff.Q" output="fabric.sc_out"/>
<direct name="direct5" input="ff.Q" output="fabric.reg_out"/> <direct name="direct5" input="ff.Q" output="fabric.reg_out"/>
<direct name="direct6" input="frac_logic.cout" output="fabric.cout"/> <direct name="direct6" input="frac_logic.cout" output="fabric.cout"/>
@ -454,20 +579,20 @@
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
261e-12 261e-12
263e-12 263e-12
398e-12 398e-12
397e-12 397e-12
--> -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
@ -505,6 +630,18 @@
</mode> </mode>
<!-- 4-LUT mode definition end --> <!-- 4-LUT mode definition end -->
<!-- Define shift register begin --> <!-- Define shift register begin -->
<!-- FIXME: Presence of a disabled mode with .latch site inside sometimes triggers
the VPR bug: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1655
FIXME: There is a bug in the following mode which prevents the
first register input from reaching the regular routing network.
Once both issues are fixed then the mode may be uncommented (and
enabled).
-->
<!--
<mode name="shift_register" disable_packing="true"> <mode name="shift_register" disable_packing="true">
<pb_type name="shift_reg" num_pb="1"> <pb_type name="shift_reg" num_pb="1">
<input name="reg_in" num_pins="1"/> <input name="reg_in" num_pins="1"/>
@ -532,17 +669,18 @@
<direct name="direct4" input="fle.clk" output="shift_reg.clk"/> <direct name="direct4" input="fle.clk" output="shift_reg.clk"/>
</interconnect> </interconnect>
</mode> </mode>
-->
<!-- Define shift register end --> <!-- Define shift register end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use direct connections to reduce the area to the most <!-- We use direct connections to reduce the area to the most
The global local routing is going to compensate the loss in routability The global local routing is going to compensate the loss in routability
--> -->
<!-- FIXME: The implicit port definition results in I0[0] connected to <!-- FIXME: The implicit port definition results in I0[0] connected to
in[2]. Such twisted connection is not expected. in[2]. Such twisted connection is not expected.
I[0] should be connected to in[0] I[0] should be connected to in[0]
--> -->
<complete name="crossbar" input="clb.I fle[7:0].out" output="fle[7:0].in"> <complete name="crossbar" input="clb.I fle[7:0].out" output="fle[7:0].in">
<!-- TODO: Timing should be backannotated from post-PnR results --> <!-- TODO: Timing should be backannotated from post-PnR results -->
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[7:0].clk"> <complete name="clks" input="clb.clk" output="fle[7:0].clk">
@ -550,24 +688,21 @@
<complete name="resets" input="clb.reset" output="fle[7:0].reset"> <complete name="resets" input="clb.reset" output="fle[7:0].reset">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O[3:0]"/> <direct name="clbouts1" input="fle[3:0].out" output="clb.O[3:0]"/>
<direct name="clbouts2" input="fle[7:4].out" output="clb.O[7:4]"/> <direct name="clbouts2" input="fle[7:4].out" output="clb.O[7:4]"/>
<direct name="cout_copy" input="fle[7:7].cout" output="clb.cout_copy"/> <direct name="cout_copy" input="fle[7:7].cout" output="clb.cout_copy"/>
<!-- Shift register chain links --> <!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in"> <direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/> <delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct> </direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out"> <direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
<!--pack_pattern name="chain" in_port="fle[7:7].reg_out" out_port="clb.reg_out"/-->
</direct> </direct>
<direct name="shift_register_link" input="fle[6:0].reg_out" output="fle[7:1].reg_in"> <direct name="shift_register_link" input="fle[6:0].reg_out" output="fle[7:1].reg_in">
<!--pack_pattern name="chain" in_port="fle[6:0].reg_out" out_port="fle[7:1].reg_in"/-->
</direct> </direct>
<!-- Scan chain links --> <!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in"> <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">

190
ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,5 +1,5 @@
<!-- <!--
Low-cost homogeneous FPGA Architecture. Low-cost homogeneous FPGA Architecture: SOFA HD
- Skywater 130 nm technology - Skywater 130 nm technology
- General purpose logic block: - General purpose logic block:
@ -11,6 +11,8 @@
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10 - 80% L = 4, fc_in = 0.15, Fc_out = 0.10
- 100 routing tracks per channel - 100 routing tracks per channel
- Timing is loaded through an external yml file, so that we can model multiple corners
Authors: Xifan Tang Authors: Xifan Tang
--> -->
<architecture> <architecture>
@ -186,21 +188,6 @@
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@ -214,41 +201,32 @@
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- Give uniform delays for all the MUXes driving different length of wires
book area formula. This means the mux transistors are about 5x minimum drive strength. TODO: Can be more accurate once the report timing strategies are elaborated
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large -->
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume <switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed <switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified <switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="0" Cout="0." Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- The wire delay is around 0.1ns in post PnR netlist.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems Create a pair of RC value so that R * C = 0.1ns
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> This is o.k. because other RC values are all zero
-->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
<mux name="L1_mux"/> <mux name="L1_mux"/>
<sb type="pattern">1 1</sb> <sb type="pattern">1 1</sb>
<cb type="pattern">1</cb> <cb type="pattern">1</cb>
</segment> </segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
<mux name="L2_mux"/> <mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb> <sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb> <cb type="pattern">1 1</cb>
</segment> </segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
<mux name="L4_mux"/> <mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
@ -277,18 +255,17 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as The Embedded I/O timing is 0.11ns
the delays to and from registers in the I/O (and generally I/Os are registered FIXME: the timing may include the GPIO timing!!!
today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
@ -296,7 +273,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -306,7 +283,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -386,9 +363,9 @@
<input name="DI" num_pins="1"/> <input name="DI" num_pins="1"/>
<output name="Q" num_pins="1"/> <output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@ -398,22 +375,22 @@
<direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/> <direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/> <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D"> <mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
</mux> </mux>
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D"> <mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/> <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/> <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
</mux> </mux>
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -443,18 +420,10 @@
<input name="in" num_pins="3" port_class="lut_in"/> <input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out"> <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
@ -462,20 +431,22 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/> <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D"> <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
<!-- Consider the delay of the MUX between LUT3 and FF -->
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/> <delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -505,20 +476,11 @@
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
@ -526,20 +488,22 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -561,15 +525,27 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/> <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/> <!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${REGIN_TO_FF0_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
</direct>
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
</direct>
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/> <direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/> <direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/> <!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
</direct>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
<!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
</direct>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/> <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -591,52 +567,36 @@
I[0] should be connected to in[0] I[0] should be connected to in[0]
--> -->
<direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]"> <direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]"> <direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]"> <direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]"> <direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]"> <direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]"> <direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]"> <direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]"> <direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]"> <direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]"> <direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]"> <direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]"> <direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]"> <direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]"> <direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]"> <direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]"> <direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk"> <complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete> </complete>
@ -650,7 +610,7 @@
<!-- Shift register chain links --> <!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in"> <direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/> <delay_constant max="0e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/--> <!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct> </direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out"> <direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
@ -662,7 +622,7 @@
<!-- Scan chain links --> <!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in"> <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/> <delay_constant max="0e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct> </direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out"> <direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct> </direct>

169
ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,5 +1,5 @@
<!-- <!--
Low-cost homogeneous FPGA Architecture. Low-cost homogeneous FPGA Architecture for QLSOFA_HD.
- Skywater 130 nm technology - Skywater 130 nm technology
- General purpose logic block: - General purpose logic block:
@ -204,21 +204,6 @@
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@ -232,41 +217,25 @@
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
book area formula. This means the mux transistors are about 5x minimum drive strength. <switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large <switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="0" Cout="0" Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
<mux name="L1_mux"/> <mux name="L1_mux"/>
<sb type="pattern">1 1</sb> <sb type="pattern">1 1</sb>
<cb type="pattern">1</cb> <cb type="pattern">1</cb>
</segment> </segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
<mux name="L2_mux"/> <mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb> <sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb> <cb type="pattern">1 1</cb>
</segment> </segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
<mux name="L4_mux"/> <mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
@ -296,10 +265,10 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -315,7 +284,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -325,7 +294,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -430,10 +399,10 @@
<input name="reset" num_pins="1"/> <input name="reset" num_pins="1"/>
<output name="Q" num_pins="1"/> <output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
<T_setup value="66e-12" port="ff.reset" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.reset" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@ -446,22 +415,22 @@
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/> <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/> <complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D"> <mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
</mux> </mux>
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D"> <mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/> <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/> <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
</mux> </mux>
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -494,18 +463,10 @@
<input name="in" num_pins="3" port_class="lut_in"/> <input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out"> <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
@ -513,8 +474,8 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/> <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
@ -525,8 +486,8 @@
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/> <delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -556,20 +517,11 @@
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
@ -577,20 +529,21 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -612,15 +565,23 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/> <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="shift_reg.reg_in" out_port="ff[0].D"/>
</direct>
<direct name="direct2" input="ff[0].Q" output="ff[1].D">
<delay_constant max="${FF0_TO_FF1_DELAY}" in_port="ff[0].Q" out_port="ff[1].D"/>
</direct>
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/> <direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/> <direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]">
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/> <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="shift_reg.ff_out[0:0]"/>
</direct>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]">
<delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="shift_reg.ff_out[1:1]"/>
</direct>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/> <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -642,52 +603,36 @@
I[0] should be connected to in[0] I[0] should be connected to in[0]
--> -->
<direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]"> <direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]"> <direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]"> <direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]"> <direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]"> <direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]"> <direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]"> <direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]"> <direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]"> <direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]"> <direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]"> <direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]"> <direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]"> <direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]"> <direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]"> <direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]"> <direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk"> <complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete> </complete>
@ -703,7 +648,7 @@
<!-- Shift register chain links --> <!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in"> <direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/> <delay_constant max="0" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/--> <!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct> </direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out"> <direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
@ -715,7 +660,7 @@
<!-- Scan chain links --> <!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in"> <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/> <delay_constant max="0" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct> </direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out"> <direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct> </direct>
@ -724,7 +669,7 @@
<!-- Carry chain links --> <!-- Carry chain links -->
<direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin"> <direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/> <delay_constant max="0" in_port="clb.cin" out_port="fle[0:0].cin"/>
</direct> </direct>
<direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout"> <direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout">
</direct> </direct>

6
DOC/requirements.txt
View File

@ -9,6 +9,12 @@
sphinxcontrib-bibtex<2.0.0 sphinxcontrib-bibtex<2.0.0
sphinxcontrib-tikz sphinxcontrib-tikz
# Package required to embed youtube video
sphinxcontrib-yt
# Package required to convert SVG for latex building
sphinxcontrib-svg2pdfconverter
#Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1 #Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1
#See: #See:
# * https://github.com/sphinx-doc/sphinx/issues/3951 # * https://github.com/sphinx-doc/sphinx/issues/3951

402
DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fle_arch_timing.svg Normal file
View File

@ -0,0 +1,402 @@
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DOC/source/datasheet/qlsofa_hd/index.rst
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@ -14,3 +14,5 @@ QLSOFA HD
qlsofa_hd_clb_arch qlsofa_hd_clb_arch
qlsofa_hd_circuit_design qlsofa_hd_circuit_design
qlsofa_hd_timing

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@ -8,7 +8,7 @@ Architecture
Floorplan Floorplan
^^^^^^^^^ ^^^^^^^^^
QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA. QLSOFA HD FPGA share the same floorplan as SOFA HD FPGA.
See details at :ref:`sofa_hd_fpga_arch_floorplan`. See details at :ref:`sofa_hd_fpga_arch_floorplan`.
Tiles Tiles
@ -46,6 +46,32 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
| | | cells. | | | | cells. |
+------+----------+----------------------------------------------+ +------+----------+----------------------------------------------+
.. _qlsofa_hd_fpga_arch_routing_arch:
Routing Architecture
^^^^^^^^^^^^^^^^^^^^
The routing architecture shares the same principle as the SOFA HD routing architecture (See details in :ref:`sofa_hd_fpga_arch_routing_arch`).
.. note:: Different from SOFA HD, each routing channel consists of 60 routing tracks. See details in :numref:`table_qlsofa_hd_fpga_arch_routing_track_distribution`.
.. _table_qlsofa_hd_fpga_arch_routing_track_distribution:
.. table:: Routing track distribution of QLSOFA HD FPGA
+------------+------------------------------+
| Track type | Number of tracks per channel |
+============+==============================+
| Length-1 | 6 (10%) |
+------------+------------------------------+
| Length-2 | 6 (10%) |
+------------+------------------------------+
| Length-4 | 48 (80%) |
+------------+------------------------------+
| Total | 60 |
+------------+------------------------------+
.. _qlsofa_hd_fpga_arch_scan_chain: .. _qlsofa_hd_fpga_arch_scan_chain:
Scan-chain Scan-chain

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@ -0,0 +1,100 @@
.. _qlsofa_hd_timing:
Timing Annotation
-----------------
.. _qlsofa_hd_timing_clb:
Configurable Logic Block
^^^^^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_qlsofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.
.. _fig_qlsofa_hd_fle_arch_timing:
.. figure:: ./figures/qlsofa_hd_fle_arch_timing.svg
:width: 80%
:alt: Schematic of a logic element used in QLSOFA HD FPGA
Schematic of a logic element used in QLSOFA HD FPGA
.. _table_qlsofa_hd_fle_arch_timing:
.. table:: Path delays of logic element in the QLSOFA HD FPGA
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] | 0.85 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] | 0.57 |
+-------------------------+------------------------------+
| in2 -> B | 0.60 |
+-------------------------+------------------------------+
| B -> LUT3_out[0] | 0.32 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] | 0.90 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] | 0.62 |
+-------------------------+------------------------------+
| B -> LUT3_out[1] | 0.33 |
+-------------------------+------------------------------+
| in0 -> LUT4_out | 1.17 |
+-------------------------+------------------------------+
| in1 -> LUT4_out | 0.89 |
+-------------------------+------------------------------+
| in2 -> LUT4_out | 1.21 |
+-------------------------+------------------------------+
| in3 -> LUT4_out | 0.79 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
+-------------------------+------------------------------+
| LUT4_out[0] -> A | 0.58 |
+-------------------------+------------------------------+
| A -> out[0] | 0.88 |
+-------------------------+------------------------------+
| A -> FF[0] | 0.56 |
+-------------------------+------------------------------+
| FF[0] -> out[0] | 0.88 |
+-------------------------+------------------------------+
| LUT3_out[1] -> out[1] | 0.89 |
+-------------------------+------------------------------+
| LUT3_out[1] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
| FF[1] -> out[1] | 0.89 |
+-------------------------+------------------------------+
| regin -> FF[0] | 0.58 |
+-------------------------+------------------------------+
| FF[0] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
.. _qlsofa_hd_timing_io:
I/O Block
^^^^^^^^^
The path delays of I/O blocks in QLSOFA HD FPGA is same as the SOFA HD FPGA. See details in :ref:`sofa_hd_timing_io`.
.. _qlsofa_hd_timing_routing:
Routing Architecture
^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_qlsofa_hd_routing_arch_timing`.
.. _table_qlsofa_hd_routing_arch_timing:
.. table:: Path delays of routing blocks in the QLSOFA HD FPGA
+---------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+===========================+==============================+
| A -> B | 1.44 |
+---------------------------+------------------------------+
| A -> C | 1.44 |
+---------------------------+------------------------------+
| A -> D | 1.44 |
+---------------------------+------------------------------+
| B -> E | 1.38 |
+---------------------------+------------------------------+

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@ -14,3 +14,5 @@ SOFA CHD
sofa_chd_clb_arch sofa_chd_clb_arch
sofa_chd_circuit_design sofa_chd_circuit_design
sofa_chd_timing

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.. _sofa_chd_timing:
Timing Annotation
-----------------
.. _sofa_chd_timing_clb:
Configurable Logic Block
^^^^^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_sofa_chd_fle_arch_timing` are listed in :numref:`table_sofa_chd_fle_arch_timing`.
.. _fig_sofa_chd_fle_arch_timing:
.. figure:: ./figures/sofa_chd_fle_arch_timing.svg
:width: 80%
:alt: Schematic of a logic element used in SOFA CHD FPGA
Schematic of a logic element used in SOFA CHD FPGA
.. _table_sofa_chd_fle_arch_timing:
.. table:: Path delays of logic element in the SOFA CHD FPGA
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] | 0.85 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] | 0.57 |
+-------------------------+------------------------------+
| in2 -> B | 0.60 |
+-------------------------+------------------------------+
| B -> LUT3_out[0] | 0.32 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] | 0.90 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] | 0.62 |
+-------------------------+------------------------------+
| B -> LUT3_out[1] | 0.33 |
+-------------------------+------------------------------+
| in0 -> LUT4_out | 1.17 |
+-------------------------+------------------------------+
| in1 -> LUT4_out | 0.89 |
+-------------------------+------------------------------+
| in2 -> LUT4_out | 1.21 |
+-------------------------+------------------------------+
| in3 -> LUT4_out | 0.79 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
+-------------------------+------------------------------+
| LUT4_out[0] -> A | 0.58 |
+-------------------------+------------------------------+
| A -> out[0] | 0.88 |
+-------------------------+------------------------------+
| A -> FF[0] | 0.56 |
+-------------------------+------------------------------+
| FF[0] -> out[0] | 0.88 |
+-------------------------+------------------------------+
| LUT3_out[1] -> out[1] | 0.89 |
+-------------------------+------------------------------+
| LUT3_out[1] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
| FF[1] -> out[1] | 0.89 |
+-------------------------+------------------------------+
| regin -> FF[0] | 0.58 |
+-------------------------+------------------------------+
| FF[0] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
.. _sofa_chd_timing_io:
I/O Block
^^^^^^^^^
The path delays of I/O blocks in SOFA CHD FPGA is same as the SOFA HD FPGA. See details in :ref:`sofa_hd_timing_io`.
.. _sofa_chd_timing_routing:
Routing Architecture
^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_chd_routing_arch_timing`.
.. _table_sofa_chd_routing_arch_timing:
.. table:: Path delays of routing blocks in the SOFA CHD FPGA
+---------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+===========================+==============================+
| A -> B | 1.44 |
+---------------------------+------------------------------+
| A -> C | 1.44 |
+---------------------------+------------------------------+
| A -> D | 1.44 |
+---------------------------+------------------------------+
| B -> E | 1.38 |
+---------------------------+------------------------------+

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@ -14,3 +14,5 @@ SOFA HD
sofa_hd_clb_arch sofa_hd_clb_arch
sofa_hd_circuit_design sofa_hd_circuit_design
sofa_hd_timing

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@ -59,6 +59,47 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
| | | cells. | | | | cells. |
+------+----------+----------------------------------------------+ +------+----------+----------------------------------------------+
.. _sofa_hd_fpga_arch_routing_arch:
Routing Architecture
^^^^^^^^^^^^^^^^^^^^
The routing architecture is based on uni-directional routing tracks, which are interconnected by routing multiplexers.
:numref:`fig_sofa_hd_routing_arch` illustrates the detailed organization of the routing architecture.
.. _fig_sofa_hd_routing_arch:
.. figure:: ./figures/sofa_hd_routing_arch.svg
:width: 80%
:alt: Detailed routing architecture
Detailed routing architecture
The routing architecture consists the following type of routing tracks:
- Length-1 wires (``L1 wires``), which hop over 1 logic block (including I/O block)
- Length-2 wires (``L2 wires``), which hop over 2 logic block (including I/O block)
- Length-4 wires (``L4 wires``), which hop over 4 logic block (including I/O block)
Each tile includes two routing channels, i.e., the X-direction routing channel and the Y-direction routing channel, providing horizental and vertical connections to adjacent tiles.
Each routing channel consists of 40 routing tracks. See details in :numref:`table_sofa_hd_fpga_arch_routing_track_distribution`.
.. _table_sofa_hd_fpga_arch_routing_track_distribution:
.. table:: Routing track distribution of SOFA HD FPGA
+------------+------------------------------+
| Track type | Number of tracks per channel |
+============+==============================+
| Length-1 | 4 (10%) |
+------------+------------------------------+
| Length-2 | 4 (10%) |
+------------+------------------------------+
| Length-4 | 32 (80%) |
+------------+------------------------------+
| Total | 40 |
+------------+------------------------------+
.. _sofa_hd_fpga_arch_scan_chain: .. _sofa_hd_fpga_arch_scan_chain:
Scan-chain Scan-chain

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@ -0,0 +1,110 @@
.. _sofa_hd_timing:
Timing Annotation
-----------------
.. _sofa_hd_timing_clb:
Configurable Logic Block
^^^^^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.
.. _fig_sofa_hd_fle_arch_timing:
.. figure:: ./figures/sofa_hd_fle_arch_timing.svg
:width: 80%
:alt: Schematic of a logic element used in SOFA HD FPGA
Schematic of a logic element used in SOFA HD FPGA
.. _table_sofa_hd_fle_arch_timing:
.. table:: Path delays of logic element in the SOFA HD FPGA
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| in0 -> LUT3_out[0] | 0.85 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[0] | 0.57 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[0] | 0.30 |
+-------------------------+------------------------------+
| in0 -> LUT3_out[1] | 0.86 |
+-------------------------+------------------------------+
| in1 -> LUT3_out[1] | 0.59 |
+-------------------------+------------------------------+
| in2 -> LUT3_out[1] | 0.31 |
+-------------------------+------------------------------+
| in0 -> LUT4_out | 1.14 |
+-------------------------+------------------------------+
| in1 -> LUT4_out | 0.86 |
+-------------------------+------------------------------+
| in2 -> LUT4_out | 0.58 |
+-------------------------+------------------------------+
| in3 -> LUT4_out | 0.51 |
+-------------------------+------------------------------+
| LUT3_out[0] -> A | 0.56 |
+-------------------------+------------------------------+
| LUT4_out[0] -> A | 0.58 |
+-------------------------+------------------------------+
| A -> out[0] | 0.88 |
+-------------------------+------------------------------+
| A -> FF[0] | 0.56 |
+-------------------------+------------------------------+
| FF[0] -> out[0] | 0.88 |
+-------------------------+------------------------------+
| LUT3_out[1] -> out[1] | 0.89 |
+-------------------------+------------------------------+
| LUT3_out[1] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
| FF[1] -> out[1] | 0.89 |
+-------------------------+------------------------------+
| regin -> FF[0] | 0.58 |
+-------------------------+------------------------------+
| FF[0] -> FF[1] | 0.56 |
+-------------------------+------------------------------+
.. _sofa_hd_timing_io:
I/O Block
^^^^^^^^^
The path delays in :numref:`fig_sofa_hd_embedded_io_schematic` are listed in :numref:`table_sofa_hd_io_timing`.
.. _table_sofa_hd_io_timing:
.. table:: Path delays of I/O circuit in the SOFA HD FPGA
+-------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+=========================+==============================+
| SOC_IN -> FPGA_IN | 0.11 |
+-------------------------+------------------------------+
| FPGA_OUT -> SOC_OUT | 0.11 |
+-------------------------+------------------------------+
.. _sofa_hd_timing_routing:
Routing Architecture
^^^^^^^^^^^^^^^^^^^^
The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_hd_routing_arch_timing`.
.. _table_sofa_hd_routing_arch_timing:
.. table:: Path delays of routing blocks in the SOFA HD FPGA
+---------------------------+------------------------------+
| Path / Delay | TT (unit: ns) |
+===========================+==============================+
| A -> B | 1.61 |
+---------------------------+------------------------------+
| A -> C | 1.61 |
+---------------------------+------------------------------+
| A -> D | 1.61 |
+---------------------------+------------------------------+
| B -> E | 1.38 |
+---------------------------+------------------------------+

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@ -0,0 +1,39 @@
.. _hd_fpga_device_gallery:
Chip Gallery
------------
Here lists the images of each HD FPGA chips
SOFA HD
^^^^^^^
SOFA HD is the base design of the SOFA high-density eFPGA IPs
.. figure:: ./figures/sofa_hd_layout.png
:scale: 100%
:alt: Layout view of SOFA HD device in Caravel SoC
Layout view of SOFA HD device in Caravel SoC
QLSOFA HD
^^^^^^^^^
QLSOFA HD is the arithmetic-enhanced design of the SOFA high-density eFPGA IPs
.. figure:: ./figures/qlsofa_hd_layout.png
:scale: 100%
:alt: Layout view of QLSOFA HD device in Caravel SoC
Layout view of QLSOFA HD device in Caravel SoC
SOFA CHD
^^^^^^^^
SOFA CHD is the performance-optimized design of the SOFA high-density eFPGA IPs
.. figure:: ./figures/sofa_chd_layout.png
:scale: 100%
:alt: Layout view of SOFA CHD device in Caravel SoC
Layout view of SOFA CHD device in Caravel SoC

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DOC/source/device/hd_fpga/index.rst
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@ -10,3 +10,5 @@ HD FPGAs
hd_device_comp hd_device_comp
hd_device_dcac hd_device_dcac
hd_device_gallery

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@ -17,4 +17,3 @@ We aims to empower embedded applications with its low-cost design approach but h
:alt: 24-hour FPGA IP development: from PDK to production-ready layout :alt: 24-hour FPGA IP development: from PDK to production-ready layout
24-hour FPGA IP development: from PDK to production-ready layout 24-hour FPGA IP development: from PDK to production-ready layout

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</direct_connection> </direct_connection>
<tile_annotations> <tile_annotations>
<global_port name="clk" is_clock="true" default_val="0"> <global_port name="clk" is_clock="true" default_val="0">
<tile name=="clb" port="clk" x="-1" y="-1"/> <tile name="clb" port="clk" x="-1" y="-1"/>
</global_port> </global_port>
<global_port name="Reset" is_reset="true" default_val="1"> <global_port name="Reset" is_reset="true" default_val="1">
<tile name=="clb" port="reset" x="-1" y="-1"/> <tile name="clb" port="reset" x="-1" y="-1"/>
</global_port> </global_port>
</tile_annotations> </tile_annotations>
<pb_type_annotations> <pb_type_annotations>

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`timescale 1ns/1ps
//-----------------------------------------------------
// Function : QuickLogic physical CCFF
// - intorduce CFGE to gate CCFF output for
// un-wanted toggling during configuration
// - intorduce test data in, SI, for DFM
//
// Note: This cell is built with Standard Cells from HD library
// It is already technology mapped and can be directly used
// for physical design
//-----------------------------------------------------
module QL_CCFF (
input RESET_B,
input SE,
input CFGE,
input D,
input SI,
output Q,
output CFGQN,
output CFGQ,
input CLK
);
sky130_fd_sc_hd__nand2_1 NAND2_CFGQN (
.A(Q),
.B(CFGE),
.X(CFGQN)
);
sky130_fd_sc_hd__inv_1 INV_CFGQN (
.A(CFGQN),
.Y(CFGQ)
);
sky130_fd_sc_hd__sdfrtp_1 SDFRTP (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SI),
.SCE(SE),
.RESET_B(RESET_B)
);
endmodule

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`timescale 1ns/1ps
//-----------------------------------------------------
// Function : An embedded I/O with
// - An I/O isolation signal to set
// the I/O in input mode. This is to avoid
// any unexpected output signals to damage
// circuits outside the FPGA due to configurable
// memories are not properly initialized
// This feature may not be needed if the configurable
// memory cell has a built-in set/reset functionality
// - Internal protection circuitry to ensure
// clean signals at all the SOC I/O ports
// This is to avoid
// - output any random signal
// when the I/O is in input mode, also avoid
// - driven by any random signal
// when the I/O is output mode
//
// Note: This cell is built with Standard Cells from HD library
// It is already technology mapped and can be directly used
// for physical design
//-----------------------------------------------------
module EMBEDDED_IO_HD (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_IO_DIR,
input CFG_DONE
);
wire cfg_done_b;
sky130_fd_sc_hd__inv_1 INV (
.A(CFG_DONE),
.Y(cfg_done_b)
);
sky130_fd_sc_hd__or3_1 OR3 (
.A(FPGA_IO_DIR),
.B(FPGA_OUT),
.C(cfg_done_b),
.X(SOC_OUT)
);
sky130_fd_sc_hd__and2_1 AND2 (
.A(FPGA_IO_DIR),
.B(SOC_IN),
.X(FPGA_IN)
);
endmodule

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`timescale 1ns/1ps
//-----------------------------------------------------
// Function : An embedded I/O with
// - An I/O isolation signal to set
// the I/O in input mode. This is to avoid
// any unexpected output signals to damage
// circuits outside the FPGA due to configurable
// memories are not properly initialized
// This feature may not be needed if the configurable
// memory cell has a built-in set/reset functionality
// - Internal protection circuitry to ensure
// clean signals at all the SOC I/O ports
// This is to avoid
// - output any random signal
// when the I/O is in input mode, also avoid
// - driven by any random signal
// when the I/O is output mode
//
// Note: This cell is built with Standard Cells from HD library
// It is already technology mapped and can be directly used
// for physical design
//-----------------------------------------------------
module IO (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_IO_DIR,
input CFG_DONE,
input IO_ISOL_N
);
wire cfg_done_b;
wire io_isol;
wire f2a_o_gate;
wire f2a_o_int;
sky130_fd_sc_hd__inv_1 INV_CFG_DONE (
.A(CFG_DONE),
.Y(cfg_done_b)
);
sky130_fd_sc_hd__inv_1 INV_ISOL_N (
.A(IO_ISOL_N),
.Y(io_isol)
);
// output path
sky130_fd_sc_hd__nor2_1 NOR2 (
.A(FPGA_IO_DIR),
.B(cfg_done_b),
.Y(f2a_o_gate)
);
sky130_fd_sc_hd__nand2_1 NAND2 (
.A(FPGA_OUT),
.B(f2a_o_gate),
.Y(f2a_o_int)
);
sky130_fd_sc_hd__einvn_4 EINVN_OUT (
.A(f2a_o_int),
.TE_B(io_isol),
.Z(SOC_OUT)
);
// input path
sky130_fd_sc_hd__and3_1 AND3 (
.A(SOC_IN),
.B(FPGA_IO_DIR),
.C(IO_ISOL_N),
.X(FPGA_IN)
);
endmodule

20
README.md
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@ -4,7 +4,20 @@
## Introduction ## Introduction
SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework.
This repository provide the following support for the eFPGA IPs
- **Architecture description file** : Users can inspect architecture details and try architecture evalution using the [VTR project](https://github.com/verilog-to-routing/vtr-verilog-to-routing) and the [OpenFPGA project](https://github.com/lnis-uofu/OpenFPGA).
- **Fabrication-ready GDSII layouts**: Users can integrate to their chip designs.
- **Post-layout Verilog Netlists**: Users can run HDL simulations on the eFPGA IPs to validate their applications
- **Benchmark suites**: An example benchmarking suite with which users can run quick examples on the eFPGA IPs
- **Documentation**: Datasheets for each eFPGA IPs downto circuit-level details
<p>
<img src="./DOC/source/device/hd_fpga/figures/sofa_hd_layout.png" width="200">
<img src="./DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png" width="200">
<img src="./DOC/source/device/hd_fpga/figures/sofa_chd_layout.png" width="200">
</p>
## Quick Start ## Quick Start
@ -22,6 +35,11 @@ python3 SCRIPT/repo_setup.py --openfpga_root_path ${OPENFPGA_PROJECT_DIRECTORY}
Otherwise, you should provide full path using the option _--openfpga\_root\_path_ Otherwise, you should provide full path using the option _--openfpga\_root\_path_
## Chip Gallery
You can find a chip gallery in the online documentation.
## Directory Organization ## Directory Organization
* Keep this folder clean and organized as follows * Keep this folder clean and organized as follows

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# This script is designed to generate bitstream
# with a fixed device layout, which can be used for bitstream loaders
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup #--verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
# - Enabled frame view creation to save runtime and memory
# Note that this is turned on when bitstream generation
# is the ONLY purpose of the flow!!!
build_fabric --compress_routing --duplicate_grid_pin --frame_view --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file arch_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.txt --format plain_text
write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Finish and exit OpenFPGA
exit

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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=40
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
[ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

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@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

53
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_bitstream/config/task_template.conf Normal file
View File

@ -0,0 +1,53 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
[ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

53
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_bitstream/config/task_template.conf Normal file
View File

@ -0,0 +1,53 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
[ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
[SYNTHESIS_PARAM]
bench0_top = and2
bench1_top = and2_latch
bench2_top = bin2bcd
bench3_top = counter
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
#bench5_top = rs_decoder_top
bench6_top = top_module
bench7_top = and2_or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

4
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf
View File

@ -23,6 +23,8 @@ openfpga_vpr_device_layout=32x32
openfpga_vpr_route_chan_width=60 openfpga_vpr_route_chan_width=60
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml
# Yosys parameters
yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
[ARCHITECTURES] [ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@ -32,7 +34,7 @@ bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/io_reg/io_reg.v
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
bench0_top = io_reg bench0_top = io_reg
bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test= #end_flow_with_test=

44
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf
View File

@ -24,6 +24,8 @@ openfpga_vpr_route_chan_width=60
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/prepnr openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/prepnr
openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/SRC/fabric_netlists.v openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/SRC/fabric_netlists.v
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml
# Yosys parameters
yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
[ARCHITECTURES] [ARCHITECTURES]
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@ -38,7 +40,8 @@ bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
bench8=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cavlc_top/rtl/*.v # Skip cavlc benchmark because current yosys script failed in DFF mapping; Problem should be solved once the yosys script is updated
#bench8=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cavlc_top/rtl/*.v
#bench9=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cf_fft_256_8/rtl/*.v #bench9=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/cf_fft_256_8/rtl/*.v
bench10=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter120bitx5/rtl/*.v bench10=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter120bitx5/rtl/*.v
bench11=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter_16bit/rtl/*.v bench11=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter_16bit/rtl/*.v
@ -47,7 +50,8 @@ bench12=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/dct_mac/rtl/*.v
bench14=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/diffeq_f_systemC/rtl/*.v bench14=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/diffeq_f_systemC/rtl/*.v
#bench15=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/i2c_master_top/rtl/*.v #bench15=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/i2c_master_top/rtl/*.v
#bench16=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/iir/rtl/*.v #bench16=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/iir/rtl/*.v
bench17=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/jpeg_qnr/rtl/*.v # Skip jpeg_qnr benchmark because current yosys script failed in DFF mapping; Problem should be solved once the yosys script is updated
#bench17=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/jpeg_qnr/rtl/*.v
bench18=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/multi_enc_decx2x4/rtl/*.v bench18=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/multi_enc_decx2x4/rtl/*.v
#bench19=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/sdc_controller/rtl/*.v #bench19=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/sdc_controller/rtl/*.v
bench20=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/sha256/rtl/*.v bench20=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/sha256/rtl/*.v
@ -56,47 +60,47 @@ bench22=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/io_tc1/rtl/*.v
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
bench0_top = and2 bench0_top = and2
bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench1_top = and2_latch bench1_top = and2_latch
bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench2_top = bin2bcd bench2_top = bin2bcd
bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench3_top = counter bench3_top = counter
bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench4_top = routing_test bench4_top = routing_test
bench4_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench4_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
# RS decoder needs 1.5k LUT4, exceeding device capacity # RS decoder needs 1.5k LUT4, exceeding device capacity
bench5_top = rs_decoder_top bench5_top = rs_decoder_top
bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench6_top = top_module bench6_top = top_module
bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench7_top = and2_or2 bench7_top = and2_or2
bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench8_top = cavlc_top bench8_top = cavlc_top
bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
#bench9_top = cf_fft_256_8 #bench9_top = cf_fft_256_8
bench10_top = counter120bitx5 bench10_top = counter120bitx5
bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench11_top = top bench11_top = top
bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench12_top = dct_mac bench12_top = dct_mac
bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
#bench13_top = des_perf #bench13_top = des_perf
bench14_top = diffeq_f_systemC bench14_top = diffeq_f_systemC
bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
#bench15_top = i2c_master_top #bench15_top = i2c_master_top
#bench16_top = iir #bench16_top = iir
bench17_top = jpeg_qnr bench17_top = jpeg_qnr
bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench18_top = multi_enc_decx2x4 bench18_top = multi_enc_decx2x4
bench18_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys #bench18_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
#bench19_top = sdc_controller #bench19_top = sdc_controller
bench20_top = sha256 bench20_top = sha256
bench20_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench20_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench21_top = unsigned_mult_80 bench21_top = unsigned_mult_80
bench21_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench21_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench22_top = io_tc1 bench22_top = io_tc1
bench22_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench22_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test= #end_flow_with_test=

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SNPS_PT/SCRIPT/report_timing_cb.tcl Normal file
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@ -0,0 +1,89 @@
#####################################################################
# A template script to report timing for Connection Blocks from post-PnR results
# using Synopsys PrimeTime
#####################################################################
#
##################################
# Define environment variables
#
set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
if {"SOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
}
set TIMING_REPORT_HOME "../TIMING_REPORTS/";
# Enable preprocessing in Verilog parser
set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths true
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
##################################
# Sweep all the CB design
set DESIGN_NAMES {"cbx_1__0_" "cbx_1__1_" "cbx_1__2_" "cby_0__1_" "cby_1__1_" "cby_2__1_"};
foreach DESIGN_NAME ${DESIGN_NAMES} {
##################################
# Ensure a clean start
remove_design -all
remove_lib -all
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
##################################
# Read post-PnR netlists
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
link_design ${DESIGN_NAME}
#########################################
# Setup constraints to break combinational loops
#source ${SDC_HOME}/disable_configurable_memory_outputs.sdc
set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
#########################################
# Setup constraints for clocks
#source ${SDC_HOME}/global_ports.sdc
#########################################
# Setup constraints for paths
# Connection block name
set CB_CHAN_NAME "chan*";
set CB_PIN_NAME "*grid_pin*";
set_max_delay -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} 6.02e-11
set_max_delay -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} 6.02e-11
##################################
# Read post-PnR parasitics
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
##################################
# Report timing of Connect block
report_timing -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
report_timing -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
}
##################################
# Finish and quit
# Comment it out if you want to debug
exit

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@ -0,0 +1,129 @@
#####################################################################
# A template script to report timing for A CLB from post-PnR results
# using Synopsys PrimeTime
#####################################################################
##################################
# Define environment variables
#
set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
if {"SOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
}
set TIMING_REPORT_HOME "../TIMING_REPORTS/";
# Enable preprocessing in Verilog parser
set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths tr
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
##################################
# Ensure a clean start
remove_design -all
remove_lib -all
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
##################################
# Read post-PnR netlists
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
# Top-level module name
set DESIGN_NAME "grid_clb";
link_design ${DESIGN_NAME}
#########################################
# Setup constraints to break combinational loops
if {${DEVICE_NAME} == "SOFA_HD"} {
set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q
} else {
# QLSOFA and SOFA CHD use a LUT with carry logic, the memory is deeper in hierarchy
# Also QLSOFA and SOFA CHD use a different FF cell as configuration memory
set_disable_timing */*/*/*/*mem*/sky*_fd_sc_hd__dfrtp_*_*_/Q
set_disable_timing */*/*/*/*/*mem*/sky*_fd_sc_hd__dfrtp_*_*_/Q
#Disable cin/cout paths
set_disable_timing logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/frac_logic_cin
set_disable_timing logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/frac_logic_cout
}
#
##########################################
## Setup constraints for clocks
##########################################
## Setup constraints for paths
##################################
# Read post-PnR parasitics
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
##################################
# Report timing of Connect block
# LUT4 output timing
set LUT_INPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in"
set LUT4_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out"
# Walk through all the input pin and output pin paths
for {set ipin 0} {$ipin < 4} {incr ipin} {
if {0 == $ipin} {
report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT4_OUTPUT_PORT_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt
} else {
report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT4_OUTPUT_PORT_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt
}
}
# LUT3 output timing
set LUT3_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out"
# Walk through all the input pin and output pin paths
for {set ipin 0} {$ipin < 3} {incr ipin} {
for {set opin 0} {$opin < 2} {incr opin} {
if {0 == $ipin && 0 == $opin} {
report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT3_OUTPUT_PORT_NAME}[$opin] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt
} else {
report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT3_OUTPUT_PORT_NAME}[$opin] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt
}
}
}
# Output selector timing
set FRAC_LOGIC_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]"
set FF_PATH "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff"
set FLE_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out"
report_timing -from ${FF_PATH}_0/ff_Q[0] -to ${FLE_OUTPUT_PORT_NAME}[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
report_timing -from ${FRAC_LOGIC_OUTPUT_PORT_NAME}[0] -to ${FLE_OUTPUT_PORT_NAME}[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
report_timing -from ${FF_PATH}_1/ff_Q[0] -to ${FLE_OUTPUT_PORT_NAME}[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
report_timing -from ${FRAC_LOGIC_OUTPUT_PORT_NAME}[1] -to ${FLE_OUTPUT_PORT_NAME}[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
# LUT output to FF input timing
report_timing -from ${LUT4_OUTPUT_PORT_NAME} -to ${FF_PATH}_0/ff_D[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
report_timing -from ${LUT3_OUTPUT_PORT_NAME} -to ${FF_PATH}_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
report_timing -from ${LUT3_OUTPUT_PORT_NAME} -to ${FF_PATH}_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
# TODO: Carry logic timing
##################################
# Finish and quit
# Comment it out if you want to debug
exit

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@ -0,0 +1,81 @@
#####################################################################
# A template script to report timing for A CLB from post-PnR results
# using Synopsys PrimeTime
#####################################################################
##################################
# Define environment variables
#
set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
if {"SOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
}
set TIMING_REPORT_HOME "../TIMING_REPORTS/";
# Enable preprocessing in Verilog parser
set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths tr
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
##################################
# Ensure a clean start
remove_design -all
remove_lib -all
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
##################################
# Read post-PnR netlists
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
# Top-level module name
# May sweep for all the io modules
set DESIGN_NAME "cbx_1__0__logical_tile_io_mode_physical__iopad_0";
link_design ${DESIGN_NAME}
#########################################
# Setup constraints to break combinational loops
set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q
#
##########################################
## Setup constraints for clocks
##########################################
## Setup constraints for paths
##################################
# Read post-PnR parasitics
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
##################################
# Report timing of Connect block
# Inpad -> FPGA timing
report_timing -from gfpga_pad_EMBEDDED_IO_HD_SOC_IN -to iopad_inpad > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
report_timing -from iopad_outpad -to gfpga_pad_EMBEDDED_IO_HD_SOC_OUT >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
##################################
# Finish and quit
# Comment it out if you want to debug
exit

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#####################################################################
# A template script to report timing for Connection Blocks from post-PnR results
# using Synopsys PrimeTime
#####################################################################
##################################
# Define environment variables
set DEVICE_NAME "SOFA_HD"
#set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
if {"SOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
}
set TIMING_REPORT_HOME "../TIMING_REPORTS/";
# Enable preprocessing in Verilog parser
set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths tr
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
##################################
# Sweep all the SB designs
set DESIGN_NAMES {"sb_1__1_" "sb_0__0_" "sb_0__2_" "sb_0__1_" "sb_2__0_" "sb_2__2_" "sb_2__1_" "sb_1__0_" "sb_1__2_"};
foreach DESIGN_NAME ${DESIGN_NAMES} {
##################################
# Ensure a clean start
remove_design -all
remove_lib -all
##################################
# Read timing libraries
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
##################################
# Read post-PnR netlists
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
link_design ${DESIGN_NAME}
#########################################
# Setup constraints to break combinational loops
set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
#
##########################################
## Setup constraints for clocks
##########################################
## Setup constraints for paths
## Switch block name
set SB_CHAN_NAME "chan*";
set SB_PIN_NAME "*grid_pin*";
set_max_delay -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} 2.272500113e-12
set_max_delay -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} 7.247000222e-11
##################################
# Read post-PnR parasitics
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
##################################
# Report timing of Connect block
report_timing -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
report_timing -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
}
##################################
# Finish and quit
# Comment it out if you want to debug
exit