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[Script] Update report timing script for connection blocks so that timing reports are generated in 1 shot

This commit is contained in:
tangxifan 2021-04-01 17:53:53 -06:00
parent 062120ffd9
commit 7b49fa0684
1 changed files with 56 additions and 51 deletions
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95
SNPS_PT/SCRIPT/report_timing_cb.tcl
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@ -2,72 +2,77 @@
# A template script to report timing for Connection Blocks from post-PnR results # A template script to report timing for Connection Blocks from post-PnR results
# using Synopsys PrimeTime # using Synopsys PrimeTime
##################################################################### #####################################################################
#
##################################
# Ensure a clean start
remove_design -all
remove_lib -all
################################## ##################################
# Define environment variables # Define environment variables
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; #set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
set DEVICE_NAME "SOFA" #set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
#set DEVICE_NAME "SOFA_HD"
set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"
set TIMING_REPORT_HOME "../TIMING_REPORTS/"; set TIMING_REPORT_HOME "../TIMING_REPORTS/";
# Enable preprocessing in Verilog parser # Enable preprocessing in Verilog parser
set_app_var svr_enable_vpp true set_app_var svr_enable_vpp true
# Enable reporting ALL the timing paths even those are NOT constrained # Enable reporting ALL the timing paths even those are NOT constrained
set_app_var timing_report_unconstrained_paths tr set_app_var timing_report_unconstrained_paths true
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm" set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
################################## ##################################
# Read timing libraries # Sweep all the CB design
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" set DESIGN_NAMES {"cbx_1__0_" "cbx_1__1_" "cbx_1__2_" "cby_0__1_" "cby_1__1_" "cby_2__1_"};
foreach DESIGN_NAME ${DESIGN_NAMES} {
################################## ##################################
# Read post-PnR netlists # Ensure a clean start
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} remove_design -all
# Top-level module name remove_lib -all
#set DESIGN_NAME "cbx_1__0_";
#set DESIGN_NAME "cbx_1__1_";
#set DESIGN_NAME "cbx_1__12_";
#set DESIGN_NAME "cby_0__1_";
#set DESIGN_NAME "cby_1__1_";
set DESIGN_NAME "cby_12__1_";
link_design ${DESIGN_NAME}
######################################### ##################################
# Setup constraints to break combinational loops # Read timing libraries
#source ${SDC_HOME}/disable_configurable_memory_outputs.sdc read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
######################################### ##################################
# Setup constraints for clocks # Read post-PnR netlists
#source ${SDC_HOME}/global_ports.sdc read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
link_design ${DESIGN_NAME}
######################################### #########################################
# Setup constraints for paths # Setup constraints to break combinational loops
# Connection block name #source ${SDC_HOME}/disable_configurable_memory_outputs.sdc
set CB_CHAN_NAME "chan*"; set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
set CB_PIN_NAME "*grid_pin*";
set_max_delay -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} 6.02e-11
set_max_delay -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} 6.02e-11
################################## #########################################
# Read post-PnR parasitics # Setup constraints for clocks
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef #source ${SDC_HOME}/global_ports.sdc
################################## #########################################
# Report timing of Connect block # Setup constraints for paths
report_timing -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt # Connection block name
report_timing -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt set CB_CHAN_NAME "chan*";
set CB_PIN_NAME "*grid_pin*";
set_max_delay -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} 6.02e-11
set_max_delay -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} 6.02e-11
##################################
# Read post-PnR parasitics
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
##################################
# Report timing of Connect block
report_timing -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
report_timing -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
}
################################## ##################################
# Finish and quit # Finish and quit