diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml new file mode 100644 index 0000000..4f47d51 --- /dev/null +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -0,0 +1,684 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_top.outpad io_top.inpad + + + + + + + + + + + + io_right.outpad io_right.inpad + + + + + + + + + + + + io_bottom.outpad io_bottom.inpad + + + + + + + + + + + + io_left.outpad io_left.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk clb.reset + clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i + clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i + clb.reg_out clb.sc_out clb.cout + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 + 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ${LUT3_DELAY} + ${LUT3_DELAY} + ${LUT3_DELAY} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/BENCHMARK/vexriscv/vexriscv_large.v b/BENCHMARK/vexriscv/vexriscv_large.v new file mode 100644 index 0000000..e8ee2b7 --- /dev/null +++ b/BENCHMARK/vexriscv/vexriscv_large.v @@ -0,0 +1,7460 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : 36b3cd918896c94c4e8a224d97c559ab6dbf3ec9 + + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define EnvCtrlEnum_defaultEncoding_type [0:0] +`define EnvCtrlEnum_defaultEncoding_NONE 1'b0 +`define EnvCtrlEnum_defaultEncoding_XRET 1'b1 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define MmuPlugin_shared_State_defaultEncoding_type [2:0] +`define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000 +`define MmuPlugin_shared_State_defaultEncoding_L1_CMD 3'b001 +`define MmuPlugin_shared_State_defaultEncoding_L1_RSP 3'b010 +`define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011 +`define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100 + + +module VexRiscv ( + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output dBus_cmd_payload_uncached, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [3:0] dBus_cmd_payload_mask, + output [2:0] dBus_cmd_payload_length, + output dBus_cmd_payload_last, + input dBus_rsp_valid, + input dBus_rsp_payload_last, + input [31:0] dBus_rsp_payload_data, + input dBus_rsp_payload_error, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBus_cmd_valid, + input iBus_cmd_ready, + output reg [31:0] iBus_cmd_payload_address, + output [2:0] iBus_cmd_payload_size, + input iBus_rsp_valid, + input [31:0] iBus_rsp_payload_data, + input iBus_rsp_payload_error, + input clk, + input reset, + input debugReset +); + wire _zz_184; + wire _zz_185; + wire _zz_186; + wire _zz_187; + wire _zz_188; + wire _zz_189; + wire _zz_190; + wire _zz_191; + reg _zz_192; + reg _zz_193; + reg [31:0] _zz_194; + reg _zz_195; + reg [31:0] _zz_196; + reg [1:0] _zz_197; + reg _zz_198; + wire [31:0] _zz_199; + reg _zz_200; + reg _zz_201; + wire _zz_202; + wire [31:0] _zz_203; + wire _zz_204; + wire _zz_205; + wire _zz_206; + wire _zz_207; + wire _zz_208; + wire _zz_209; + wire _zz_210; + wire _zz_211; + wire [3:0] _zz_212; + wire _zz_213; + reg [1:0] _zz_214; + reg [31:0] _zz_215; + reg [31:0] _zz_216; + reg [31:0] _zz_217; + reg _zz_218; + reg _zz_219; + reg _zz_220; + reg [9:0] _zz_221; + reg [9:0] _zz_222; + reg [9:0] _zz_223; + reg [9:0] _zz_224; + reg _zz_225; + reg _zz_226; + reg _zz_227; + reg _zz_228; + reg _zz_229; + reg _zz_230; + reg _zz_231; + reg [9:0] _zz_232; + reg [9:0] _zz_233; + reg [9:0] _zz_234; + reg [9:0] _zz_235; + reg _zz_236; + reg _zz_237; + reg _zz_238; + reg _zz_239; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire _zz_245; + wire _zz_246; + wire _zz_247; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire _zz_254; + wire _zz_255; + wire [1:0] _zz_256; + wire _zz_257; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire _zz_261; + wire _zz_262; + wire _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire [1:0] _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire [5:0] _zz_273; + wire _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire _zz_279; + wire _zz_280; + wire _zz_281; + wire _zz_282; + wire _zz_283; + wire _zz_284; + wire _zz_285; + wire _zz_286; + wire _zz_287; + wire _zz_288; + wire [1:0] _zz_289; + wire [1:0] _zz_290; + wire _zz_291; + wire [51:0] _zz_292; + wire [51:0] _zz_293; + wire [51:0] _zz_294; + wire [32:0] _zz_295; + wire [51:0] _zz_296; + wire [49:0] _zz_297; + wire [51:0] _zz_298; + wire [49:0] _zz_299; + wire [51:0] _zz_300; + wire [32:0] _zz_301; + wire [31:0] _zz_302; + wire [32:0] _zz_303; + wire [0:0] _zz_304; + wire [0:0] _zz_305; + wire [0:0] _zz_306; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire [0:0] _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [0:0] _zz_317; + wire [0:0] _zz_318; + wire [0:0] _zz_319; + wire [0:0] _zz_320; + wire [0:0] _zz_321; + wire [0:0] _zz_322; + wire [3:0] _zz_323; + wire [2:0] _zz_324; + wire [31:0] _zz_325; + wire [1:0] _zz_326; + wire [1:0] _zz_327; + wire [1:0] _zz_328; + wire [1:0] _zz_329; + wire [9:0] _zz_330; + wire [29:0] _zz_331; + wire [9:0] _zz_332; + wire [1:0] _zz_333; + wire [1:0] _zz_334; + wire [1:0] _zz_335; + wire [19:0] _zz_336; + wire [11:0] _zz_337; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire [19:0] _zz_340; + wire [11:0] _zz_341; + wire [2:0] _zz_342; + wire [2:0] _zz_343; + wire [0:0] _zz_344; + wire [1:0] _zz_345; + wire [0:0] _zz_346; + wire [2:0] _zz_347; + wire [0:0] _zz_348; + wire [0:0] _zz_349; + wire [0:0] _zz_350; + wire [0:0] _zz_351; + wire [0:0] _zz_352; + wire [0:0] _zz_353; + wire [0:0] _zz_354; + wire [0:0] _zz_355; + wire [1:0] _zz_356; + wire [0:0] _zz_357; + wire [2:0] _zz_358; + wire [4:0] _zz_359; + wire [11:0] _zz_360; + wire [11:0] _zz_361; + wire [31:0] _zz_362; + wire [31:0] _zz_363; + wire [31:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; + wire [31:0] _zz_367; + wire [31:0] _zz_368; + wire [65:0] _zz_369; + wire [65:0] _zz_370; + wire [31:0] _zz_371; + wire [31:0] _zz_372; + wire [0:0] _zz_373; + wire [5:0] _zz_374; + wire [32:0] _zz_375; + wire [31:0] _zz_376; + wire [31:0] _zz_377; + wire [32:0] _zz_378; + wire [32:0] _zz_379; + wire [32:0] _zz_380; + wire [32:0] _zz_381; + wire [0:0] _zz_382; + wire [32:0] _zz_383; + wire [0:0] _zz_384; + wire [32:0] _zz_385; + wire [0:0] _zz_386; + wire [31:0] _zz_387; + wire [1:0] _zz_388; + wire [1:0] _zz_389; + wire [11:0] _zz_390; + wire [19:0] _zz_391; + wire [11:0] _zz_392; + wire [31:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire [11:0] _zz_396; + wire [19:0] _zz_397; + wire [11:0] _zz_398; + wire [2:0] _zz_399; + wire [0:0] _zz_400; + wire [0:0] _zz_401; + wire [0:0] _zz_402; + wire [0:0] _zz_403; + wire [0:0] _zz_404; + wire [0:0] _zz_405; + wire [0:0] _zz_406; + wire [0:0] _zz_407; + wire [0:0] _zz_408; + wire [0:0] _zz_409; + wire [0:0] _zz_410; + wire [0:0] _zz_411; + wire [0:0] _zz_412; + wire [1:0] _zz_413; + wire _zz_414; + wire _zz_415; + wire [1:0] _zz_416; + wire [31:0] _zz_417; + wire [31:0] _zz_418; + wire [31:0] _zz_419; + wire _zz_420; + wire [0:0] _zz_421; + wire [13:0] _zz_422; + wire [31:0] _zz_423; + wire [31:0] _zz_424; + wire [31:0] _zz_425; + wire _zz_426; + wire [0:0] _zz_427; + wire [7:0] _zz_428; + wire [31:0] _zz_429; + wire [31:0] _zz_430; + wire [31:0] _zz_431; + wire _zz_432; + wire [0:0] _zz_433; + wire [1:0] _zz_434; + wire _zz_435; + wire _zz_436; + wire _zz_437; + wire [31:0] _zz_438; + wire [31:0] _zz_439; + wire [31:0] _zz_440; + wire [31:0] _zz_441; + wire _zz_442; + wire [0:0] _zz_443; + wire [0:0] _zz_444; + wire _zz_445; + wire [0:0] _zz_446; + wire [26:0] _zz_447; + wire [31:0] _zz_448; + wire [31:0] _zz_449; + wire [31:0] _zz_450; + wire [31:0] _zz_451; + wire [0:0] _zz_452; + wire [0:0] _zz_453; + wire _zz_454; + wire [0:0] _zz_455; + wire [22:0] _zz_456; + wire [31:0] _zz_457; + wire _zz_458; + wire _zz_459; + wire [0:0] _zz_460; + wire [1:0] _zz_461; + wire [0:0] _zz_462; + wire [0:0] _zz_463; + wire _zz_464; + wire [0:0] _zz_465; + wire [18:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire [31:0] _zz_471; + wire [31:0] _zz_472; + wire [31:0] _zz_473; + wire [31:0] _zz_474; + wire _zz_475; + wire [1:0] _zz_476; + wire [1:0] _zz_477; + wire _zz_478; + wire [0:0] _zz_479; + wire [15:0] _zz_480; + wire [31:0] _zz_481; + wire [31:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire [31:0] _zz_485; + wire [31:0] _zz_486; + wire _zz_487; + wire [1:0] _zz_488; + wire [1:0] _zz_489; + wire _zz_490; + wire [0:0] _zz_491; + wire [12:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire [31:0] _zz_496; + wire _zz_497; + wire [0:0] _zz_498; + wire [0:0] _zz_499; + wire _zz_500; + wire [4:0] _zz_501; + wire [4:0] _zz_502; + wire _zz_503; + wire [0:0] _zz_504; + wire [9:0] _zz_505; + wire [31:0] _zz_506; + wire [31:0] _zz_507; + wire [31:0] _zz_508; + wire [31:0] _zz_509; + wire [0:0] _zz_510; + wire [1:0] _zz_511; + wire [0:0] _zz_512; + wire [2:0] _zz_513; + wire [0:0] _zz_514; + wire [4:0] _zz_515; + wire [1:0] _zz_516; + wire [1:0] _zz_517; + wire _zz_518; + wire [0:0] _zz_519; + wire [6:0] _zz_520; + wire [31:0] _zz_521; + wire [31:0] _zz_522; + wire _zz_523; + wire _zz_524; + wire [31:0] _zz_525; + wire [31:0] _zz_526; + wire _zz_527; + wire [0:0] _zz_528; + wire [0:0] _zz_529; + wire _zz_530; + wire [0:0] _zz_531; + wire [2:0] _zz_532; + wire _zz_533; + wire [0:0] _zz_534; + wire [0:0] _zz_535; + wire [0:0] _zz_536; + wire [0:0] _zz_537; + wire _zz_538; + wire [0:0] _zz_539; + wire [4:0] _zz_540; + wire [31:0] _zz_541; + wire [31:0] _zz_542; + wire [31:0] _zz_543; + wire [31:0] _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire [31:0] _zz_548; + wire [31:0] _zz_549; + wire [31:0] _zz_550; + wire _zz_551; + wire [0:0] _zz_552; + wire [0:0] _zz_553; + wire [31:0] _zz_554; + wire [31:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire _zz_559; + wire [3:0] _zz_560; + wire [3:0] _zz_561; + wire _zz_562; + wire [0:0] _zz_563; + wire [2:0] _zz_564; + wire [31:0] _zz_565; + wire [31:0] _zz_566; + wire [31:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire [31:0] _zz_570; + wire _zz_571; + wire [0:0] _zz_572; + wire [1:0] _zz_573; + wire _zz_574; + wire [2:0] _zz_575; + wire [2:0] _zz_576; + wire _zz_577; + wire [0:0] _zz_578; + wire [0:0] _zz_579; + wire [31:0] _zz_580; + wire [31:0] _zz_581; + wire [31:0] _zz_582; + wire [31:0] _zz_583; + wire [31:0] _zz_584; + wire [31:0] _zz_585; + wire [31:0] _zz_586; + wire _zz_587; + wire _zz_588; + wire _zz_589; + wire [0:0] _zz_590; + wire [0:0] _zz_591; + wire _zz_592; + wire _zz_593; + wire _zz_594; + wire _zz_595; + wire [51:0] memory_MUL_LOW; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire execute_IS_DBUS_SHARING; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC2_FORCE_ZERO; + wire `BranchCtrlEnum_defaultEncoding_type _zz_1; + wire `BranchCtrlEnum_defaultEncoding_type _zz_2; + wire `BranchCtrlEnum_defaultEncoding_type _zz_3; + wire `BranchCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire `EnvCtrlEnum_defaultEncoding_type _zz_11; + wire decode_IS_CSR; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire decode_SRC_LESS_UNSIGNED; + wire memory_IS_SFENCE_VMA; + wire execute_IS_SFENCE_VMA; + wire decode_IS_SFENCE_VMA; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire execute_PREDICTION_CONTEXT_hazard; + wire [1:0] execute_PREDICTION_CONTEXT_line_history; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire execute_PREDICTION_HAD_BRANCHED2; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] execute_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_30; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_31; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_32; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_33; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_34; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_35; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_36; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_37; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_38; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_39; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_40; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_41; + wire [31:0] _zz_42; + wire _zz_43; + reg _zz_44; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `BranchCtrlEnum_defaultEncoding_type _zz_45; + wire `EnvCtrlEnum_defaultEncoding_type _zz_46; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_47; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_48; + wire `Src2CtrlEnum_defaultEncoding_type _zz_49; + wire `AluCtrlEnum_defaultEncoding_type _zz_50; + wire `Src1CtrlEnum_defaultEncoding_type _zz_51; + wire writeBack_IS_SFENCE_VMA; + wire writeBack_IS_DBUS_SHARING; + wire memory_IS_DBUS_SHARING; + reg [31:0] _zz_52; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_53; + wire [31:0] decode_INSTRUCTION; + wire `BranchCtrlEnum_defaultEncoding_type memory_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_54; + wire [31:0] memory_PC; + wire memory_PREDICTION_CONTEXT_hazard; + wire [1:0] memory_PREDICTION_CONTEXT_line_history; + wire decode_PREDICTION_CONTEXT_hazard; + wire [1:0] decode_PREDICTION_CONTEXT_line_history; + reg _zz_55; + reg [31:0] _zz_56; + reg [31:0] _zz_57; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg IBusCachedPlugin_mmuBus_rsp_isPaging; + reg IBusCachedPlugin_mmuBus_rsp_allowRead; + reg IBusCachedPlugin_mmuBus_rsp_allowWrite; + reg IBusCachedPlugin_mmuBus_rsp_allowExecute; + reg IBusCachedPlugin_mmuBus_rsp_exception; + reg IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + reg DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg DBusCachedPlugin_mmuBus_rsp_isPaging; + reg DBusCachedPlugin_mmuBus_rsp_allowRead; + reg DBusCachedPlugin_mmuBus_rsp_allowWrite; + reg DBusCachedPlugin_mmuBus_rsp_allowExecute; + reg DBusCachedPlugin_mmuBus_rsp_exception; + reg DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_4_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_4_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_5_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_5_physical; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_58; + reg MmuPlugin_dBusAccess_cmd_valid; + reg MmuPlugin_dBusAccess_cmd_ready; + reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; + wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size; + wire MmuPlugin_dBusAccess_cmd_payload_write; + wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data; + wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask; + wire MmuPlugin_dBusAccess_rsp_valid; + wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data; + wire MmuPlugin_dBusAccess_rsp_payload_error; + wire MmuPlugin_dBusAccess_rsp_payload_redo; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_59; + wire [3:0] _zz_60; + wire _zz_61; + wire _zz_62; + wire _zz_63; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_64; + wire _zz_65; + wire _zz_66; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_67; + wire _zz_68; + reg _zz_69; + wire _zz_70; + reg _zz_71; + reg [31:0] _zz_72; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_74; + wire [9:0] _zz_75; + reg _zz_76; + reg [9:0] _zz_77; + wire [29:0] _zz_78; + wire _zz_79; + reg _zz_80; + reg [1:0] _zz_81; + wire _zz_82; + wire _zz_83; + reg [10:0] _zz_84; + wire _zz_85; + reg [18:0] _zz_86; + reg _zz_87; + wire _zz_88; + reg [10:0] _zz_89; + wire _zz_90; + reg [18:0] _zz_91; + wire [31:0] _zz_92; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire [31:0] _zz_93; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_94; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_95; + reg [31:0] _zz_96; + wire _zz_97; + reg [31:0] _zz_98; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + reg DBusCachedPlugin_forceDatapath; + reg MmuPlugin_status_sum; + reg MmuPlugin_status_mxr; + reg MmuPlugin_status_mprv; + reg MmuPlugin_satp_mode; + reg [8:0] MmuPlugin_satp_asid; + reg [19:0] MmuPlugin_satp_ppn; + reg MmuPlugin_ports_0_cache_0_valid; + reg MmuPlugin_ports_0_cache_0_exception; + reg MmuPlugin_ports_0_cache_0_superPage; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1; + reg MmuPlugin_ports_0_cache_0_allowRead; + reg MmuPlugin_ports_0_cache_0_allowWrite; + reg MmuPlugin_ports_0_cache_0_allowExecute; + reg MmuPlugin_ports_0_cache_0_allowUser; + reg MmuPlugin_ports_0_cache_1_valid; + reg MmuPlugin_ports_0_cache_1_exception; + reg MmuPlugin_ports_0_cache_1_superPage; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1; + reg MmuPlugin_ports_0_cache_1_allowRead; + reg MmuPlugin_ports_0_cache_1_allowWrite; + reg MmuPlugin_ports_0_cache_1_allowExecute; + reg MmuPlugin_ports_0_cache_1_allowUser; + reg MmuPlugin_ports_0_cache_2_valid; + reg MmuPlugin_ports_0_cache_2_exception; + reg MmuPlugin_ports_0_cache_2_superPage; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1; + reg MmuPlugin_ports_0_cache_2_allowRead; + reg MmuPlugin_ports_0_cache_2_allowWrite; + reg MmuPlugin_ports_0_cache_2_allowExecute; + reg MmuPlugin_ports_0_cache_2_allowUser; + reg MmuPlugin_ports_0_cache_3_valid; + reg MmuPlugin_ports_0_cache_3_exception; + reg MmuPlugin_ports_0_cache_3_superPage; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1; + reg MmuPlugin_ports_0_cache_3_allowRead; + reg MmuPlugin_ports_0_cache_3_allowWrite; + reg MmuPlugin_ports_0_cache_3_allowExecute; + reg MmuPlugin_ports_0_cache_3_allowUser; + wire MmuPlugin_ports_0_dirty; + reg MmuPlugin_ports_0_requireMmuLockupCalc; + reg [3:0] MmuPlugin_ports_0_cacheHitsCalc; + wire MmuPlugin_ports_0_cacheHit; + wire _zz_99; + wire _zz_100; + wire _zz_101; + wire [1:0] _zz_102; + wire MmuPlugin_ports_0_cacheLine_valid; + wire MmuPlugin_ports_0_cacheLine_exception; + wire MmuPlugin_ports_0_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_0_cacheLine_allowRead; + wire MmuPlugin_ports_0_cacheLine_allowWrite; + wire MmuPlugin_ports_0_cacheLine_allowExecute; + wire MmuPlugin_ports_0_cacheLine_allowUser; + reg MmuPlugin_ports_0_entryToReplace_willIncrement; + wire MmuPlugin_ports_0_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_0_entryToReplace_value; + wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_0_entryToReplace_willOverflow; + reg MmuPlugin_ports_1_cache_0_valid; + reg MmuPlugin_ports_1_cache_0_exception; + reg MmuPlugin_ports_1_cache_0_superPage; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1; + reg MmuPlugin_ports_1_cache_0_allowRead; + reg MmuPlugin_ports_1_cache_0_allowWrite; + reg MmuPlugin_ports_1_cache_0_allowExecute; + reg MmuPlugin_ports_1_cache_0_allowUser; + reg MmuPlugin_ports_1_cache_1_valid; + reg MmuPlugin_ports_1_cache_1_exception; + reg MmuPlugin_ports_1_cache_1_superPage; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1; + reg MmuPlugin_ports_1_cache_1_allowRead; + reg MmuPlugin_ports_1_cache_1_allowWrite; + reg MmuPlugin_ports_1_cache_1_allowExecute; + reg MmuPlugin_ports_1_cache_1_allowUser; + reg MmuPlugin_ports_1_cache_2_valid; + reg MmuPlugin_ports_1_cache_2_exception; + reg MmuPlugin_ports_1_cache_2_superPage; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1; + reg MmuPlugin_ports_1_cache_2_allowRead; + reg MmuPlugin_ports_1_cache_2_allowWrite; + reg MmuPlugin_ports_1_cache_2_allowExecute; + reg MmuPlugin_ports_1_cache_2_allowUser; + reg MmuPlugin_ports_1_cache_3_valid; + reg MmuPlugin_ports_1_cache_3_exception; + reg MmuPlugin_ports_1_cache_3_superPage; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1; + reg MmuPlugin_ports_1_cache_3_allowRead; + reg MmuPlugin_ports_1_cache_3_allowWrite; + reg MmuPlugin_ports_1_cache_3_allowExecute; + reg MmuPlugin_ports_1_cache_3_allowUser; + reg MmuPlugin_ports_1_cache_4_valid; + reg MmuPlugin_ports_1_cache_4_exception; + reg MmuPlugin_ports_1_cache_4_superPage; + reg [9:0] MmuPlugin_ports_1_cache_4_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_4_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_4_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_4_physicalAddress_1; + reg MmuPlugin_ports_1_cache_4_allowRead; + reg MmuPlugin_ports_1_cache_4_allowWrite; + reg MmuPlugin_ports_1_cache_4_allowExecute; + reg MmuPlugin_ports_1_cache_4_allowUser; + reg MmuPlugin_ports_1_cache_5_valid; + reg MmuPlugin_ports_1_cache_5_exception; + reg MmuPlugin_ports_1_cache_5_superPage; + reg [9:0] MmuPlugin_ports_1_cache_5_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_5_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_5_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_5_physicalAddress_1; + reg MmuPlugin_ports_1_cache_5_allowRead; + reg MmuPlugin_ports_1_cache_5_allowWrite; + reg MmuPlugin_ports_1_cache_5_allowExecute; + reg MmuPlugin_ports_1_cache_5_allowUser; + wire MmuPlugin_ports_1_dirty; + reg MmuPlugin_ports_1_requireMmuLockupCalc; + reg [5:0] MmuPlugin_ports_1_cacheHitsCalc; + wire MmuPlugin_ports_1_cacheHit; + wire _zz_103; + wire _zz_104; + wire _zz_105; + wire _zz_106; + wire _zz_107; + wire [2:0] _zz_108; + wire MmuPlugin_ports_1_cacheLine_valid; + wire MmuPlugin_ports_1_cacheLine_exception; + wire MmuPlugin_ports_1_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_1_cacheLine_allowRead; + wire MmuPlugin_ports_1_cacheLine_allowWrite; + wire MmuPlugin_ports_1_cacheLine_allowExecute; + wire MmuPlugin_ports_1_cacheLine_allowUser; + reg MmuPlugin_ports_1_entryToReplace_willIncrement; + wire MmuPlugin_ports_1_entryToReplace_willClear; + reg [2:0] MmuPlugin_ports_1_entryToReplace_valueNext; + reg [2:0] MmuPlugin_ports_1_entryToReplace_value; + wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_1_entryToReplace_willOverflow; + reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1; + reg [9:0] MmuPlugin_shared_vpn_0; + reg [9:0] MmuPlugin_shared_vpn_1; + reg [1:0] MmuPlugin_shared_portSortedOh; + reg MmuPlugin_shared_dBusRspStaged_valid; + reg [31:0] MmuPlugin_shared_dBusRspStaged_payload_data; + reg MmuPlugin_shared_dBusRspStaged_payload_error; + reg MmuPlugin_shared_dBusRspStaged_payload_redo; + wire MmuPlugin_shared_dBusRsp_pte_V; + wire MmuPlugin_shared_dBusRsp_pte_R; + wire MmuPlugin_shared_dBusRsp_pte_W; + wire MmuPlugin_shared_dBusRsp_pte_X; + wire MmuPlugin_shared_dBusRsp_pte_U; + wire MmuPlugin_shared_dBusRsp_pte_G; + wire MmuPlugin_shared_dBusRsp_pte_A; + wire MmuPlugin_shared_dBusRsp_pte_D; + wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW; + wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0; + wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; + wire MmuPlugin_shared_dBusRsp_exception; + wire MmuPlugin_shared_dBusRsp_leaf; + reg MmuPlugin_shared_pteBuffer_V; + reg MmuPlugin_shared_pteBuffer_R; + reg MmuPlugin_shared_pteBuffer_W; + reg MmuPlugin_shared_pteBuffer_X; + reg MmuPlugin_shared_pteBuffer_U; + reg MmuPlugin_shared_pteBuffer_G; + reg MmuPlugin_shared_pteBuffer_A; + reg MmuPlugin_shared_pteBuffer_D; + reg [1:0] MmuPlugin_shared_pteBuffer_RSW; + reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; + reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; + reg [1:0] _zz_109; + wire [1:0] _zz_110; + reg [1:0] _zz_111; + wire [1:0] MmuPlugin_shared_refills; + wire [1:0] _zz_112; + reg [1:0] _zz_113; + wire [31:0] _zz_114; + wire [32:0] _zz_115; + wire _zz_116; + wire _zz_117; + wire _zz_118; + wire _zz_119; + wire `Src1CtrlEnum_defaultEncoding_type _zz_120; + wire `AluCtrlEnum_defaultEncoding_type _zz_121; + wire `Src2CtrlEnum_defaultEncoding_type _zz_122; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_123; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_124; + wire `EnvCtrlEnum_defaultEncoding_type _zz_125; + wire `BranchCtrlEnum_defaultEncoding_type _zz_126; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_127; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_128; + reg [31:0] _zz_129; + wire _zz_130; + reg [19:0] _zz_131; + wire _zz_132; + reg [19:0] _zz_133; + reg [31:0] _zz_134; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_135; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_136; + reg _zz_137; + reg _zz_138; + reg _zz_139; + reg [4:0] _zz_140; + reg [31:0] _zz_141; + wire _zz_142; + wire _zz_143; + wire _zz_144; + wire _zz_145; + wire _zz_146; + wire _zz_147; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_148; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_149; + wire _zz_150; + wire _zz_151; + reg [32:0] _zz_152; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + wire [1:0] CsrPlugin_mtvec_mode; + wire [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_153; + wire _zz_154; + wire _zz_155; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_156; + wire _zz_157; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_158; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_159; + reg _zz_160; + reg _zz_161; + wire _zz_162; + reg [19:0] _zz_163; + wire _zz_164; + reg [10:0] _zz_165; + wire _zz_166; + reg [18:0] _zz_167; + reg _zz_168; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_169; + reg [19:0] _zz_170; + wire _zz_171; + reg [10:0] _zz_172; + wire _zz_173; + reg [18:0] _zz_174; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_PREDICTION_CONTEXT_hazard; + reg [1:0] decode_to_execute_PREDICTION_CONTEXT_line_history; + reg execute_to_memory_PREDICTION_CONTEXT_hazard; + reg [1:0] execute_to_memory_PREDICTION_CONTEXT_line_history; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_IS_SFENCE_VMA; + reg execute_to_memory_IS_SFENCE_VMA; + reg memory_to_writeBack_IS_SFENCE_VMA; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type execute_to_memory_BRANCH_CTRL; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_IS_DBUS_SHARING; + reg memory_to_writeBack_IS_DBUS_SHARING; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [2:0] _zz_175; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_256; + reg execute_CsrPlugin_csr_384; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + `ifndef SYNTHESIS + reg [31:0] _zz_1_string; + reg [31:0] _zz_2_string; + reg [31:0] _zz_3_string; + reg [31:0] _zz_4_string; + reg [31:0] _zz_5_string; + reg [31:0] _zz_6_string; + reg [31:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] decode_ENV_CTRL_string; + reg [31:0] _zz_9_string; + reg [31:0] _zz_10_string; + reg [31:0] _zz_11_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_14_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_17_string; + reg [39:0] _zz_18_string; + reg [39:0] _zz_19_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_20_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_23_string; + reg [63:0] _zz_24_string; + reg [63:0] _zz_25_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_26_string; + reg [95:0] _zz_27_string; + reg [95:0] _zz_28_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_29_string; + reg [31:0] memory_ENV_CTRL_string; + reg [31:0] _zz_30_string; + reg [31:0] execute_ENV_CTRL_string; + reg [31:0] _zz_31_string; + reg [31:0] writeBack_ENV_CTRL_string; + reg [31:0] _zz_32_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_35_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_36_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_38_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_39_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_40_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_41_string; + reg [31:0] _zz_45_string; + reg [31:0] _zz_46_string; + reg [71:0] _zz_47_string; + reg [39:0] _zz_48_string; + reg [23:0] _zz_49_string; + reg [63:0] _zz_50_string; + reg [95:0] _zz_51_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_53_string; + reg [31:0] memory_BRANCH_CTRL_string; + reg [31:0] _zz_54_string; + reg [47:0] MmuPlugin_shared_state_1_string; + reg [95:0] _zz_120_string; + reg [63:0] _zz_121_string; + reg [23:0] _zz_122_string; + reg [39:0] _zz_123_string; + reg [71:0] _zz_124_string; + reg [31:0] _zz_125_string; + reg [31:0] _zz_126_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_ENV_CTRL_string; + reg [31:0] execute_to_memory_ENV_CTRL_string; + reg [31:0] memory_to_writeBack_ENV_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [31:0] execute_to_memory_BRANCH_CTRL_string; + `endif + + reg [1:0] _zz_73 [0:1023]; + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_240 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_241 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_242 = 1'b1; + assign _zz_243 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_244 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_245 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_246 = ((_zz_189 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_247 = ((_zz_189 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_248 = ((_zz_189 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_249 = ((_zz_189 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_250 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_251 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_252 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_253 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_254 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_255 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_256 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_257 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign _zz_258 = (! dataCache_1_io_cpu_execute_refilling); + assign _zz_259 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_260 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign _zz_261 = MmuPlugin_shared_portSortedOh[0]; + assign _zz_262 = MmuPlugin_shared_portSortedOh[1]; + assign _zz_263 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_264 = (1'b0 || (! 1'b1)); + assign _zz_265 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_266 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_267 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_268 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_269 = execute_INSTRUCTION[13 : 12]; + assign _zz_270 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_271 = (! memory_arbitration_isStuck); + assign _zz_272 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_273 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_274 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_275 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign _zz_276 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign _zz_277 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign _zz_278 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign _zz_279 = (MmuPlugin_ports_1_entryToReplace_value == 3'b000); + assign _zz_280 = (MmuPlugin_ports_1_entryToReplace_value == 3'b001); + assign _zz_281 = (MmuPlugin_ports_1_entryToReplace_value == 3'b010); + assign _zz_282 = (MmuPlugin_ports_1_entryToReplace_value == 3'b011); + assign _zz_283 = (MmuPlugin_ports_1_entryToReplace_value == 3'b100); + assign _zz_284 = (MmuPlugin_ports_1_entryToReplace_value == 3'b101); + assign _zz_285 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_286 = ((_zz_153 && 1'b1) && (! 1'b0)); + assign _zz_287 = ((_zz_154 && 1'b1) && (! 1'b0)); + assign _zz_288 = ((_zz_155 && 1'b1) && (! 1'b0)); + assign _zz_289 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_290 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_291 = execute_INSTRUCTION[13]; + assign _zz_292 = ($signed(_zz_293) + $signed(_zz_298)); + assign _zz_293 = ($signed(_zz_294) + $signed(_zz_296)); + assign _zz_294 = 52'h0; + assign _zz_295 = {1'b0,memory_MUL_LL}; + assign _zz_296 = {{19{_zz_295[32]}}, _zz_295}; + assign _zz_297 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_298 = {{2{_zz_297[49]}}, _zz_297}; + assign _zz_299 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; + assign _zz_301 = ($signed(_zz_303) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_302 = _zz_301[31 : 0]; + assign _zz_303 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_304 = _zz_115[28 : 28]; + assign _zz_305 = _zz_115[27 : 27]; + assign _zz_306 = _zz_115[26 : 26]; + assign _zz_307 = _zz_115[25 : 25]; + assign _zz_308 = _zz_115[24 : 24]; + assign _zz_309 = _zz_115[18 : 18]; + assign _zz_310 = _zz_115[17 : 17]; + assign _zz_311 = _zz_115[16 : 16]; + assign _zz_312 = _zz_115[13 : 13]; + assign _zz_313 = _zz_115[12 : 12]; + assign _zz_314 = _zz_115[11 : 11]; + assign _zz_315 = _zz_115[30 : 30]; + assign _zz_316 = _zz_115[15 : 15]; + assign _zz_317 = _zz_115[5 : 5]; + assign _zz_318 = _zz_115[3 : 3]; + assign _zz_319 = _zz_115[21 : 21]; + assign _zz_320 = _zz_115[10 : 10]; + assign _zz_321 = _zz_115[4 : 4]; + assign _zz_322 = _zz_115[0 : 0]; + assign _zz_323 = (_zz_59 - 4'b0001); + assign _zz_324 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_325 = {29'd0, _zz_324}; + assign _zz_326 = ($signed(memory_PREDICTION_CONTEXT_line_history) + $signed(_zz_327)); + assign _zz_327 = (_zz_82 ? _zz_328 : _zz_329); + assign _zz_328 = 2'b11; + assign _zz_329 = 2'b01; + assign _zz_330 = _zz_78[9:0]; + assign _zz_331 = (IBusCachedPlugin_iBusRsp_stages_0_input_payload >>> 2); + assign _zz_332 = _zz_331[9:0]; + assign _zz_333 = (_zz_82 ? _zz_334 : _zz_335); + assign _zz_334 = 2'b10; + assign _zz_335 = 2'b01; + assign _zz_336 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_337 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_338 = {{_zz_84,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_339 = {{_zz_86,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_340 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_341 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_342 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_343 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_344 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_345 = {1'd0, _zz_344}; + assign _zz_346 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_347 = {2'd0, _zz_346}; + assign _zz_348 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; + assign _zz_349 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; + assign _zz_350 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; + assign _zz_351 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; + assign _zz_352 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; + assign _zz_353 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; + assign _zz_354 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; + assign _zz_355 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; + assign _zz_356 = (_zz_111 - 2'b01); + assign _zz_357 = execute_SRC_LESS; + assign _zz_358 = 3'b100; + assign _zz_359 = execute_INSTRUCTION[19 : 15]; + assign _zz_360 = execute_INSTRUCTION[31 : 20]; + assign _zz_361 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_362 = ($signed(_zz_363) + $signed(_zz_366)); + assign _zz_363 = ($signed(_zz_364) + $signed(_zz_365)); + assign _zz_364 = execute_SRC1; + assign _zz_365 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_366 = (execute_SRC_USE_SUB_LESS ? _zz_367 : _zz_368); + assign _zz_367 = 32'h00000001; + assign _zz_368 = 32'h0; + assign _zz_369 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_370 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_371 = writeBack_MUL_LOW[31 : 0]; + assign _zz_372 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_373 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_374 = {5'd0, _zz_373}; + assign _zz_375 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_376 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_377 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_378 = {_zz_148,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_379 = _zz_380; + assign _zz_380 = _zz_381; + assign _zz_381 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_149) : _zz_149)} + _zz_383); + assign _zz_382 = memory_DivPlugin_div_needRevert; + assign _zz_383 = {32'd0, _zz_382}; + assign _zz_384 = _zz_151; + assign _zz_385 = {32'd0, _zz_384}; + assign _zz_386 = _zz_150; + assign _zz_387 = {31'd0, _zz_386}; + assign _zz_388 = (_zz_156 & (~ _zz_389)); + assign _zz_389 = (_zz_156 - 2'b01); + assign _zz_390 = execute_INSTRUCTION[31 : 20]; + assign _zz_391 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_392 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_393 = {_zz_163,execute_INSTRUCTION[31 : 20]}; + assign _zz_394 = {{_zz_165,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_395 = {{_zz_167,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_396 = execute_INSTRUCTION[31 : 20]; + assign _zz_397 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_398 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_399 = 3'b100; + assign _zz_400 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_401 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_402 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_403 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_404 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_405 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_406 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_407 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_408 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_409 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_410 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_411 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_412 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_413 = _zz_326; + assign _zz_414 = 1'b1; + assign _zz_415 = 1'b1; + assign _zz_416 = {_zz_63,_zz_62}; + assign _zz_417 = 32'h0000107f; + assign _zz_418 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_419 = 32'h00002073; + assign _zz_420 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_421 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_422 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_423) == 32'h00000003),{(_zz_424 == _zz_425),{_zz_426,{_zz_427,_zz_428}}}}}}; + assign _zz_423 = 32'h0000505f; + assign _zz_424 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_425 = 32'h00000063; + assign _zz_426 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_427 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_428 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_429) == 32'h00001013),{(_zz_430 == _zz_431),{_zz_432,{_zz_433,_zz_434}}}}}}; + assign _zz_429 = 32'hfc00307f; + assign _zz_430 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_431 = 32'h00005033; + assign _zz_432 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_433 = ((decode_INSTRUCTION & 32'hfe007fff) == 32'h12000073); + assign _zz_434 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00100073)}; + assign _zz_435 = decode_INSTRUCTION[31]; + assign _zz_436 = decode_INSTRUCTION[31]; + assign _zz_437 = decode_INSTRUCTION[7]; + assign _zz_438 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_439 = 32'h00000004; + assign _zz_440 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_441 = 32'h00000040; + assign _zz_442 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz_443 = ((decode_INSTRUCTION & 32'h02103050) == 32'h00000050); + assign _zz_444 = 1'b0; + assign _zz_445 = ({(_zz_448 == _zz_449),(_zz_450 == _zz_451)} != 2'b00); + assign _zz_446 = (_zz_119 != 1'b0); + assign _zz_447 = {(_zz_119 != 1'b0),{(_zz_452 != _zz_453),{_zz_454,{_zz_455,_zz_456}}}}; + assign _zz_448 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_449 = 32'h00001050; + assign _zz_450 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_451 = 32'h00002050; + assign _zz_452 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_453 = 1'b0; + assign _zz_454 = (((decode_INSTRUCTION & _zz_457) == 32'h02000030) != 1'b0); + assign _zz_455 = ({_zz_458,_zz_459} != 2'b00); + assign _zz_456 = {({_zz_460,_zz_461} != 3'b000),{(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}}; + assign _zz_457 = 32'h02004074; + assign _zz_458 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_459 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_460 = ((decode_INSTRUCTION & _zz_467) == 32'h40001010); + assign _zz_461 = {(_zz_468 == _zz_469),(_zz_470 == _zz_471)}; + assign _zz_462 = ((decode_INSTRUCTION & _zz_472) == 32'h00000024); + assign _zz_463 = 1'b0; + assign _zz_464 = ((_zz_473 == _zz_474) != 1'b0); + assign _zz_465 = (_zz_475 != 1'b0); + assign _zz_466 = {(_zz_476 != _zz_477),{_zz_478,{_zz_479,_zz_480}}}; + assign _zz_467 = 32'h40003054; + assign _zz_468 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_469 = 32'h00001010; + assign _zz_470 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_471 = 32'h00001010; + assign _zz_472 = 32'h00000064; + assign _zz_473 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_474 = 32'h00001000; + assign _zz_475 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_476 = {(_zz_481 == _zz_482),(_zz_483 == _zz_484)}; + assign _zz_477 = 2'b00; + assign _zz_478 = ((_zz_485 == _zz_486) != 1'b0); + assign _zz_479 = (_zz_487 != 1'b0); + assign _zz_480 = {(_zz_488 != _zz_489),{_zz_490,{_zz_491,_zz_492}}}; + assign _zz_481 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_482 = 32'h00002000; + assign _zz_483 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_484 = 32'h00001000; + assign _zz_485 = (decode_INSTRUCTION & 32'h02003050); + assign _zz_486 = 32'h02000050; + assign _zz_487 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz_488 = {(_zz_493 == _zz_494),(_zz_495 == _zz_496)}; + assign _zz_489 = 2'b00; + assign _zz_490 = ({_zz_497,{_zz_498,_zz_499}} != 3'b000); + assign _zz_491 = (_zz_500 != 1'b0); + assign _zz_492 = {(_zz_501 != _zz_502),{_zz_503,{_zz_504,_zz_505}}}; + assign _zz_493 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_494 = 32'h00000020; + assign _zz_495 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_496 = 32'h00000020; + assign _zz_497 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_498 = ((decode_INSTRUCTION & _zz_506) == 32'h0); + assign _zz_499 = ((decode_INSTRUCTION & _zz_507) == 32'h00000040); + assign _zz_500 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_501 = {(_zz_508 == _zz_509),{_zz_117,{_zz_510,_zz_511}}}; + assign _zz_502 = 5'h0; + assign _zz_503 = ({_zz_117,{_zz_512,_zz_513}} != 5'h0); + assign _zz_504 = ({_zz_514,_zz_515} != 6'h0); + assign _zz_505 = {(_zz_516 != _zz_517),{_zz_518,{_zz_519,_zz_520}}}; + assign _zz_506 = 32'h00000038; + assign _zz_507 = 32'h02103040; + assign _zz_508 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_509 = 32'h00000040; + assign _zz_510 = (_zz_521 == _zz_522); + assign _zz_511 = {_zz_523,_zz_524}; + assign _zz_512 = (_zz_525 == _zz_526); + assign _zz_513 = {_zz_527,{_zz_528,_zz_529}}; + assign _zz_514 = _zz_118; + assign _zz_515 = {_zz_530,{_zz_531,_zz_532}}; + assign _zz_516 = {_zz_117,_zz_533}; + assign _zz_517 = 2'b00; + assign _zz_518 = ({_zz_534,_zz_535} != 2'b00); + assign _zz_519 = (_zz_536 != _zz_537); + assign _zz_520 = {_zz_538,{_zz_539,_zz_540}}; + assign _zz_521 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_522 = 32'h00004020; + assign _zz_523 = ((decode_INSTRUCTION & _zz_541) == 32'h00000010); + assign _zz_524 = ((decode_INSTRUCTION & _zz_542) == 32'h00000020); + assign _zz_525 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_526 = 32'h00002010; + assign _zz_527 = ((decode_INSTRUCTION & _zz_543) == 32'h00000010); + assign _zz_528 = (_zz_544 == _zz_545); + assign _zz_529 = (_zz_546 == _zz_547); + assign _zz_530 = ((decode_INSTRUCTION & _zz_548) == 32'h00001010); + assign _zz_531 = (_zz_549 == _zz_550); + assign _zz_532 = {_zz_551,{_zz_552,_zz_553}}; + assign _zz_533 = ((decode_INSTRUCTION & _zz_554) == 32'h00000020); + assign _zz_534 = _zz_117; + assign _zz_535 = (_zz_555 == _zz_556); + assign _zz_536 = (_zz_557 == _zz_558); + assign _zz_537 = 1'b0; + assign _zz_538 = (_zz_559 != 1'b0); + assign _zz_539 = (_zz_560 != _zz_561); + assign _zz_540 = {_zz_562,{_zz_563,_zz_564}}; + assign _zz_541 = 32'h00000030; + assign _zz_542 = 32'h02000020; + assign _zz_543 = 32'h00001030; + assign _zz_544 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_545 = 32'h00002020; + assign _zz_546 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_547 = 32'h00000020; + assign _zz_548 = 32'h00001010; + assign _zz_549 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_550 = 32'h00002010; + assign _zz_551 = ((decode_INSTRUCTION & _zz_565) == 32'h00000010); + assign _zz_552 = (_zz_566 == _zz_567); + assign _zz_553 = (_zz_568 == _zz_569); + assign _zz_554 = 32'h00000070; + assign _zz_555 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_556 = 32'h0; + assign _zz_557 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_558 = 32'h00004010; + assign _zz_559 = ((decode_INSTRUCTION & _zz_570) == 32'h00002010); + assign _zz_560 = {_zz_571,{_zz_572,_zz_573}}; + assign _zz_561 = 4'b0000; + assign _zz_562 = (_zz_574 != 1'b0); + assign _zz_563 = (_zz_575 != _zz_576); + assign _zz_564 = {_zz_577,{_zz_578,_zz_579}}; + assign _zz_565 = 32'h00000050; + assign _zz_566 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_567 = 32'h00000004; + assign _zz_568 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_569 = 32'h0; + assign _zz_570 = 32'h00006014; + assign _zz_571 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_572 = ((decode_INSTRUCTION & _zz_580) == 32'h0); + assign _zz_573 = {(_zz_581 == _zz_582),(_zz_583 == _zz_584)}; + assign _zz_574 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_575 = {(_zz_585 == _zz_586),{_zz_587,_zz_588}}; + assign _zz_576 = 3'b000; + assign _zz_577 = ({_zz_589,_zz_116} != 2'b00); + assign _zz_578 = ({_zz_590,_zz_591} != 2'b00); + assign _zz_579 = (_zz_592 != 1'b0); + assign _zz_580 = 32'h00000018; + assign _zz_581 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_582 = 32'h00002000; + assign _zz_583 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_584 = 32'h00001000; + assign _zz_585 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_586 = 32'h00000040; + assign _zz_587 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_588 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_589 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_590 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_591 = _zz_116; + assign _zz_592 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_593 = execute_INSTRUCTION[31]; + assign _zz_594 = execute_INSTRUCTION[31]; + assign _zz_595 = execute_INSTRUCTION[7]; + always @ (posedge clk) begin + if(_zz_55) begin + _zz_73[_zz_75] <= _zz_413; + end + end + + always @ (posedge clk) begin + if(_zz_79) begin + _zz_214 <= _zz_73[_zz_330]; + end + end + + always @ (posedge clk) begin + if(_zz_414) begin + _zz_215 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_415) begin + _zz_216 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_44) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_184 ), //i + .io_cpu_prefetch_isValid (_zz_185 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_186 ), //i + .io_cpu_fetch_isStuck (_zz_187 ), //i + .io_cpu_fetch_isRemoved (_zz_188 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_189 ), //i + .io_cpu_decode_isStuck (_zz_190 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_191 ), //i + .io_cpu_fill_valid (_zz_192 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_10 (_zz_175[2:0] ), //i + ._zz_11 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_193 ), //i + .io_cpu_execute_address (_zz_194[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (_zz_195 ), //i + .io_cpu_execute_args_data (_zz_196[31:0] ), //i + .io_cpu_execute_args_size (_zz_197[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_198 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_199[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_200 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_4_sel (DBusCachedPlugin_mmuBus_rsp_ways_4_sel ), //i + .io_cpu_memory_mmuRsp_ways_4_physical (DBusCachedPlugin_mmuBus_rsp_ways_4_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_5_sel (DBusCachedPlugin_mmuBus_rsp_ways_5_sel ), //i + .io_cpu_memory_mmuRsp_ways_5_physical (DBusCachedPlugin_mmuBus_rsp_ways_5_physical[31:0] ), //i + .io_cpu_writeBack_isValid (_zz_201 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_202 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_203[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_204 ), //i + .io_cpu_writeBack_fence_SR (_zz_205 ), //i + .io_cpu_writeBack_fence_SO (_zz_206 ), //i + .io_cpu_writeBack_fence_SI (_zz_207 ), //i + .io_cpu_writeBack_fence_PW (_zz_208 ), //i + .io_cpu_writeBack_fence_PR (_zz_209 ), //i + .io_cpu_writeBack_fence_PO (_zz_210 ), //i + .io_cpu_writeBack_fence_PI (_zz_211 ), //i + .io_cpu_writeBack_fence_FM (_zz_212[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_213 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dBus_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_416) + 2'b00 : begin + _zz_217 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_217 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_217 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_217 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_102) + 2'b00 : begin + _zz_218 = MmuPlugin_ports_0_cache_0_valid; + _zz_219 = MmuPlugin_ports_0_cache_0_exception; + _zz_220 = MmuPlugin_ports_0_cache_0_superPage; + _zz_221 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_222 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_223 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_224 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_225 = MmuPlugin_ports_0_cache_0_allowRead; + _zz_226 = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_227 = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_228 = MmuPlugin_ports_0_cache_0_allowUser; + end + 2'b01 : begin + _zz_218 = MmuPlugin_ports_0_cache_1_valid; + _zz_219 = MmuPlugin_ports_0_cache_1_exception; + _zz_220 = MmuPlugin_ports_0_cache_1_superPage; + _zz_221 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_222 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_223 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_224 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_225 = MmuPlugin_ports_0_cache_1_allowRead; + _zz_226 = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_227 = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_228 = MmuPlugin_ports_0_cache_1_allowUser; + end + 2'b10 : begin + _zz_218 = MmuPlugin_ports_0_cache_2_valid; + _zz_219 = MmuPlugin_ports_0_cache_2_exception; + _zz_220 = MmuPlugin_ports_0_cache_2_superPage; + _zz_221 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_222 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_223 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_224 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_225 = MmuPlugin_ports_0_cache_2_allowRead; + _zz_226 = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_227 = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_228 = MmuPlugin_ports_0_cache_2_allowUser; + end + default : begin + _zz_218 = MmuPlugin_ports_0_cache_3_valid; + _zz_219 = MmuPlugin_ports_0_cache_3_exception; + _zz_220 = MmuPlugin_ports_0_cache_3_superPage; + _zz_221 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_222 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_223 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_224 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_225 = MmuPlugin_ports_0_cache_3_allowRead; + _zz_226 = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_227 = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_228 = MmuPlugin_ports_0_cache_3_allowUser; + end + endcase + end + + always @(*) begin + case(_zz_108) + 3'b000 : begin + _zz_229 = MmuPlugin_ports_1_cache_0_valid; + _zz_230 = MmuPlugin_ports_1_cache_0_exception; + _zz_231 = MmuPlugin_ports_1_cache_0_superPage; + _zz_232 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_0_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_0_allowUser; + end + 3'b001 : begin + _zz_229 = MmuPlugin_ports_1_cache_1_valid; + _zz_230 = MmuPlugin_ports_1_cache_1_exception; + _zz_231 = MmuPlugin_ports_1_cache_1_superPage; + _zz_232 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_1_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_1_allowUser; + end + 3'b010 : begin + _zz_229 = MmuPlugin_ports_1_cache_2_valid; + _zz_230 = MmuPlugin_ports_1_cache_2_exception; + _zz_231 = MmuPlugin_ports_1_cache_2_superPage; + _zz_232 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_2_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_2_allowUser; + end + 3'b011 : begin + _zz_229 = MmuPlugin_ports_1_cache_3_valid; + _zz_230 = MmuPlugin_ports_1_cache_3_exception; + _zz_231 = MmuPlugin_ports_1_cache_3_superPage; + _zz_232 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_3_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_3_allowUser; + end + 3'b100 : begin + _zz_229 = MmuPlugin_ports_1_cache_4_valid; + _zz_230 = MmuPlugin_ports_1_cache_4_exception; + _zz_231 = MmuPlugin_ports_1_cache_4_superPage; + _zz_232 = MmuPlugin_ports_1_cache_4_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_4_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_4_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_4_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_4_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_4_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_4_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_4_allowUser; + end + default : begin + _zz_229 = MmuPlugin_ports_1_cache_5_valid; + _zz_230 = MmuPlugin_ports_1_cache_5_exception; + _zz_231 = MmuPlugin_ports_1_cache_5_superPage; + _zz_232 = MmuPlugin_ports_1_cache_5_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_5_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_5_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_5_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_5_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_5_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_5_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_5_allowUser; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `BranchCtrlEnum_defaultEncoding_INC : _zz_1_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_1_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_1_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_1_string = "JALR"; + default : _zz_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_2) + `BranchCtrlEnum_defaultEncoding_INC : _zz_2_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_2_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_2_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_2_string = "JALR"; + default : _zz_2_string = "????"; + endcase + end + always @(*) begin + case(_zz_3) + `BranchCtrlEnum_defaultEncoding_INC : _zz_3_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_3_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_3_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_3_string = "JALR"; + default : _zz_3_string = "????"; + endcase + end + always @(*) begin + case(_zz_4) + `BranchCtrlEnum_defaultEncoding_INC : _zz_4_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_4_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_4_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_4_string = "JALR"; + default : _zz_4_string = "????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET"; + default : _zz_5_string = "????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET"; + default : _zz_6_string = "????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET"; + default : _zz_7_string = "????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET"; + default : _zz_8_string = "????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET"; + default : decode_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET"; + default : _zz_9_string = "????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET"; + default : _zz_10_string = "????"; + endcase + end + always @(*) begin + case(_zz_11) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_11_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_11_string = "XRET"; + default : _zz_11_string = "????"; + endcase + end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; + endcase + end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase + end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; + endcase + end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase + end + always @(*) begin + case(_zz_25) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; + default : _zz_25_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_29) + `BranchCtrlEnum_defaultEncoding_INC : _zz_29_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_29_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_29_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_29_string = "JALR"; + default : _zz_29_string = "????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET"; + default : memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_30) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_30_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_30_string = "XRET"; + default : _zz_30_string = "????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET"; + default : execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_31) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_31_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_31_string = "XRET"; + default : _zz_31_string = "????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET"; + default : writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_32) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_32_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_32_string = "XRET"; + default : _zz_32_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_35) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35_string = "SRA_1 "; + default : _zz_35_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_36) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_36_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_36_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_36_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_36_string = "SRA_1 "; + default : _zz_36_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_38) + `Src2CtrlEnum_defaultEncoding_RS : _zz_38_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_38_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_38_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_38_string = "PC "; + default : _zz_38_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_39) + `Src1CtrlEnum_defaultEncoding_RS : _zz_39_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_39_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_39_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_39_string = "URS1 "; + default : _zz_39_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_40) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_40_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_40_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_40_string = "BITWISE "; + default : _zz_40_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_41) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_41_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_41_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_41_string = "AND_1"; + default : _zz_41_string = "?????"; + endcase + end + always @(*) begin + case(_zz_45) + `BranchCtrlEnum_defaultEncoding_INC : _zz_45_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_45_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_45_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_45_string = "JALR"; + default : _zz_45_string = "????"; + endcase + end + always @(*) begin + case(_zz_46) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_46_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_46_string = "XRET"; + default : _zz_46_string = "????"; + endcase + end + always @(*) begin + case(_zz_47) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_47_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_47_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_47_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_47_string = "SRA_1 "; + default : _zz_47_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_48) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_48_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_48_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_48_string = "AND_1"; + default : _zz_48_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49) + `Src2CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_49_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_49_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_49_string = "PC "; + default : _zz_49_string = "???"; + endcase + end + always @(*) begin + case(_zz_50) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_50_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_50_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_50_string = "BITWISE "; + default : _zz_50_string = "????????"; + endcase + end + always @(*) begin + case(_zz_51) + `Src1CtrlEnum_defaultEncoding_RS : _zz_51_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_51_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_51_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_51_string = "URS1 "; + default : _zz_51_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_53) + `BranchCtrlEnum_defaultEncoding_INC : _zz_53_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_53_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_53_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_53_string = "JALR"; + default : _zz_53_string = "????"; + endcase + end + always @(*) begin + case(memory_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : memory_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : memory_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : memory_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : memory_BRANCH_CTRL_string = "JALR"; + default : memory_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_54) + `BranchCtrlEnum_defaultEncoding_INC : _zz_54_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_54_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_54_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_54_string = "JALR"; + default : _zz_54_string = "????"; + endcase + end + always @(*) begin + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; + default : MmuPlugin_shared_state_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_120) + `Src1CtrlEnum_defaultEncoding_RS : _zz_120_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_120_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_120_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_120_string = "URS1 "; + default : _zz_120_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_121) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_121_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_121_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_121_string = "BITWISE "; + default : _zz_121_string = "????????"; + endcase + end + always @(*) begin + case(_zz_122) + `Src2CtrlEnum_defaultEncoding_RS : _zz_122_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_122_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_122_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_122_string = "PC "; + default : _zz_122_string = "???"; + endcase + end + always @(*) begin + case(_zz_123) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_123_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_123_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_123_string = "AND_1"; + default : _zz_123_string = "?????"; + endcase + end + always @(*) begin + case(_zz_124) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_124_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_124_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_124_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_124_string = "SRA_1 "; + default : _zz_124_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_125) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_125_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_125_string = "XRET"; + default : _zz_125_string = "????"; + endcase + end + always @(*) begin + case(_zz_126) + `BranchCtrlEnum_defaultEncoding_INC : _zz_126_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_126_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_126_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_126_string = "JALR"; + default : _zz_126_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; + default : decode_to_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; + default : execute_to_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; + default : memory_to_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_to_memory_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_to_memory_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_to_memory_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_to_memory_BRANCH_CTRL_string = "JALR"; + default : execute_to_memory_BRANCH_CTRL_string = "????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_292) + $signed(_zz_300)); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_SHIFT_RIGHT = _zz_302; + assign execute_REGFILE_WRITE_DATA = _zz_128; + assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_194[1 : 0]; + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign _zz_5 = _zz_6; + assign _zz_7 = _zz_8; + assign decode_ENV_CTRL = _zz_9; + assign _zz_10 = _zz_11; + assign decode_IS_CSR = _zz_304[0]; + assign decode_IS_RS2_SIGNED = _zz_305[0]; + assign decode_IS_RS1_SIGNED = _zz_306[0]; + assign decode_IS_DIV = _zz_307[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_308[0]; + assign _zz_12 = _zz_13; + assign decode_SHIFT_CTRL = _zz_14; + assign _zz_15 = _zz_16; + assign decode_ALU_BITWISE_CTRL = _zz_17; + assign _zz_18 = _zz_19; + assign decode_SRC_LESS_UNSIGNED = _zz_309[0]; + assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; + assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; + assign decode_IS_SFENCE_VMA = _zz_310[0]; + assign decode_MEMORY_MANAGMENT = _zz_311[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_312[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_313[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_314[0]; + assign decode_SRC2_CTRL = _zz_20; + assign _zz_21 = _zz_22; + assign decode_ALU_CTRL = _zz_23; + assign _zz_24 = _zz_25; + assign decode_SRC1_CTRL = _zz_26; + assign _zz_27 = _zz_28; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign execute_PREDICTION_CONTEXT_hazard = decode_to_execute_PREDICTION_CONTEXT_hazard; + assign execute_PREDICTION_CONTEXT_line_history = decode_to_execute_PREDICTION_CONTEXT_line_history; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_BRANCH_COND_RESULT = _zz_161; + assign execute_BRANCH_CTRL = _zz_29; + assign execute_PC = decode_to_execute_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_315[0]; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_30; + assign execute_ENV_CTRL = _zz_31; + assign writeBack_ENV_CTRL = _zz_32; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_RS1 = decode_to_execute_RS1; + assign decode_RS2_USE = _zz_316[0]; + assign decode_RS1_USE = _zz_317[0]; + always @ (*) begin + _zz_33 = execute_REGFILE_WRITE_DATA; + if(_zz_240)begin + _zz_33 = execute_CsrPlugin_readData; + end + if(DBusCachedPlugin_forceDatapath)begin + _zz_33 = MmuPlugin_dBusAccess_cmd_payload_address; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_139)begin + if((_zz_140 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_141; + end + end + if(_zz_241)begin + if(_zz_242)begin + if(_zz_143)begin + decode_RS2 = _zz_52; + end + end + end + if(_zz_243)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_145)begin + decode_RS2 = _zz_34; + end + end + end + if(_zz_244)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_147)begin + decode_RS2 = _zz_33; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_139)begin + if((_zz_140 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_141; + end + end + if(_zz_241)begin + if(_zz_242)begin + if(_zz_142)begin + decode_RS1 = _zz_52; + end + end + end + if(_zz_243)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_144)begin + decode_RS1 = _zz_34; + end + end + end + if(_zz_244)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_146)begin + decode_RS1 = _zz_33; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_34 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_34 = _zz_136; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_34 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(_zz_245)begin + _zz_34 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_35; + assign execute_SHIFT_CTRL = _zz_36; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_37 = execute_PC; + assign execute_SRC2_CTRL = _zz_38; + assign execute_SRC1_CTRL = _zz_39; + assign decode_SRC_USE_SUB_LESS = _zz_318[0]; + assign decode_SRC_ADD_ZERO = _zz_319[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_40; + assign execute_SRC2 = _zz_134; + assign execute_SRC1 = _zz_129; + assign execute_ALU_BITWISE_CTRL = _zz_41; + assign _zz_42 = writeBack_INSTRUCTION; + assign _zz_43 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_44 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_44 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_320[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_417) == 32'h00001073),{(_zz_418 == _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}} != 21'h0); + assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; + assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; + assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; + always @ (*) begin + _zz_52 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_52 = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_290) + 2'b00 : begin + _zz_52 = _zz_371; + end + default : begin + _zz_52 = _zz_372; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_321[0]; + assign decode_FLUSH_ALL = _zz_322[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_246)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_247)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_248)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_249)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_53; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + assign memory_BRANCH_CTRL = _zz_54; + assign memory_PC = execute_to_memory_PC; + assign memory_PREDICTION_CONTEXT_hazard = execute_to_memory_PREDICTION_CONTEXT_hazard; + assign memory_PREDICTION_CONTEXT_line_history = execute_to_memory_PREDICTION_CONTEXT_line_history; + assign decode_PREDICTION_CONTEXT_hazard = _zz_80; + assign decode_PREDICTION_CONTEXT_line_history = _zz_81; + always @ (*) begin + _zz_55 = 1'b0; + if(_zz_74)begin + _zz_55 = 1'b1; + end + end + + always @ (*) begin + _zz_56 = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_56 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_57 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_57 = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + case(_zz_175) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid)begin + decode_arbitration_haltByOther = 1'b1; + end + if((decode_arbitration_isValid && (_zz_137 || _zz_138)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_250)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_250)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((_zz_213 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_240)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_251)begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushIt = 1'b0; + if(_zz_251)begin + if(_zz_252)begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(_zz_251)begin + if(_zz_252)begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(_zz_245)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_253)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_254)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_253)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_254)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_251)begin + if(_zz_252)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_255)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + _zz_58 = 1'b0; + if(DebugPlugin_godmode)begin + _zz_58 = 1'b1; + end + end + + assign CsrPlugin_inWfi = 1'b0; + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_253)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_254)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_253)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_254)begin + case(_zz_256) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode)begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + end + end + + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_59 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_60 = (_zz_59 & (~ _zz_323)); + assign _zz_61 = _zz_60[3]; + assign _zz_62 = (_zz_60[1] || _zz_61); + assign _zz_63 = (_zz_60[2] || _zz_61); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_217; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_325); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_64 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_64); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_64); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_65 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_65); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_65); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_67; + assign _zz_67 = ((1'b0 && (! _zz_68)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_68 = _zz_69; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_68; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_70 = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_72; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + always @ (*) begin + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(_zz_175) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + end + + assign _zz_78 = (IBusCachedPlugin_fetchPc_output_payload >>> 2); + assign _zz_79 = (IBusCachedPlugin_iBusRsp_stages_0_output_ready || IBusCachedPlugin_externalFlush); + assign _zz_82 = (IBusCachedPlugin_decodePrediction_rsp_wasWrong ^ memory_PREDICTION_CONTEXT_line_history[1]); + assign _zz_75 = (memory_PC[11 : 2] + 10'h0); + assign _zz_74 = ((((! memory_PREDICTION_CONTEXT_hazard) && memory_arbitration_isFiring) && (memory_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B)) && (! ($signed(memory_PREDICTION_CONTEXT_line_history) == $signed(_zz_333)))); + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && decode_PREDICTION_CONTEXT_line_history[1])); + if(_zz_87)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_83 = _zz_336[19]; + always @ (*) begin + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7] = _zz_83; + _zz_84[6] = _zz_83; + _zz_84[5] = _zz_83; + _zz_84[4] = _zz_83; + _zz_84[3] = _zz_83; + _zz_84[2] = _zz_83; + _zz_84[1] = _zz_83; + _zz_84[0] = _zz_83; + end + + assign _zz_85 = _zz_337[11]; + always @ (*) begin + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15] = _zz_85; + _zz_86[14] = _zz_85; + _zz_86[13] = _zz_85; + _zz_86[12] = _zz_85; + _zz_86[11] = _zz_85; + _zz_86[10] = _zz_85; + _zz_86[9] = _zz_85; + _zz_86[8] = _zz_85; + _zz_86[7] = _zz_85; + _zz_86[6] = _zz_85; + _zz_86[5] = _zz_85; + _zz_86[4] = _zz_85; + _zz_86[3] = _zz_85; + _zz_86[2] = _zz_85; + _zz_86[1] = _zz_85; + _zz_86[0] = _zz_85; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_87 = _zz_338[1]; + end + default : begin + _zz_87 = _zz_339[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_88 = _zz_340[19]; + always @ (*) begin + _zz_89[10] = _zz_88; + _zz_89[9] = _zz_88; + _zz_89[8] = _zz_88; + _zz_89[7] = _zz_88; + _zz_89[6] = _zz_88; + _zz_89[5] = _zz_88; + _zz_89[4] = _zz_88; + _zz_89[3] = _zz_88; + _zz_89[2] = _zz_88; + _zz_89[1] = _zz_88; + _zz_89[0] = _zz_88; + end + + assign _zz_90 = _zz_341[11]; + always @ (*) begin + _zz_91[18] = _zz_90; + _zz_91[17] = _zz_90; + _zz_91[16] = _zz_90; + _zz_91[15] = _zz_90; + _zz_91[14] = _zz_90; + _zz_91[13] = _zz_90; + _zz_91[12] = _zz_90; + _zz_91[11] = _zz_90; + _zz_91[10] = _zz_90; + _zz_91[9] = _zz_90; + _zz_91[8] = _zz_90; + _zz_91[7] = _zz_90; + _zz_91[6] = _zz_90; + _zz_91[5] = _zz_90; + _zz_91[4] = _zz_90; + _zz_91[3] = _zz_90; + _zz_91[2] = _zz_90; + _zz_91[1] = _zz_90; + _zz_91[0] = _zz_90; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_89,{{{_zz_435,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_91,{{{_zz_436,_zz_437},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_185 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_186 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_187 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_186; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_189 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_190 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_191 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_249)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_247)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @ (*) begin + _zz_192 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_247)begin + _zz_192 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_248)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_246)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_248)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_246)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_184 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_valid; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + _zz_193 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + if(_zz_258)begin + _zz_193 = 1'b1; + end + end + end + end + + always @ (*) begin + _zz_194 = execute_SRC_ADD; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + _zz_194 = MmuPlugin_dBusAccess_cmd_payload_address; + end + end + end + + always @ (*) begin + _zz_195 = execute_MEMORY_WR; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + _zz_195 = MmuPlugin_dBusAccess_cmd_payload_write; + end + end + end + + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_94 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_94 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_94 = execute_RS2[31 : 0]; + end + endcase + end + + always @ (*) begin + _zz_196 = _zz_94; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + _zz_196 = MmuPlugin_dBusAccess_cmd_payload_data; + end + end + end + + always @ (*) begin + _zz_197 = execute_DBusCachedPlugin_size; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + _zz_197 = MmuPlugin_dBusAccess_cmd_payload_size; + end + end + end + + assign _zz_213 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + always @ (*) begin + _zz_198 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + if(memory_IS_DBUS_SHARING)begin + _zz_198 = 1'b1; + end + end + + assign _zz_199 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_198; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_199; + always @ (*) begin + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + if(memory_IS_DBUS_SHARING)begin + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b1; + end + end + + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @ (*) begin + _zz_200 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_58 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_200 = 1'b1; + end + end + + always @ (*) begin + _zz_201 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_IS_DBUS_SHARING)begin + _zz_201 = 1'b1; + end + end + + assign _zz_202 = (CsrPlugin_privilege == 2'b00); + assign _zz_203 = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_259)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_259)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_259)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_342}; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_343}; + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_95 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_96[31] = _zz_95; + _zz_96[30] = _zz_95; + _zz_96[29] = _zz_95; + _zz_96[28] = _zz_95; + _zz_96[27] = _zz_95; + _zz_96[26] = _zz_95; + _zz_96[25] = _zz_95; + _zz_96[24] = _zz_95; + _zz_96[23] = _zz_95; + _zz_96[22] = _zz_95; + _zz_96[21] = _zz_95; + _zz_96[20] = _zz_95; + _zz_96[19] = _zz_95; + _zz_96[18] = _zz_95; + _zz_96[17] = _zz_95; + _zz_96[16] = _zz_95; + _zz_96[15] = _zz_95; + _zz_96[14] = _zz_95; + _zz_96[13] = _zz_95; + _zz_96[12] = _zz_95; + _zz_96[11] = _zz_95; + _zz_96[10] = _zz_95; + _zz_96[9] = _zz_95; + _zz_96[8] = _zz_95; + _zz_96[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_97 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_98[31] = _zz_97; + _zz_98[30] = _zz_97; + _zz_98[29] = _zz_97; + _zz_98[28] = _zz_97; + _zz_98[27] = _zz_97; + _zz_98[26] = _zz_97; + _zz_98[25] = _zz_97; + _zz_98[24] = _zz_97; + _zz_98[23] = _zz_97; + _zz_98[22] = _zz_97; + _zz_98[21] = _zz_97; + _zz_98[20] = _zz_97; + _zz_98[19] = _zz_97; + _zz_98[18] = _zz_97; + _zz_98[17] = _zz_97; + _zz_98[16] = _zz_97; + _zz_98[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_289) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_96; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_98; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + always @ (*) begin + MmuPlugin_dBusAccess_cmd_ready = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + if(_zz_258)begin + MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); + end + end + end + end + + always @ (*) begin + DBusCachedPlugin_forceDatapath = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + DBusCachedPlugin_forceDatapath = 1'b1; + end + end + end + + assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1_io_cpu_writeBack_isWrite)) && (dataCache_1_io_cpu_redo || (! dataCache_1_io_cpu_writeBack_haltIt))); + assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1_io_cpu_writeBack_data; + assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1_io_cpu_writeBack_unalignedAccess || dataCache_1_io_cpu_writeBack_accessError); + assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1_io_cpu_redo; + assign MmuPlugin_ports_0_dirty = 1'b0; + always @ (*) begin + MmuPlugin_ports_0_requireMmuLockupCalc = (((IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 28] == 4'b1100) && (! IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + if((CsrPlugin_privilege == 2'b11))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + end + + always @ (*) begin + MmuPlugin_ports_0_cacheHitsCalc[0] = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[1] = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[2] = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[3] = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + end + + assign MmuPlugin_ports_0_cacheHit = (MmuPlugin_ports_0_cacheHitsCalc != 4'b0000); + assign _zz_99 = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign _zz_100 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_99); + assign _zz_101 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_99); + assign _zz_102 = {_zz_101,_zz_100}; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_218; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_219; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_220; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_221; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_222; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_223; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_224; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_225; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_226; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_227; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_228; + always @ (*) begin + MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; + if(_zz_260)begin + if(_zz_261)begin + MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; + end + end + end + + assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0; + assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); + always @ (*) begin + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_345); + if(MmuPlugin_ports_0_entryToReplace_willClear)begin + MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); + end else begin + IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; + end else begin + IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; + end else begin + IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_0_dirty) && MmuPlugin_ports_0_cacheHit) && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); + end else begin + IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_0_dirty || (! MmuPlugin_ports_0_cacheHit)); + end else begin + IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; + end else begin + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111); + assign IBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_0_requireMmuLockupCalc); + assign IBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_0_cacheHitsCalc[0]; + assign IBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_0_cache_0_physicalAddress_1,(MmuPlugin_ports_0_cache_0_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_0_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_0_cacheHitsCalc[1]; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_0_cache_1_physicalAddress_1,(MmuPlugin_ports_0_cache_1_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_1_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_0_cacheHitsCalc[2]; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_0_cache_2_physicalAddress_1,(MmuPlugin_ports_0_cache_2_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_2_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_0_cache_3_physicalAddress_1,(MmuPlugin_ports_0_cache_3_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_3_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_ports_1_dirty = 1'b0; + always @ (*) begin + MmuPlugin_ports_1_requireMmuLockupCalc = (((DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 28] == 4'b1100) && (! DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end + if((CsrPlugin_privilege == 2'b11))begin + if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end + end + end + + always @ (*) begin + MmuPlugin_ports_1_cacheHitsCalc[0] = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[1] = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[2] = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[3] = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[4] = ((MmuPlugin_ports_1_cache_4_valid && (MmuPlugin_ports_1_cache_4_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_4_superPage || (MmuPlugin_ports_1_cache_4_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[5] = ((MmuPlugin_ports_1_cache_5_valid && (MmuPlugin_ports_1_cache_5_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_5_superPage || (MmuPlugin_ports_1_cache_5_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + end + + assign MmuPlugin_ports_1_cacheHit = (MmuPlugin_ports_1_cacheHitsCalc != 6'h0); + assign _zz_103 = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign _zz_104 = MmuPlugin_ports_1_cacheHitsCalc[5]; + assign _zz_105 = ((MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_103) || _zz_104); + assign _zz_106 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_103); + assign _zz_107 = (MmuPlugin_ports_1_cacheHitsCalc[4] || _zz_104); + assign _zz_108 = {_zz_107,{_zz_106,_zz_105}}; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_229; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_230; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_231; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_232; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_233; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_234; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_235; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_236; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_237; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_238; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_239; + always @ (*) begin + MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; + if(_zz_260)begin + if(_zz_262)begin + MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; + end + end + end + + assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; + assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 3'b101); + assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); + always @ (*) begin + if(MmuPlugin_ports_1_entryToReplace_willOverflow)begin + MmuPlugin_ports_1_entryToReplace_valueNext = 3'b000; + end else begin + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_347); + end + if(MmuPlugin_ports_1_entryToReplace_willClear)begin + MmuPlugin_ports_1_entryToReplace_valueNext = 3'b000; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); + end else begin + DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; + end else begin + DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; + end else begin + DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_1_dirty) && MmuPlugin_ports_1_cacheHit) && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); + end else begin + DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_1_dirty || (! MmuPlugin_ports_1_cacheHit)); + end else begin + DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; + end else begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111); + assign DBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_1_requireMmuLockupCalc); + assign DBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_1_cacheHitsCalc[0]; + assign DBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_1_cache_0_physicalAddress_1,(MmuPlugin_ports_1_cache_0_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_0_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_1_cacheHitsCalc[1]; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_1_cache_1_physicalAddress_1,(MmuPlugin_ports_1_cache_1_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_1_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_1_cacheHitsCalc[2]; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_4_sel = MmuPlugin_ports_1_cacheHitsCalc[4]; + assign DBusCachedPlugin_mmuBus_rsp_ways_4_physical = {{MmuPlugin_ports_1_cache_4_physicalAddress_1,(MmuPlugin_ports_1_cache_4_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_4_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_5_sel = MmuPlugin_ports_1_cacheHitsCalc[5]; + assign DBusCachedPlugin_mmuBus_rsp_ways_5_physical = {{MmuPlugin_ports_1_cache_5_physicalAddress_1,(MmuPlugin_ports_1_cache_5_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_5_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_shared_dBusRsp_pte_V = _zz_348[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = _zz_349[0]; + assign MmuPlugin_shared_dBusRsp_pte_W = _zz_350[0]; + assign MmuPlugin_shared_dBusRsp_pte_X = _zz_351[0]; + assign MmuPlugin_shared_dBusRsp_pte_U = _zz_352[0]; + assign MmuPlugin_shared_dBusRsp_pte_G = _zz_353[0]; + assign MmuPlugin_shared_dBusRsp_pte_A = _zz_354[0]; + assign MmuPlugin_shared_dBusRsp_pte_D = _zz_355[0]; + assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; + assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; + assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; + assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_shared_dBusRspStaged_payload_error); + assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X); + always @ (*) begin + MmuPlugin_dBusAccess_cmd_valid = 1'b0; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + MmuPlugin_dBusAccess_cmd_valid = 1'b1; + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + MmuPlugin_dBusAccess_cmd_valid = 1'b1; + end + default : begin + end + endcase + end + + assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; + assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; + always @ (*) begin + MmuPlugin_dBusAccess_cmd_payload_address = 32'h0; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},2'b00}; + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},2'b00}; + end + default : begin + end + endcase + end + + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'h0; + assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; + always @ (*) begin + _zz_109[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); + _zz_109[1] = (((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)); + end + + assign _zz_110 = _zz_109; + always @ (*) begin + _zz_111[0] = _zz_110[1]; + _zz_111[1] = _zz_110[0]; + end + + assign _zz_112 = (_zz_111 & (~ _zz_356)); + always @ (*) begin + _zz_113[0] = _zz_112[1]; + _zz_113[1] = _zz_112[0]; + end + + assign MmuPlugin_shared_refills = _zz_113; + assign _zz_114 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); + assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[0]); + assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[1]); + assign _zz_116 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_117 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_118 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_119 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_115 = {({_zz_118,(_zz_438 == _zz_439)} != 2'b00),{((_zz_440 == _zz_441) != 1'b0),{(_zz_442 != 1'b0),{(_zz_443 != _zz_444),{_zz_445,{_zz_446,_zz_447}}}}}}; + assign _zz_120 = _zz_115[2 : 1]; + assign _zz_51 = _zz_120; + assign _zz_121 = _zz_115[7 : 6]; + assign _zz_50 = _zz_121; + assign _zz_122 = _zz_115[9 : 8]; + assign _zz_49 = _zz_122; + assign _zz_123 = _zz_115[20 : 19]; + assign _zz_48 = _zz_123; + assign _zz_124 = _zz_115[23 : 22]; + assign _zz_47 = _zz_124; + assign _zz_125 = _zz_115[29 : 29]; + assign _zz_46 = _zz_125; + assign _zz_126 = _zz_115[32 : 31]; + assign _zz_45 = _zz_126; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_215; + assign decode_RegFilePlugin_rs2Data = _zz_216; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_43 && writeBack_arbitration_isFiring); + if(_zz_127)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_42[11 : 7]; + if(_zz_127)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_52; + if(_zz_127)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_128 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_128 = {31'd0, _zz_357}; + end + default : begin + _zz_128 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_129 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_129 = {29'd0, _zz_358}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_129 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_129 = {27'd0, _zz_359}; + end + endcase + end + + assign _zz_130 = _zz_360[11]; + always @ (*) begin + _zz_131[19] = _zz_130; + _zz_131[18] = _zz_130; + _zz_131[17] = _zz_130; + _zz_131[16] = _zz_130; + _zz_131[15] = _zz_130; + _zz_131[14] = _zz_130; + _zz_131[13] = _zz_130; + _zz_131[12] = _zz_130; + _zz_131[11] = _zz_130; + _zz_131[10] = _zz_130; + _zz_131[9] = _zz_130; + _zz_131[8] = _zz_130; + _zz_131[7] = _zz_130; + _zz_131[6] = _zz_130; + _zz_131[5] = _zz_130; + _zz_131[4] = _zz_130; + _zz_131[3] = _zz_130; + _zz_131[2] = _zz_130; + _zz_131[1] = _zz_130; + _zz_131[0] = _zz_130; + end + + assign _zz_132 = _zz_361[11]; + always @ (*) begin + _zz_133[19] = _zz_132; + _zz_133[18] = _zz_132; + _zz_133[17] = _zz_132; + _zz_133[16] = _zz_132; + _zz_133[15] = _zz_132; + _zz_133[14] = _zz_132; + _zz_133[13] = _zz_132; + _zz_133[12] = _zz_132; + _zz_133[11] = _zz_132; + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_134 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_134 = {_zz_131,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_134 = {_zz_133,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_134 = _zz_37; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_362; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_135[0] = execute_SRC1[31]; + _zz_135[1] = execute_SRC1[30]; + _zz_135[2] = execute_SRC1[29]; + _zz_135[3] = execute_SRC1[28]; + _zz_135[4] = execute_SRC1[27]; + _zz_135[5] = execute_SRC1[26]; + _zz_135[6] = execute_SRC1[25]; + _zz_135[7] = execute_SRC1[24]; + _zz_135[8] = execute_SRC1[23]; + _zz_135[9] = execute_SRC1[22]; + _zz_135[10] = execute_SRC1[21]; + _zz_135[11] = execute_SRC1[20]; + _zz_135[12] = execute_SRC1[19]; + _zz_135[13] = execute_SRC1[18]; + _zz_135[14] = execute_SRC1[17]; + _zz_135[15] = execute_SRC1[16]; + _zz_135[16] = execute_SRC1[15]; + _zz_135[17] = execute_SRC1[14]; + _zz_135[18] = execute_SRC1[13]; + _zz_135[19] = execute_SRC1[12]; + _zz_135[20] = execute_SRC1[11]; + _zz_135[21] = execute_SRC1[10]; + _zz_135[22] = execute_SRC1[9]; + _zz_135[23] = execute_SRC1[8]; + _zz_135[24] = execute_SRC1[7]; + _zz_135[25] = execute_SRC1[6]; + _zz_135[26] = execute_SRC1[5]; + _zz_135[27] = execute_SRC1[4]; + _zz_135[28] = execute_SRC1[3]; + _zz_135[29] = execute_SRC1[2]; + _zz_135[30] = execute_SRC1[1]; + _zz_135[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_135 : execute_SRC1); + always @ (*) begin + _zz_136[0] = memory_SHIFT_RIGHT[31]; + _zz_136[1] = memory_SHIFT_RIGHT[30]; + _zz_136[2] = memory_SHIFT_RIGHT[29]; + _zz_136[3] = memory_SHIFT_RIGHT[28]; + _zz_136[4] = memory_SHIFT_RIGHT[27]; + _zz_136[5] = memory_SHIFT_RIGHT[26]; + _zz_136[6] = memory_SHIFT_RIGHT[25]; + _zz_136[7] = memory_SHIFT_RIGHT[24]; + _zz_136[8] = memory_SHIFT_RIGHT[23]; + _zz_136[9] = memory_SHIFT_RIGHT[22]; + _zz_136[10] = memory_SHIFT_RIGHT[21]; + _zz_136[11] = memory_SHIFT_RIGHT[20]; + _zz_136[12] = memory_SHIFT_RIGHT[19]; + _zz_136[13] = memory_SHIFT_RIGHT[18]; + _zz_136[14] = memory_SHIFT_RIGHT[17]; + _zz_136[15] = memory_SHIFT_RIGHT[16]; + _zz_136[16] = memory_SHIFT_RIGHT[15]; + _zz_136[17] = memory_SHIFT_RIGHT[14]; + _zz_136[18] = memory_SHIFT_RIGHT[13]; + _zz_136[19] = memory_SHIFT_RIGHT[12]; + _zz_136[20] = memory_SHIFT_RIGHT[11]; + _zz_136[21] = memory_SHIFT_RIGHT[10]; + _zz_136[22] = memory_SHIFT_RIGHT[9]; + _zz_136[23] = memory_SHIFT_RIGHT[8]; + _zz_136[24] = memory_SHIFT_RIGHT[7]; + _zz_136[25] = memory_SHIFT_RIGHT[6]; + _zz_136[26] = memory_SHIFT_RIGHT[5]; + _zz_136[27] = memory_SHIFT_RIGHT[4]; + _zz_136[28] = memory_SHIFT_RIGHT[3]; + _zz_136[29] = memory_SHIFT_RIGHT[2]; + _zz_136[30] = memory_SHIFT_RIGHT[1]; + _zz_136[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_137 = 1'b0; + if(_zz_263)begin + if(_zz_264)begin + if(_zz_142)begin + _zz_137 = 1'b1; + end + end + end + if(_zz_265)begin + if(_zz_266)begin + if(_zz_144)begin + _zz_137 = 1'b1; + end + end + end + if(_zz_267)begin + if(_zz_268)begin + if(_zz_146)begin + _zz_137 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_137 = 1'b0; + end + end + + always @ (*) begin + _zz_138 = 1'b0; + if(_zz_263)begin + if(_zz_264)begin + if(_zz_143)begin + _zz_138 = 1'b1; + end + end + end + if(_zz_265)begin + if(_zz_266)begin + if(_zz_145)begin + _zz_138 = 1'b1; + end + end + end + if(_zz_267)begin + if(_zz_268)begin + if(_zz_147)begin + _zz_138 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_138 = 1'b0; + end + end + + assign _zz_142 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_143 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_144 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_145 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_146 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_147 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + always @ (*) begin + case(_zz_269) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_269) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_369) + $signed(_zz_370)); + assign memory_DivPlugin_frontendOk = 1'b1; + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_245)begin + if(_zz_270)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_271)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_374); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_148 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_148[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_375); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_376 : _zz_377); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_378[31:0]; + assign _zz_149 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_150 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_151 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_152[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_152[31 : 0] = execute_RS1; + end + + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign CsrPlugin_mtvec_mode = 2'b00; + assign CsrPlugin_mtvec_base = 30'h20000008; + assign _zz_153 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_154 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_155 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_156 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_157 = _zz_388[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_250)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_256)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_384)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_272)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_272)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_272)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_291) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid)begin + case(_zz_273) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_158))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + always @ (*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_273) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_159 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_159 == 3'b000)) begin + _zz_160 = execute_BranchPlugin_eq; + end else if((_zz_159 == 3'b001)) begin + _zz_160 = (! execute_BranchPlugin_eq); + end else if((((_zz_159 & 3'b101) == 3'b101))) begin + _zz_160 = (! execute_SRC_LESS); + end else begin + _zz_160 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_161 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_161 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_161 = 1'b1; + end + default : begin + _zz_161 = _zz_160; + end + endcase + end + + assign _zz_162 = _zz_390[11]; + always @ (*) begin + _zz_163[19] = _zz_162; + _zz_163[18] = _zz_162; + _zz_163[17] = _zz_162; + _zz_163[16] = _zz_162; + _zz_163[15] = _zz_162; + _zz_163[14] = _zz_162; + _zz_163[13] = _zz_162; + _zz_163[12] = _zz_162; + _zz_163[11] = _zz_162; + _zz_163[10] = _zz_162; + _zz_163[9] = _zz_162; + _zz_163[8] = _zz_162; + _zz_163[7] = _zz_162; + _zz_163[6] = _zz_162; + _zz_163[5] = _zz_162; + _zz_163[4] = _zz_162; + _zz_163[3] = _zz_162; + _zz_163[2] = _zz_162; + _zz_163[1] = _zz_162; + _zz_163[0] = _zz_162; + end + + assign _zz_164 = _zz_391[19]; + always @ (*) begin + _zz_165[10] = _zz_164; + _zz_165[9] = _zz_164; + _zz_165[8] = _zz_164; + _zz_165[7] = _zz_164; + _zz_165[6] = _zz_164; + _zz_165[5] = _zz_164; + _zz_165[4] = _zz_164; + _zz_165[3] = _zz_164; + _zz_165[2] = _zz_164; + _zz_165[1] = _zz_164; + _zz_165[0] = _zz_164; + end + + assign _zz_166 = _zz_392[11]; + always @ (*) begin + _zz_167[18] = _zz_166; + _zz_167[17] = _zz_166; + _zz_167[16] = _zz_166; + _zz_167[15] = _zz_166; + _zz_167[14] = _zz_166; + _zz_167[13] = _zz_166; + _zz_167[12] = _zz_166; + _zz_167[11] = _zz_166; + _zz_167[10] = _zz_166; + _zz_167[9] = _zz_166; + _zz_167[8] = _zz_166; + _zz_167[7] = _zz_166; + _zz_167[6] = _zz_166; + _zz_167[5] = _zz_166; + _zz_167[4] = _zz_166; + _zz_167[3] = _zz_166; + _zz_167[2] = _zz_166; + _zz_167[1] = _zz_166; + _zz_167[0] = _zz_166; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_168 = (_zz_393[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_168 = _zz_394[1]; + end + default : begin + _zz_168 = _zz_395[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_168); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_169 = _zz_396[11]; + always @ (*) begin + _zz_170[19] = _zz_169; + _zz_170[18] = _zz_169; + _zz_170[17] = _zz_169; + _zz_170[16] = _zz_169; + _zz_170[15] = _zz_169; + _zz_170[14] = _zz_169; + _zz_170[13] = _zz_169; + _zz_170[12] = _zz_169; + _zz_170[11] = _zz_169; + _zz_170[10] = _zz_169; + _zz_170[9] = _zz_169; + _zz_170[8] = _zz_169; + _zz_170[7] = _zz_169; + _zz_170[6] = _zz_169; + _zz_170[5] = _zz_169; + _zz_170[4] = _zz_169; + _zz_170[3] = _zz_169; + _zz_170[2] = _zz_169; + _zz_170[1] = _zz_169; + _zz_170[0] = _zz_169; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_170,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_172,{{{_zz_593,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_174,{{{_zz_594,_zz_595},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_399}; + end + end + endcase + end + + assign _zz_171 = _zz_397[19]; + always @ (*) begin + _zz_172[10] = _zz_171; + _zz_172[9] = _zz_171; + _zz_172[8] = _zz_171; + _zz_172[7] = _zz_171; + _zz_172[6] = _zz_171; + _zz_172[5] = _zz_171; + _zz_172[4] = _zz_171; + _zz_172[3] = _zz_171; + _zz_172[2] = _zz_171; + _zz_172[1] = _zz_171; + _zz_172[0] = _zz_171; + end + + assign _zz_173 = _zz_398[11]; + always @ (*) begin + _zz_174[18] = _zz_173; + _zz_174[17] = _zz_173; + _zz_174[16] = _zz_173; + _zz_174[15] = _zz_173; + _zz_174[14] = _zz_173; + _zz_174[13] = _zz_173; + _zz_174[12] = _zz_173; + _zz_174[11] = _zz_173; + _zz_174[10] = _zz_173; + _zz_174[9] = _zz_173; + _zz_174[8] = _zz_173; + _zz_174[7] = _zz_173; + _zz_174[6] = _zz_173; + _zz_174[5] = _zz_173; + _zz_174[4] = _zz_173; + _zz_174[3] = _zz_173; + _zz_174[2] = _zz_173; + _zz_174[1] = _zz_173; + _zz_174[0] = _zz_173; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + assign _zz_28 = decode_SRC1_CTRL; + assign _zz_26 = _zz_51; + assign _zz_39 = decode_to_execute_SRC1_CTRL; + assign _zz_25 = decode_ALU_CTRL; + assign _zz_23 = _zz_50; + assign _zz_40 = decode_to_execute_ALU_CTRL; + assign _zz_22 = decode_SRC2_CTRL; + assign _zz_20 = _zz_49; + assign _zz_38 = decode_to_execute_SRC2_CTRL; + assign _zz_19 = decode_ALU_BITWISE_CTRL; + assign _zz_17 = _zz_48; + assign _zz_41 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_16 = decode_SHIFT_CTRL; + assign _zz_13 = execute_SHIFT_CTRL; + assign _zz_14 = _zz_47; + assign _zz_36 = decode_to_execute_SHIFT_CTRL; + assign _zz_35 = execute_to_memory_SHIFT_CTRL; + assign _zz_11 = decode_ENV_CTRL; + assign _zz_8 = execute_ENV_CTRL; + assign _zz_6 = memory_ENV_CTRL; + assign _zz_9 = _zz_46; + assign _zz_31 = decode_to_execute_ENV_CTRL; + assign _zz_30 = execute_to_memory_ENV_CTRL; + assign _zz_32 = memory_to_writeBack_ENV_CTRL; + assign _zz_4 = decode_BRANCH_CTRL; + assign _zz_2 = execute_BRANCH_CTRL; + assign _zz_53 = _zz_45; + assign _zz_29 = decode_to_execute_BRANCH_CTRL; + assign _zz_54 = execute_to_memory_BRANCH_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(_zz_175) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_176 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_176[19 : 19] = MmuPlugin_status_mxr; + _zz_176[18 : 18] = MmuPlugin_status_sum; + _zz_176[17 : 17] = MmuPlugin_status_mprv; + _zz_176[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_176[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_176[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_256)begin + _zz_177[19 : 19] = MmuPlugin_status_mxr; + _zz_177[18 : 18] = MmuPlugin_status_sum; + _zz_177[17 : 17] = MmuPlugin_status_mprv; + end + end + + always @ (*) begin + _zz_178 = 32'h0; + if(execute_CsrPlugin_csr_384)begin + _zz_178[31 : 31] = MmuPlugin_satp_mode; + _zz_178[30 : 22] = MmuPlugin_satp_asid; + _zz_178[19 : 0] = MmuPlugin_satp_ppn; + end + end + + always @ (*) begin + _zz_179 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_179[11 : 11] = CsrPlugin_mip_MEIP; + _zz_179[7 : 7] = CsrPlugin_mip_MTIP; + _zz_179[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_180[11 : 11] = CsrPlugin_mie_MEIE; + _zz_180[7 : 7] = CsrPlugin_mie_MTIE; + _zz_180[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_181[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_182[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_182[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_183[31 : 0] = CsrPlugin_mtval; + end + end + + assign execute_CsrPlugin_readData = (((_zz_176 | _zz_177) | (_zz_178 | _zz_179)) | ((_zz_180 | _zz_181) | (_zz_182 | _zz_183))); + always @ (posedge clk or posedge reset) begin + if (reset) begin + IBusCachedPlugin_fetchPc_pcReg <= 32'h80000000; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_69 <= 1'b0; + _zz_71 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_92; + IBusCachedPlugin_rspCounter <= 32'h0; + DBusCachedPlugin_rspCounter <= _zz_93; + DBusCachedPlugin_rspCounter <= 32'h0; + MmuPlugin_status_sum <= 1'b0; + MmuPlugin_status_mxr <= 1'b0; + MmuPlugin_status_mprv <= 1'b0; + MmuPlugin_satp_mode <= 1'b0; + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_0_entryToReplace_value <= 2'b00; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_4_valid <= 1'b0; + MmuPlugin_ports_1_cache_5_valid <= 1'b0; + MmuPlugin_ports_1_entryToReplace_value <= 3'b000; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; + _zz_127 <= 1'b1; + _zz_139 <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_175 <= 3'b000; + execute_to_memory_IS_DBUS_SHARING <= 1'b0; + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_69 <= 1'b0; + end + if(_zz_67)begin + _zz_69 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_71 <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext; + if(contextSwitching)begin + if(MmuPlugin_ports_0_cache_0_exception)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_1_exception)begin + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_2_exception)begin + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_3_exception)begin + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + end + end + MmuPlugin_ports_1_entryToReplace_value <= MmuPlugin_ports_1_entryToReplace_valueNext; + if(contextSwitching)begin + if(MmuPlugin_ports_1_cache_0_exception)begin + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_1_exception)begin + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_2_exception)begin + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_3_exception)begin + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_4_exception)begin + MmuPlugin_ports_1_cache_4_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_5_exception)begin + MmuPlugin_ports_1_cache_5_valid <= 1'b0; + end + end + MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + if(_zz_274)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if((MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception))begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + end + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + end + end + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; + end + end + default : begin + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + end + end + end + endcase + if(_zz_260)begin + if(_zz_261)begin + if(_zz_275)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b1; + end + if(_zz_276)begin + MmuPlugin_ports_0_cache_1_valid <= 1'b1; + end + if(_zz_277)begin + MmuPlugin_ports_0_cache_2_valid <= 1'b1; + end + if(_zz_278)begin + MmuPlugin_ports_0_cache_3_valid <= 1'b1; + end + end + if(_zz_262)begin + if(_zz_279)begin + MmuPlugin_ports_1_cache_0_valid <= 1'b1; + end + if(_zz_280)begin + MmuPlugin_ports_1_cache_1_valid <= 1'b1; + end + if(_zz_281)begin + MmuPlugin_ports_1_cache_2_valid <= 1'b1; + end + if(_zz_282)begin + MmuPlugin_ports_1_cache_3_valid <= 1'b1; + end + if(_zz_283)begin + MmuPlugin_ports_1_cache_4_valid <= 1'b1; + end + if(_zz_284)begin + MmuPlugin_ports_1_cache_5_valid <= 1'b1; + end + end + end + if((writeBack_arbitration_isValid && writeBack_IS_SFENCE_VMA))begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_4_valid <= 1'b0; + MmuPlugin_ports_1_cache_5_valid <= 1'b0; + end + _zz_127 <= 1'b0; + _zz_139 <= (_zz_43 && writeBack_arbitration_isFiring); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_285)begin + if(_zz_286)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_287)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_288)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_253)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_254)begin + case(_zz_256) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_155,{_zz_154,_zz_153}} != 3'b000) || CsrPlugin_thirdPartyWake); + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_DBUS_SHARING <= memory_IS_DBUS_SHARING; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_175) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_175 <= 3'b001; + end + end + 3'b001 : begin + _zz_175 <= 3'b010; + end + 3'b010 : begin + _zz_175 <= 3'b011; + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_175 <= 3'b100; + end + end + 3'b100 : begin + _zz_175 <= 3'b000; + end + default : begin + end + endcase + if(MmuPlugin_dBusAccess_rsp_valid)begin + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_status_mxr <= _zz_400[0]; + MmuPlugin_status_sum <= _zz_401[0]; + MmuPlugin_status_mprv <= _zz_402[0]; + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_403[0]; + CsrPlugin_mstatus_MIE <= _zz_404[0]; + end + end + if(execute_CsrPlugin_csr_256)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_status_mxr <= _zz_405[0]; + MmuPlugin_status_sum <= _zz_406[0]; + MmuPlugin_status_mprv <= _zz_407[0]; + end + end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_4_valid <= 1'b0; + MmuPlugin_ports_1_cache_5_valid <= 1'b0; + end + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_mode <= _zz_408[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_410[0]; + CsrPlugin_mie_MTIE <= _zz_411[0]; + CsrPlugin_mie_MSIE <= _zz_412[0]; + end + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_72 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + _zz_76 <= _zz_74; + _zz_77 <= _zz_75; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_80 <= (_zz_76 && (_zz_77 == _zz_332)); + _zz_81 <= _zz_214[1 : 0]; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + MmuPlugin_shared_dBusRspStaged_payload_data <= MmuPlugin_dBusAccess_rsp_payload_data; + MmuPlugin_shared_dBusRspStaged_payload_error <= MmuPlugin_dBusAccess_rsp_payload_error; + MmuPlugin_shared_dBusRspStaged_payload_redo <= MmuPlugin_dBusAccess_rsp_payload_redo; + if((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)))begin + MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; + MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_shared_pteBuffer_X <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_shared_pteBuffer_U <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_shared_pteBuffer_G <= MmuPlugin_shared_dBusRsp_pte_G; + MmuPlugin_shared_pteBuffer_A <= MmuPlugin_shared_dBusRsp_pte_A; + MmuPlugin_shared_pteBuffer_D <= MmuPlugin_shared_dBusRsp_pte_D; + MmuPlugin_shared_pteBuffer_RSW <= MmuPlugin_shared_dBusRsp_pte_RSW; + MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; + end + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + if(_zz_274)begin + MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; + MmuPlugin_shared_vpn_1 <= _zz_114[31 : 22]; + MmuPlugin_shared_vpn_0 <= _zz_114[21 : 12]; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + end + default : begin + end + endcase + if(_zz_260)begin + if(_zz_261)begin + if(_zz_275)begin + MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_276)begin + MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_277)begin + MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_278)begin + MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + if(_zz_262)begin + if(_zz_279)begin + MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_280)begin + MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_281)begin + MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_282)begin + MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_283)begin + MmuPlugin_ports_1_cache_4_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_4_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_4_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_4_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_4_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_4_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_4_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_4_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_4_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_4_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_284)begin + MmuPlugin_ports_1_cache_5_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_5_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_5_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_5_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_5_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_5_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_5_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_5_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_5_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_5_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + end + _zz_140 <= _zz_42[11 : 7]; + _zz_141 <= _zz_52; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_245)begin + if(_zz_270)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_379[31:0]; + end + end + end + if(_zz_271)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_151 ? (~ _zz_152) : _zz_152) + _zz_385); + memory_DivPlugin_rs2 <= ((_zz_150 ? (~ execute_RS2) : execute_RS2) + _zz_387); + memory_DivPlugin_div_needRevert <= ((_zz_151 ^ (_zz_150 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_250)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_157 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_157 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_285)begin + if(_zz_286)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_287)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_288)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_253)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_37; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_57; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_56; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_CONTEXT_hazard <= decode_PREDICTION_CONTEXT_hazard; + decode_to_execute_PREDICTION_CONTEXT_line_history <= decode_PREDICTION_CONTEXT_line_history; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PREDICTION_CONTEXT_hazard <= execute_PREDICTION_CONTEXT_hazard; + execute_to_memory_PREDICTION_CONTEXT_line_history <= execute_PREDICTION_CONTEXT_line_history; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_27; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_24; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_21; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_18; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_15; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_12; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_10; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_7; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_5; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_3; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_33; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_34; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_256 <= (decode_INSTRUCTION[31 : 20] == 12'h100); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_384 <= (decode_INSTRUCTION[31 : 20] == 12'h180); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_asid <= execute_CsrPlugin_writeData[30 : 22]; + MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; + end + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_409[0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_52; + end + _zz_158 <= debug_bus_cmd_payload_address[2]; + if(_zz_251)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk or posedge debugReset) begin + if (debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_273) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(_zz_251)begin + if(_zz_252)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_255)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_memory_mmuRsp_ways_0_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_0_physical, + input io_cpu_memory_mmuRsp_ways_1_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_1_physical, + input io_cpu_memory_mmuRsp_ways_2_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_2_physical, + input io_cpu_memory_mmuRsp_ways_3_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_3_physical, + input io_cpu_memory_mmuRsp_ways_4_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_4_physical, + input io_cpu_memory_mmuRsp_ways_5_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_5_physical, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_mmuRsp_ways_0_sel; + reg [31:0] stageB_mmuRsp_ways_0_physical; + reg stageB_mmuRsp_ways_1_sel; + reg [31:0] stageB_mmuRsp_ways_1_physical; + reg stageB_mmuRsp_ways_2_sel; + reg [31:0] stageB_mmuRsp_ways_2_physical; + reg stageB_mmuRsp_ways_3_sel; + reg [31:0] stageB_mmuRsp_ways_3_physical; + reg stageB_mmuRsp_ways_4_sel; + reg [31:0] stageB_mmuRsp_ways_4_physical; + reg stageB_mmuRsp_ways_5_sel; + reg [31:0] stageB_mmuRsp_ways_5_physical; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + reg [21:0] ways_0_tags [0:127]; + reg [7:0] ways_0_data_symbol0 [0:1023]; + reg [7:0] ways_0_data_symbol1 [0:1023]; + reg [7:0] ways_0_data_symbol2 [0:1023]; + reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + end + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; + end + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + stageB_mmuRsp_ways_0_sel <= io_cpu_memory_mmuRsp_ways_0_sel; + stageB_mmuRsp_ways_0_physical <= io_cpu_memory_mmuRsp_ways_0_physical; + stageB_mmuRsp_ways_1_sel <= io_cpu_memory_mmuRsp_ways_1_sel; + stageB_mmuRsp_ways_1_physical <= io_cpu_memory_mmuRsp_ways_1_physical; + stageB_mmuRsp_ways_2_sel <= io_cpu_memory_mmuRsp_ways_2_sel; + stageB_mmuRsp_ways_2_physical <= io_cpu_memory_mmuRsp_ways_2_physical; + stageB_mmuRsp_ways_3_sel <= io_cpu_memory_mmuRsp_ways_3_sel; + stageB_mmuRsp_ways_3_physical <= io_cpu_memory_mmuRsp_ways_3_physical; + stageB_mmuRsp_ways_4_sel <= io_cpu_memory_mmuRsp_ways_4_sel; + stageB_mmuRsp_ways_4_physical <= io_cpu_memory_mmuRsp_ways_4_physical; + stageB_mmuRsp_ways_5_sel <= io_cpu_memory_mmuRsp_ways_5_sel; + stageB_mmuRsp_ways_5_physical <= io_cpu_memory_mmuRsp_ways_5_physical; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk or posedge reset) begin + if (reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + input io_cpu_fetch_mmuRsp_ways_0_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_0_physical, + input io_cpu_fetch_mmuRsp_ways_1_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_1_physical, + input io_cpu_fetch_mmuRsp_ways_2_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_2_physical, + input io_cpu_fetch_mmuRsp_ways_3_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_3_physical, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_10, + input [31:0] _zz_11, + input clk, + input reset +); + reg [31:0] _zz_12; + reg [21:0] _zz_13; + wire _zz_14; + wire _zz_15; + wire [0:0] _zz_16; + wire [0:0] _zz_17; + wire [21:0] _zz_18; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_mmuRsp_ways_0_sel; + reg [31:0] decodeStage_mmuRsp_ways_0_physical; + reg decodeStage_mmuRsp_ways_1_sel; + reg [31:0] decodeStage_mmuRsp_ways_1_physical; + reg decodeStage_mmuRsp_ways_2_sel; + reg [31:0] decodeStage_mmuRsp_ways_2_physical; + reg decodeStage_mmuRsp_ways_3_sel; + reg [31:0] decodeStage_mmuRsp_ways_3_physical; + reg decodeStage_hit_tags_0_valid; + reg decodeStage_hit_tags_0_error; + reg [19:0] decodeStage_hit_tags_0_address; + wire decodeStage_hit_hits_0; + wire decodeStage_hit_valid; + reg [31:0] _zz_9; + wire [31:0] decodeStage_hit_data; + reg [31:0] banks_0 [0:1023]; + reg [21:0] ways_0_tags [0:127]; + + assign _zz_14 = (! lineLoader_flushCounter[7]); + assign _zz_15 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_16 = _zz_8[0 : 0]; + assign _zz_17 = _zz_8[1 : 1]; + assign _zz_18 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_12 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_18; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_13 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_14)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_12; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_13; + assign fetchStage_read_waysValues_0_tag_valid = _zz_16[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_17[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign io_cpu_fetch_data = fetchStage_read_banksValue_0_data; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 12])); + assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != 1'b0); + assign decodeStage_hit_data = _zz_9; + assign io_cpu_decode_data = decodeStage_hit_data; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_tags_0_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk or posedge reset) begin + if (reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_15)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_14)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_15)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + decodeStage_mmuRsp_ways_0_sel <= io_cpu_fetch_mmuRsp_ways_0_sel; + decodeStage_mmuRsp_ways_0_physical <= io_cpu_fetch_mmuRsp_ways_0_physical; + decodeStage_mmuRsp_ways_1_sel <= io_cpu_fetch_mmuRsp_ways_1_sel; + decodeStage_mmuRsp_ways_1_physical <= io_cpu_fetch_mmuRsp_ways_1_physical; + decodeStage_mmuRsp_ways_2_sel <= io_cpu_fetch_mmuRsp_ways_2_sel; + decodeStage_mmuRsp_ways_2_physical <= io_cpu_fetch_mmuRsp_ways_2_physical; + decodeStage_mmuRsp_ways_3_sel <= io_cpu_fetch_mmuRsp_ways_3_sel; + decodeStage_mmuRsp_ways_3_physical <= io_cpu_fetch_mmuRsp_ways_3_physical; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_tags_0_valid <= fetchStage_read_waysValues_0_tag_valid; + decodeStage_hit_tags_0_error <= fetchStage_read_waysValues_0_tag_error; + decodeStage_hit_tags_0_address <= fetchStage_read_waysValues_0_tag_address; + end + if((! io_cpu_decode_isStuck))begin + _zz_9 <= fetchStage_read_banksValue_0_data; + end + if((_zz_10 != 3'b000))begin + _zz_9 <= _zz_11; + end + end + + +endmodule diff --git a/BENCHMARK/vexriscv/vexriscv_linux.v b/BENCHMARK/vexriscv/vexriscv_linux.v new file mode 100644 index 0000000..644b467 --- /dev/null +++ b/BENCHMARK/vexriscv/vexriscv_linux.v @@ -0,0 +1,8248 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : 36b3cd918896c94c4e8a224d97c559ab6dbf3ec9 + + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define MmuPlugin_shared_State_defaultEncoding_type [2:0] +`define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000 +`define MmuPlugin_shared_State_defaultEncoding_L1_CMD 3'b001 +`define MmuPlugin_shared_State_defaultEncoding_L1_RSP 3'b010 +`define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011 +`define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100 + + +module VexRiscv ( + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output dBus_cmd_payload_uncached, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [3:0] dBus_cmd_payload_mask, + output [2:0] dBus_cmd_payload_length, + output dBus_cmd_payload_last, + input dBus_rsp_valid, + input dBus_rsp_payload_last, + input [31:0] dBus_rsp_payload_data, + input dBus_rsp_payload_error, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input externalInterruptS, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBus_cmd_valid, + input iBus_cmd_ready, + output reg [31:0] iBus_cmd_payload_address, + output [2:0] iBus_cmd_payload_size, + input iBus_rsp_valid, + input [31:0] iBus_rsp_payload_data, + input iBus_rsp_payload_error, + input clk, + input reset, + input debugReset +); + wire _zz_186; + wire _zz_187; + wire _zz_188; + wire _zz_189; + wire _zz_190; + wire _zz_191; + wire _zz_192; + wire _zz_193; + reg _zz_194; + reg _zz_195; + reg [31:0] _zz_196; + reg _zz_197; + reg [31:0] _zz_198; + reg [1:0] _zz_199; + reg _zz_200; + reg _zz_201; + wire _zz_202; + wire [2:0] _zz_203; + reg _zz_204; + wire [31:0] _zz_205; + reg _zz_206; + reg _zz_207; + wire _zz_208; + wire [31:0] _zz_209; + wire _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire [3:0] _zz_218; + wire _zz_219; + wire _zz_220; + reg [31:0] _zz_221; + reg [31:0] _zz_222; + reg [31:0] _zz_223; + reg _zz_224; + reg _zz_225; + reg _zz_226; + reg [9:0] _zz_227; + reg [9:0] _zz_228; + reg [9:0] _zz_229; + reg [9:0] _zz_230; + reg _zz_231; + reg _zz_232; + reg _zz_233; + reg _zz_234; + reg _zz_235; + reg _zz_236; + reg _zz_237; + reg [9:0] _zz_238; + reg [9:0] _zz_239; + reg [9:0] _zz_240; + reg [9:0] _zz_241; + reg _zz_242; + reg _zz_243; + reg _zz_244; + reg _zz_245; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_246; + wire _zz_247; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire _zz_254; + wire _zz_255; + wire _zz_256; + wire _zz_257; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire _zz_261; + wire _zz_262; + wire [1:0] _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire [1:0] _zz_273; + wire _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire [5:0] _zz_279; + wire _zz_280; + wire _zz_281; + wire _zz_282; + wire _zz_283; + wire _zz_284; + wire _zz_285; + wire _zz_286; + wire _zz_287; + wire _zz_288; + wire _zz_289; + wire _zz_290; + wire _zz_291; + wire _zz_292; + wire _zz_293; + wire _zz_294; + wire _zz_295; + wire _zz_296; + wire _zz_297; + wire _zz_298; + wire _zz_299; + wire _zz_300; + wire _zz_301; + wire _zz_302; + wire _zz_303; + wire [1:0] _zz_304; + wire [1:0] _zz_305; + wire _zz_306; + wire [51:0] _zz_307; + wire [51:0] _zz_308; + wire [51:0] _zz_309; + wire [32:0] _zz_310; + wire [51:0] _zz_311; + wire [49:0] _zz_312; + wire [51:0] _zz_313; + wire [49:0] _zz_314; + wire [51:0] _zz_315; + wire [32:0] _zz_316; + wire [31:0] _zz_317; + wire [32:0] _zz_318; + wire [0:0] _zz_319; + wire [0:0] _zz_320; + wire [0:0] _zz_321; + wire [0:0] _zz_322; + wire [0:0] _zz_323; + wire [0:0] _zz_324; + wire [0:0] _zz_325; + wire [0:0] _zz_326; + wire [0:0] _zz_327; + wire [0:0] _zz_328; + wire [0:0] _zz_329; + wire [0:0] _zz_330; + wire [0:0] _zz_331; + wire [0:0] _zz_332; + wire [0:0] _zz_333; + wire [0:0] _zz_334; + wire [0:0] _zz_335; + wire [0:0] _zz_336; + wire [0:0] _zz_337; + wire [0:0] _zz_338; + wire [0:0] _zz_339; + wire [4:0] _zz_340; + wire [2:0] _zz_341; + wire [31:0] _zz_342; + wire [11:0] _zz_343; + wire [31:0] _zz_344; + wire [19:0] _zz_345; + wire [11:0] _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; + wire [19:0] _zz_349; + wire [11:0] _zz_350; + wire [2:0] _zz_351; + wire [2:0] _zz_352; + wire [0:0] _zz_353; + wire [2:0] _zz_354; + wire [4:0] _zz_355; + wire [11:0] _zz_356; + wire [11:0] _zz_357; + wire [31:0] _zz_358; + wire [31:0] _zz_359; + wire [31:0] _zz_360; + wire [31:0] _zz_361; + wire [31:0] _zz_362; + wire [31:0] _zz_363; + wire [31:0] _zz_364; + wire [65:0] _zz_365; + wire [65:0] _zz_366; + wire [31:0] _zz_367; + wire [31:0] _zz_368; + wire [0:0] _zz_369; + wire [5:0] _zz_370; + wire [32:0] _zz_371; + wire [31:0] _zz_372; + wire [31:0] _zz_373; + wire [32:0] _zz_374; + wire [32:0] _zz_375; + wire [32:0] _zz_376; + wire [32:0] _zz_377; + wire [0:0] _zz_378; + wire [32:0] _zz_379; + wire [0:0] _zz_380; + wire [32:0] _zz_381; + wire [0:0] _zz_382; + wire [31:0] _zz_383; + wire [1:0] _zz_384; + wire [1:0] _zz_385; + wire [11:0] _zz_386; + wire [19:0] _zz_387; + wire [11:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire [31:0] _zz_391; + wire [11:0] _zz_392; + wire [19:0] _zz_393; + wire [11:0] _zz_394; + wire [2:0] _zz_395; + wire [0:0] _zz_396; + wire [1:0] _zz_397; + wire [0:0] _zz_398; + wire [1:0] _zz_399; + wire [0:0] _zz_400; + wire [0:0] _zz_401; + wire [0:0] _zz_402; + wire [0:0] _zz_403; + wire [0:0] _zz_404; + wire [0:0] _zz_405; + wire [0:0] _zz_406; + wire [0:0] _zz_407; + wire [1:0] _zz_408; + wire [0:0] _zz_409; + wire [0:0] _zz_410; + wire [0:0] _zz_411; + wire [0:0] _zz_412; + wire [0:0] _zz_413; + wire [0:0] _zz_414; + wire [0:0] _zz_415; + wire [0:0] _zz_416; + wire [0:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire [0:0] _zz_420; + wire [0:0] _zz_421; + wire [0:0] _zz_422; + wire [0:0] _zz_423; + wire [0:0] _zz_424; + wire [0:0] _zz_425; + wire [0:0] _zz_426; + wire [0:0] _zz_427; + wire [0:0] _zz_428; + wire [0:0] _zz_429; + wire [0:0] _zz_430; + wire [0:0] _zz_431; + wire [0:0] _zz_432; + wire [0:0] _zz_433; + wire [0:0] _zz_434; + wire [0:0] _zz_435; + wire [0:0] _zz_436; + wire [0:0] _zz_437; + wire [0:0] _zz_438; + wire [0:0] _zz_439; + wire [0:0] _zz_440; + wire [0:0] _zz_441; + wire [0:0] _zz_442; + wire [0:0] _zz_443; + wire [0:0] _zz_444; + wire [0:0] _zz_445; + wire [0:0] _zz_446; + wire [0:0] _zz_447; + wire [0:0] _zz_448; + wire [0:0] _zz_449; + wire [0:0] _zz_450; + wire [0:0] _zz_451; + wire [0:0] _zz_452; + wire [0:0] _zz_453; + wire _zz_454; + wire _zz_455; + wire [2:0] _zz_456; + wire [31:0] _zz_457; + wire [31:0] _zz_458; + wire [31:0] _zz_459; + wire _zz_460; + wire [0:0] _zz_461; + wire [17:0] _zz_462; + wire [31:0] _zz_463; + wire [31:0] _zz_464; + wire [31:0] _zz_465; + wire _zz_466; + wire [0:0] _zz_467; + wire [11:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire [31:0] _zz_471; + wire _zz_472; + wire [0:0] _zz_473; + wire [5:0] _zz_474; + wire [31:0] _zz_475; + wire [31:0] _zz_476; + wire [31:0] _zz_477; + wire _zz_478; + wire _zz_479; + wire _zz_480; + wire _zz_481; + wire _zz_482; + wire [31:0] _zz_483; + wire _zz_484; + wire _zz_485; + wire [0:0] _zz_486; + wire [0:0] _zz_487; + wire _zz_488; + wire [0:0] _zz_489; + wire [29:0] _zz_490; + wire [31:0] _zz_491; + wire [31:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire [31:0] _zz_496; + wire [0:0] _zz_497; + wire [0:0] _zz_498; + wire [0:0] _zz_499; + wire [0:0] _zz_500; + wire _zz_501; + wire [0:0] _zz_502; + wire [25:0] _zz_503; + wire [31:0] _zz_504; + wire [31:0] _zz_505; + wire _zz_506; + wire [1:0] _zz_507; + wire [1:0] _zz_508; + wire _zz_509; + wire [0:0] _zz_510; + wire [21:0] _zz_511; + wire [31:0] _zz_512; + wire [31:0] _zz_513; + wire [31:0] _zz_514; + wire [31:0] _zz_515; + wire _zz_516; + wire [0:0] _zz_517; + wire [0:0] _zz_518; + wire _zz_519; + wire [0:0] _zz_520; + wire [0:0] _zz_521; + wire _zz_522; + wire [0:0] _zz_523; + wire [18:0] _zz_524; + wire [31:0] _zz_525; + wire [31:0] _zz_526; + wire [31:0] _zz_527; + wire _zz_528; + wire _zz_529; + wire _zz_530; + wire [0:0] _zz_531; + wire [0:0] _zz_532; + wire _zz_533; + wire [0:0] _zz_534; + wire [15:0] _zz_535; + wire [31:0] _zz_536; + wire _zz_537; + wire [0:0] _zz_538; + wire [1:0] _zz_539; + wire _zz_540; + wire [0:0] _zz_541; + wire [0:0] _zz_542; + wire _zz_543; + wire [0:0] _zz_544; + wire [12:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire [31:0] _zz_548; + wire [31:0] _zz_549; + wire [31:0] _zz_550; + wire [31:0] _zz_551; + wire _zz_552; + wire [0:0] _zz_553; + wire [3:0] _zz_554; + wire [0:0] _zz_555; + wire [1:0] _zz_556; + wire [4:0] _zz_557; + wire [4:0] _zz_558; + wire _zz_559; + wire [0:0] _zz_560; + wire [9:0] _zz_561; + wire [31:0] _zz_562; + wire [31:0] _zz_563; + wire [31:0] _zz_564; + wire _zz_565; + wire [0:0] _zz_566; + wire [1:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire _zz_570; + wire _zz_571; + wire _zz_572; + wire [0:0] _zz_573; + wire [2:0] _zz_574; + wire [0:0] _zz_575; + wire [3:0] _zz_576; + wire [6:0] _zz_577; + wire [6:0] _zz_578; + wire _zz_579; + wire [0:0] _zz_580; + wire [7:0] _zz_581; + wire [31:0] _zz_582; + wire [31:0] _zz_583; + wire [31:0] _zz_584; + wire _zz_585; + wire _zz_586; + wire [31:0] _zz_587; + wire [31:0] _zz_588; + wire [31:0] _zz_589; + wire [31:0] _zz_590; + wire [31:0] _zz_591; + wire _zz_592; + wire [0:0] _zz_593; + wire [0:0] _zz_594; + wire _zz_595; + wire [0:0] _zz_596; + wire [1:0] _zz_597; + wire [0:0] _zz_598; + wire [4:0] _zz_599; + wire [0:0] _zz_600; + wire [0:0] _zz_601; + wire [1:0] _zz_602; + wire [1:0] _zz_603; + wire _zz_604; + wire [0:0] _zz_605; + wire [5:0] _zz_606; + wire [31:0] _zz_607; + wire [31:0] _zz_608; + wire [31:0] _zz_609; + wire [31:0] _zz_610; + wire [31:0] _zz_611; + wire [31:0] _zz_612; + wire [31:0] _zz_613; + wire [31:0] _zz_614; + wire _zz_615; + wire _zz_616; + wire [31:0] _zz_617; + wire [31:0] _zz_618; + wire _zz_619; + wire [0:0] _zz_620; + wire [2:0] _zz_621; + wire [31:0] _zz_622; + wire [31:0] _zz_623; + wire _zz_624; + wire _zz_625; + wire [0:0] _zz_626; + wire [0:0] _zz_627; + wire _zz_628; + wire [0:0] _zz_629; + wire [3:0] _zz_630; + wire [31:0] _zz_631; + wire [31:0] _zz_632; + wire [31:0] _zz_633; + wire [31:0] _zz_634; + wire [31:0] _zz_635; + wire _zz_636; + wire [0:0] _zz_637; + wire [0:0] _zz_638; + wire [31:0] _zz_639; + wire [31:0] _zz_640; + wire [31:0] _zz_641; + wire [31:0] _zz_642; + wire [0:0] _zz_643; + wire [3:0] _zz_644; + wire [1:0] _zz_645; + wire [1:0] _zz_646; + wire _zz_647; + wire [0:0] _zz_648; + wire [1:0] _zz_649; + wire [31:0] _zz_650; + wire [31:0] _zz_651; + wire [31:0] _zz_652; + wire [31:0] _zz_653; + wire [31:0] _zz_654; + wire _zz_655; + wire [0:0] _zz_656; + wire [1:0] _zz_657; + wire _zz_658; + wire [0:0] _zz_659; + wire [1:0] _zz_660; + wire [2:0] _zz_661; + wire [2:0] _zz_662; + wire _zz_663; + wire _zz_664; + wire [31:0] _zz_665; + wire [31:0] _zz_666; + wire [31:0] _zz_667; + wire _zz_668; + wire [31:0] _zz_669; + wire [31:0] _zz_670; + wire [31:0] _zz_671; + wire _zz_672; + wire _zz_673; + wire [0:0] _zz_674; + wire [0:0] _zz_675; + wire [0:0] _zz_676; + wire [0:0] _zz_677; + wire _zz_678; + wire _zz_679; + wire _zz_680; + wire _zz_681; + wire [31:0] _zz_682; + wire [51:0] memory_MUL_LOW; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire execute_IS_DBUS_SHARING; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] decode_SRC2; + wire [31:0] decode_SRC1; + wire decode_SRC2_FORCE_ZERO; + wire memory_IS_SFENCE_VMA; + wire execute_IS_SFENCE_VMA; + wire decode_IS_SFENCE_VMA; + wire `BranchCtrlEnum_defaultEncoding_type _zz_1; + wire `BranchCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire decode_IS_CSR; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_18; + wire `AluCtrlEnum_defaultEncoding_type _zz_19; + wire `AluCtrlEnum_defaultEncoding_type _zz_20; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire writeBack_IS_SFENCE_VMA; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire execute_PREDICTION_HAD_BRANCHED2; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_21; + wire [31:0] execute_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_22; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_23; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_24; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_25; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_26; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_27; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_28; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_29; + wire [31:0] _zz_30; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_31; + wire [31:0] _zz_32; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_33; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_34; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] _zz_36; + wire _zz_37; + reg _zz_38; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `BranchCtrlEnum_defaultEncoding_type _zz_39; + wire `EnvCtrlEnum_defaultEncoding_type _zz_40; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_41; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_42; + wire `Src2CtrlEnum_defaultEncoding_type _zz_43; + wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire `Src1CtrlEnum_defaultEncoding_type _zz_45; + wire writeBack_IS_DBUS_SHARING; + wire memory_IS_DBUS_SHARING; + reg [31:0] _zz_46; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_AMO; + wire execute_MEMORY_LRSC; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_AMO; + wire decode_MEMORY_LRSC; + reg _zz_47; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_48; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_49; + reg [31:0] _zz_50; + reg [31:0] _zz_51; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg IBusCachedPlugin_mmuBus_rsp_isPaging; + reg IBusCachedPlugin_mmuBus_rsp_allowRead; + reg IBusCachedPlugin_mmuBus_rsp_allowWrite; + reg IBusCachedPlugin_mmuBus_rsp_allowExecute; + reg IBusCachedPlugin_mmuBus_rsp_exception; + reg IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + reg DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg DBusCachedPlugin_mmuBus_rsp_isPaging; + reg DBusCachedPlugin_mmuBus_rsp_allowRead; + reg DBusCachedPlugin_mmuBus_rsp_allowWrite; + reg DBusCachedPlugin_mmuBus_rsp_allowExecute; + reg DBusCachedPlugin_mmuBus_rsp_exception; + reg DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_52; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + reg CsrPlugin_redoInterface_valid; + wire [31:0] CsrPlugin_redoInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg MmuPlugin_dBusAccess_cmd_valid; + reg MmuPlugin_dBusAccess_cmd_ready; + reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; + wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size; + wire MmuPlugin_dBusAccess_cmd_payload_write; + wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data; + wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask; + wire MmuPlugin_dBusAccess_rsp_valid; + wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data; + wire MmuPlugin_dBusAccess_rsp_payload_error; + wire MmuPlugin_dBusAccess_rsp_payload_redo; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [4:0] _zz_53; + wire [4:0] _zz_54; + wire _zz_55; + wire _zz_56; + wire _zz_57; + wire _zz_58; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_59; + wire _zz_60; + wire _zz_61; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_62; + wire _zz_63; + reg _zz_64; + wire _zz_65; + reg _zz_66; + reg [31:0] _zz_67; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_68; + reg [18:0] _zz_69; + wire _zz_70; + reg [10:0] _zz_71; + wire _zz_72; + reg [18:0] _zz_73; + reg _zz_74; + wire _zz_75; + reg [10:0] _zz_76; + wire _zz_77; + reg [18:0] _zz_78; + wire [31:0] _zz_79; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + reg dBus_rsp_regNext_valid; + reg dBus_rsp_regNext_payload_last; + reg [31:0] dBus_rsp_regNext_payload_data; + reg dBus_rsp_regNext_payload_error; + wire [31:0] _zz_80; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_81; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_82; + reg [31:0] _zz_83; + wire _zz_84; + reg [31:0] _zz_85; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + reg DBusCachedPlugin_forceDatapath; + wire [35:0] _zz_86; + wire _zz_87; + wire _zz_88; + wire _zz_89; + wire _zz_90; + wire _zz_91; + wire _zz_92; + wire `Src1CtrlEnum_defaultEncoding_type _zz_93; + wire `AluCtrlEnum_defaultEncoding_type _zz_94; + wire `Src2CtrlEnum_defaultEncoding_type _zz_95; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_96; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_97; + wire `EnvCtrlEnum_defaultEncoding_type _zz_98; + wire `BranchCtrlEnum_defaultEncoding_type _zz_99; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_100; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_101; + reg [31:0] _zz_102; + wire _zz_103; + reg [19:0] _zz_104; + wire _zz_105; + reg [19:0] _zz_106; + reg [31:0] _zz_107; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_108; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_109; + reg _zz_110; + reg _zz_111; + reg _zz_112; + reg [4:0] _zz_113; + reg [31:0] _zz_114; + wire _zz_115; + wire _zz_116; + wire _zz_117; + wire _zz_118; + wire _zz_119; + wire _zz_120; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire [31:0] _zz_121; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [31:0] _zz_122; + wire _zz_123; + wire _zz_124; + reg [32:0] _zz_125; + reg [1:0] _zz_126; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg CsrPlugin_medeleg_IAM; + reg CsrPlugin_medeleg_IAF; + reg CsrPlugin_medeleg_II; + reg CsrPlugin_medeleg_LAM; + reg CsrPlugin_medeleg_LAF; + reg CsrPlugin_medeleg_SAM; + reg CsrPlugin_medeleg_SAF; + reg CsrPlugin_medeleg_EU; + reg CsrPlugin_medeleg_ES; + reg CsrPlugin_medeleg_IPF; + reg CsrPlugin_medeleg_LPF; + reg CsrPlugin_medeleg_SPF; + reg CsrPlugin_mideleg_ST; + reg CsrPlugin_mideleg_SE; + reg CsrPlugin_mideleg_SS; + reg CsrPlugin_sstatus_SIE; + reg CsrPlugin_sstatus_SPIE; + reg [0:0] CsrPlugin_sstatus_SPP; + reg CsrPlugin_sip_SEIP_SOFT; + reg CsrPlugin_sip_SEIP_INPUT; + wire CsrPlugin_sip_SEIP_OR; + reg CsrPlugin_sip_STIP; + reg CsrPlugin_sip_SSIP; + reg CsrPlugin_sie_SEIE; + reg CsrPlugin_sie_STIE; + reg CsrPlugin_sie_SSIE; + reg [1:0] CsrPlugin_stvec_mode; + reg [29:0] CsrPlugin_stvec_base; + reg [31:0] CsrPlugin_sscratch; + reg CsrPlugin_scause_interrupt; + reg [3:0] CsrPlugin_scause_exceptionCode; + reg [31:0] CsrPlugin_stval; + reg [31:0] CsrPlugin_sepc; + reg [21:0] CsrPlugin_satp_PPN; + reg [8:0] CsrPlugin_satp_ASID; + reg [0:0] CsrPlugin_satp_MODE; + wire _zz_127; + wire _zz_128; + wire _zz_129; + wire _zz_130; + wire _zz_131; + wire _zz_132; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_133; + wire _zz_134; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + reg [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_135; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_136; + reg _zz_137; + reg _zz_138; + wire _zz_139; + reg [19:0] _zz_140; + wire _zz_141; + reg [10:0] _zz_142; + wire _zz_143; + reg [18:0] _zz_144; + reg _zz_145; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_146; + reg [19:0] _zz_147; + wire _zz_148; + reg [10:0] _zz_149; + wire _zz_150; + reg [18:0] _zz_151; + wire [31:0] execute_BranchPlugin_branchAdder; + reg MmuPlugin_status_sum; + reg MmuPlugin_status_mxr; + reg MmuPlugin_status_mprv; + reg MmuPlugin_satp_mode; + reg [8:0] MmuPlugin_satp_asid; + reg [19:0] MmuPlugin_satp_ppn; + reg MmuPlugin_ports_0_cache_0_valid; + reg MmuPlugin_ports_0_cache_0_exception; + reg MmuPlugin_ports_0_cache_0_superPage; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1; + reg MmuPlugin_ports_0_cache_0_allowRead; + reg MmuPlugin_ports_0_cache_0_allowWrite; + reg MmuPlugin_ports_0_cache_0_allowExecute; + reg MmuPlugin_ports_0_cache_0_allowUser; + reg MmuPlugin_ports_0_cache_1_valid; + reg MmuPlugin_ports_0_cache_1_exception; + reg MmuPlugin_ports_0_cache_1_superPage; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1; + reg MmuPlugin_ports_0_cache_1_allowRead; + reg MmuPlugin_ports_0_cache_1_allowWrite; + reg MmuPlugin_ports_0_cache_1_allowExecute; + reg MmuPlugin_ports_0_cache_1_allowUser; + reg MmuPlugin_ports_0_cache_2_valid; + reg MmuPlugin_ports_0_cache_2_exception; + reg MmuPlugin_ports_0_cache_2_superPage; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1; + reg MmuPlugin_ports_0_cache_2_allowRead; + reg MmuPlugin_ports_0_cache_2_allowWrite; + reg MmuPlugin_ports_0_cache_2_allowExecute; + reg MmuPlugin_ports_0_cache_2_allowUser; + reg MmuPlugin_ports_0_cache_3_valid; + reg MmuPlugin_ports_0_cache_3_exception; + reg MmuPlugin_ports_0_cache_3_superPage; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1; + reg MmuPlugin_ports_0_cache_3_allowRead; + reg MmuPlugin_ports_0_cache_3_allowWrite; + reg MmuPlugin_ports_0_cache_3_allowExecute; + reg MmuPlugin_ports_0_cache_3_allowUser; + wire MmuPlugin_ports_0_dirty; + reg MmuPlugin_ports_0_requireMmuLockupCalc; + reg [3:0] MmuPlugin_ports_0_cacheHitsCalc; + wire MmuPlugin_ports_0_cacheHit; + wire _zz_152; + wire _zz_153; + wire _zz_154; + wire [1:0] _zz_155; + wire MmuPlugin_ports_0_cacheLine_valid; + wire MmuPlugin_ports_0_cacheLine_exception; + wire MmuPlugin_ports_0_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_0_cacheLine_allowRead; + wire MmuPlugin_ports_0_cacheLine_allowWrite; + wire MmuPlugin_ports_0_cacheLine_allowExecute; + wire MmuPlugin_ports_0_cacheLine_allowUser; + reg MmuPlugin_ports_0_entryToReplace_willIncrement; + wire MmuPlugin_ports_0_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_0_entryToReplace_value; + wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_0_entryToReplace_willOverflow; + reg MmuPlugin_ports_1_cache_0_valid; + reg MmuPlugin_ports_1_cache_0_exception; + reg MmuPlugin_ports_1_cache_0_superPage; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1; + reg MmuPlugin_ports_1_cache_0_allowRead; + reg MmuPlugin_ports_1_cache_0_allowWrite; + reg MmuPlugin_ports_1_cache_0_allowExecute; + reg MmuPlugin_ports_1_cache_0_allowUser; + reg MmuPlugin_ports_1_cache_1_valid; + reg MmuPlugin_ports_1_cache_1_exception; + reg MmuPlugin_ports_1_cache_1_superPage; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1; + reg MmuPlugin_ports_1_cache_1_allowRead; + reg MmuPlugin_ports_1_cache_1_allowWrite; + reg MmuPlugin_ports_1_cache_1_allowExecute; + reg MmuPlugin_ports_1_cache_1_allowUser; + reg MmuPlugin_ports_1_cache_2_valid; + reg MmuPlugin_ports_1_cache_2_exception; + reg MmuPlugin_ports_1_cache_2_superPage; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1; + reg MmuPlugin_ports_1_cache_2_allowRead; + reg MmuPlugin_ports_1_cache_2_allowWrite; + reg MmuPlugin_ports_1_cache_2_allowExecute; + reg MmuPlugin_ports_1_cache_2_allowUser; + reg MmuPlugin_ports_1_cache_3_valid; + reg MmuPlugin_ports_1_cache_3_exception; + reg MmuPlugin_ports_1_cache_3_superPage; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1; + reg MmuPlugin_ports_1_cache_3_allowRead; + reg MmuPlugin_ports_1_cache_3_allowWrite; + reg MmuPlugin_ports_1_cache_3_allowExecute; + reg MmuPlugin_ports_1_cache_3_allowUser; + wire MmuPlugin_ports_1_dirty; + reg MmuPlugin_ports_1_requireMmuLockupCalc; + reg [3:0] MmuPlugin_ports_1_cacheHitsCalc; + wire MmuPlugin_ports_1_cacheHit; + wire _zz_156; + wire _zz_157; + wire _zz_158; + wire [1:0] _zz_159; + wire MmuPlugin_ports_1_cacheLine_valid; + wire MmuPlugin_ports_1_cacheLine_exception; + wire MmuPlugin_ports_1_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_1_cacheLine_allowRead; + wire MmuPlugin_ports_1_cacheLine_allowWrite; + wire MmuPlugin_ports_1_cacheLine_allowExecute; + wire MmuPlugin_ports_1_cacheLine_allowUser; + reg MmuPlugin_ports_1_entryToReplace_willIncrement; + wire MmuPlugin_ports_1_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_1_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_1_entryToReplace_value; + wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_1_entryToReplace_willOverflow; + reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1; + reg [9:0] MmuPlugin_shared_vpn_0; + reg [9:0] MmuPlugin_shared_vpn_1; + reg [1:0] MmuPlugin_shared_portSortedOh; + reg MmuPlugin_shared_dBusRspStaged_valid; + reg [31:0] MmuPlugin_shared_dBusRspStaged_payload_data; + reg MmuPlugin_shared_dBusRspStaged_payload_error; + reg MmuPlugin_shared_dBusRspStaged_payload_redo; + wire MmuPlugin_shared_dBusRsp_pte_V; + wire MmuPlugin_shared_dBusRsp_pte_R; + wire MmuPlugin_shared_dBusRsp_pte_W; + wire MmuPlugin_shared_dBusRsp_pte_X; + wire MmuPlugin_shared_dBusRsp_pte_U; + wire MmuPlugin_shared_dBusRsp_pte_G; + wire MmuPlugin_shared_dBusRsp_pte_A; + wire MmuPlugin_shared_dBusRsp_pte_D; + wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW; + wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0; + wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; + wire MmuPlugin_shared_dBusRsp_exception; + wire MmuPlugin_shared_dBusRsp_leaf; + reg MmuPlugin_shared_pteBuffer_V; + reg MmuPlugin_shared_pteBuffer_R; + reg MmuPlugin_shared_pteBuffer_W; + reg MmuPlugin_shared_pteBuffer_X; + reg MmuPlugin_shared_pteBuffer_U; + reg MmuPlugin_shared_pteBuffer_G; + reg MmuPlugin_shared_pteBuffer_A; + reg MmuPlugin_shared_pteBuffer_D; + reg [1:0] MmuPlugin_shared_pteBuffer_RSW; + reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; + reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; + reg [1:0] _zz_160; + wire [1:0] _zz_161; + reg [1:0] _zz_162; + wire [1:0] MmuPlugin_shared_refills; + wire [1:0] _zz_163; + reg [1:0] _zz_164; + wire [31:0] _zz_165; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_LRSC; + reg decode_to_execute_MEMORY_AMO; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_SFENCE_VMA; + reg execute_to_memory_IS_SFENCE_VMA; + reg memory_to_writeBack_IS_SFENCE_VMA; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg [31:0] decode_to_execute_SRC1; + reg [31:0] decode_to_execute_SRC2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_IS_DBUS_SHARING; + reg memory_to_writeBack_IS_DBUS_SHARING; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [2:0] _zz_166; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_770; + reg execute_CsrPlugin_csr_771; + reg execute_CsrPlugin_csr_256; + reg execute_CsrPlugin_csr_324; + reg execute_CsrPlugin_csr_260; + reg execute_CsrPlugin_csr_261; + reg execute_CsrPlugin_csr_321; + reg execute_CsrPlugin_csr_320; + reg execute_CsrPlugin_csr_322; + reg execute_CsrPlugin_csr_323; + reg execute_CsrPlugin_csr_384; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + `ifndef SYNTHESIS + reg [31:0] _zz_1_string; + reg [31:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_7_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; + reg [39:0] _zz_17_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_18_string; + reg [63:0] _zz_19_string; + reg [63:0] _zz_20_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_21_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_22_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_23_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_24_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_27_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_28_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_31_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_33_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_34_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_35_string; + reg [31:0] _zz_39_string; + reg [39:0] _zz_40_string; + reg [71:0] _zz_41_string; + reg [39:0] _zz_42_string; + reg [23:0] _zz_43_string; + reg [63:0] _zz_44_string; + reg [95:0] _zz_45_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_48_string; + reg [95:0] _zz_93_string; + reg [63:0] _zz_94_string; + reg [23:0] _zz_95_string; + reg [39:0] _zz_96_string; + reg [71:0] _zz_97_string; + reg [39:0] _zz_98_string; + reg [31:0] _zz_99_string; + reg [47:0] MmuPlugin_shared_state_1_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_246 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_247 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_248 = 1'b1; + assign _zz_249 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_250 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_251 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_252 = ((_zz_191 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_253 = ((_zz_191 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_254 = ((_zz_191 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_255 = ((_zz_191 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_256 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_257 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_258 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_259 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_260 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_261 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_262 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_264 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign _zz_265 = (! dataCache_1_io_cpu_execute_refilling); + assign _zz_266 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_267 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_268 = (1'b0 || (! 1'b1)); + assign _zz_269 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_270 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_271 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_272 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_273 = execute_INSTRUCTION[13 : 12]; + assign _zz_274 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_275 = (! memory_arbitration_isStuck); + assign _zz_276 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_277 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_278 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_279 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_280 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign _zz_281 = MmuPlugin_shared_portSortedOh[0]; + assign _zz_282 = MmuPlugin_shared_portSortedOh[1]; + assign _zz_283 = (_zz_220 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_284 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); + assign _zz_285 = ((_zz_127 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); + assign _zz_286 = ((_zz_128 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); + assign _zz_287 = ((_zz_129 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); + assign _zz_288 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_289 = ((_zz_127 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); + assign _zz_290 = ((_zz_128 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); + assign _zz_291 = ((_zz_129 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); + assign _zz_292 = ((_zz_130 && 1'b1) && (! 1'b0)); + assign _zz_293 = ((_zz_131 && 1'b1) && (! 1'b0)); + assign _zz_294 = ((_zz_132 && 1'b1) && (! 1'b0)); + assign _zz_295 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_296 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign _zz_297 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign _zz_298 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign _zz_299 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign _zz_300 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); + assign _zz_301 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); + assign _zz_302 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); + assign _zz_303 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign _zz_304 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_305 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_306 = execute_INSTRUCTION[13]; + assign _zz_307 = ($signed(_zz_308) + $signed(_zz_313)); + assign _zz_308 = ($signed(_zz_309) + $signed(_zz_311)); + assign _zz_309 = 52'h0; + assign _zz_310 = {1'b0,memory_MUL_LL}; + assign _zz_311 = {{19{_zz_310[32]}}, _zz_310}; + assign _zz_312 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_313 = {{2{_zz_312[49]}}, _zz_312}; + assign _zz_314 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_315 = {{2{_zz_314[49]}}, _zz_314}; + assign _zz_316 = ($signed(_zz_318) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_317 = _zz_316[31 : 0]; + assign _zz_318 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_319 = _zz_86[35 : 35]; + assign _zz_320 = _zz_86[29 : 29]; + assign _zz_321 = _zz_86[28 : 28]; + assign _zz_322 = _zz_86[27 : 27]; + assign _zz_323 = _zz_86[26 : 26]; + assign _zz_324 = _zz_86[25 : 25]; + assign _zz_325 = _zz_86[20 : 20]; + assign _zz_326 = _zz_86[19 : 19]; + assign _zz_327 = _zz_86[13 : 13]; + assign _zz_328 = _zz_86[12 : 12]; + assign _zz_329 = _zz_86[11 : 11]; + assign _zz_330 = _zz_86[32 : 32]; + assign _zz_331 = _zz_86[17 : 17]; + assign _zz_332 = _zz_86[5 : 5]; + assign _zz_333 = _zz_86[3 : 3]; + assign _zz_334 = _zz_86[18 : 18]; + assign _zz_335 = _zz_86[10 : 10]; + assign _zz_336 = _zz_86[16 : 16]; + assign _zz_337 = _zz_86[15 : 15]; + assign _zz_338 = _zz_86[4 : 4]; + assign _zz_339 = _zz_86[0 : 0]; + assign _zz_340 = (_zz_53 - 5'h01); + assign _zz_341 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_342 = {29'd0, _zz_341}; + assign _zz_343 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_344 = {{_zz_69,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_345 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_346 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_347 = {{_zz_71,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_348 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_349 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_350 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_351 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_352 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_353 = execute_SRC_LESS; + assign _zz_354 = 3'b100; + assign _zz_355 = decode_INSTRUCTION[19 : 15]; + assign _zz_356 = decode_INSTRUCTION[31 : 20]; + assign _zz_357 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_358 = ($signed(_zz_359) + $signed(_zz_362)); + assign _zz_359 = ($signed(_zz_360) + $signed(_zz_361)); + assign _zz_360 = execute_SRC1; + assign _zz_361 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_362 = (execute_SRC_USE_SUB_LESS ? _zz_363 : _zz_364); + assign _zz_363 = 32'h00000001; + assign _zz_364 = 32'h0; + assign _zz_365 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_366 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_367 = writeBack_MUL_LOW[31 : 0]; + assign _zz_368 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_369 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_370 = {5'd0, _zz_369}; + assign _zz_371 = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_372 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_373 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_374 = {_zz_121,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_375 = _zz_376; + assign _zz_376 = _zz_377; + assign _zz_377 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_122) : _zz_122)} + _zz_379); + assign _zz_378 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_379 = {32'd0, _zz_378}; + assign _zz_380 = _zz_124; + assign _zz_381 = {32'd0, _zz_380}; + assign _zz_382 = _zz_123; + assign _zz_383 = {31'd0, _zz_382}; + assign _zz_384 = (_zz_133 & (~ _zz_385)); + assign _zz_385 = (_zz_133 - 2'b01); + assign _zz_386 = execute_INSTRUCTION[31 : 20]; + assign _zz_387 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_388 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_389 = {_zz_140,execute_INSTRUCTION[31 : 20]}; + assign _zz_390 = {{_zz_142,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_391 = {{_zz_144,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_392 = execute_INSTRUCTION[31 : 20]; + assign _zz_393 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_394 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_395 = 3'b100; + assign _zz_396 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_397 = {1'd0, _zz_396}; + assign _zz_398 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_399 = {1'd0, _zz_398}; + assign _zz_400 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; + assign _zz_401 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; + assign _zz_402 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; + assign _zz_403 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; + assign _zz_404 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; + assign _zz_405 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; + assign _zz_406 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; + assign _zz_407 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; + assign _zz_408 = (_zz_162 - 2'b01); + assign _zz_409 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_410 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_411 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_412 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_413 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_414 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_415 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_416 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_417 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_418 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_419 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_420 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_421 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_422 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_423 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_424 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_425 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_426 = execute_CsrPlugin_writeData[0 : 0]; + assign _zz_427 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_428 = execute_CsrPlugin_writeData[2 : 2]; + assign _zz_429 = execute_CsrPlugin_writeData[4 : 4]; + assign _zz_430 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_431 = execute_CsrPlugin_writeData[6 : 6]; + assign _zz_432 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_433 = execute_CsrPlugin_writeData[8 : 8]; + assign _zz_434 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_435 = execute_CsrPlugin_writeData[12 : 12]; + assign _zz_436 = execute_CsrPlugin_writeData[13 : 13]; + assign _zz_437 = execute_CsrPlugin_writeData[15 : 15]; + assign _zz_438 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_439 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_440 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_441 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_442 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_443 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_444 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_445 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_446 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_447 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_448 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_449 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_450 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_451 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_452 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_453 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_454 = 1'b1; + assign _zz_455 = 1'b1; + assign _zz_456 = {_zz_56,{_zz_58,_zz_57}}; + assign _zz_457 = 32'h0000107f; + assign _zz_458 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_459 = 32'h00002073; + assign _zz_460 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_461 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_462 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_463) == 32'h00000003),{(_zz_464 == _zz_465),{_zz_466,{_zz_467,_zz_468}}}}}}; + assign _zz_463 = 32'h0000505f; + assign _zz_464 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_465 = 32'h00000063; + assign _zz_466 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_467 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); + assign _zz_468 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_469) == 32'h0000500f),{(_zz_470 == _zz_471),{_zz_472,{_zz_473,_zz_474}}}}}}; + assign _zz_469 = 32'h01f0707f; + assign _zz_470 = (decode_INSTRUCTION & 32'hbc00707f); + assign _zz_471 = 32'h00005013; + assign _zz_472 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); + assign _zz_473 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_474 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_475) == 32'h12000073),{(_zz_476 == _zz_477),{_zz_478,_zz_479}}}}}; + assign _zz_475 = 32'hfe007fff; + assign _zz_476 = (decode_INSTRUCTION & 32'hdfffffff); + assign _zz_477 = 32'h10200073; + assign _zz_478 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); + assign _zz_479 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_480 = decode_INSTRUCTION[31]; + assign _zz_481 = decode_INSTRUCTION[31]; + assign _zz_482 = decode_INSTRUCTION[7]; + assign _zz_483 = 32'h02003050; + assign _zz_484 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_485 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_486 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00100050); + assign _zz_487 = 1'b0; + assign _zz_488 = ({(_zz_491 == _zz_492),(_zz_493 == _zz_494)} != 2'b00); + assign _zz_489 = ((_zz_495 == _zz_496) != 1'b0); + assign _zz_490 = {({_zz_497,_zz_498} != 2'b00),{(_zz_499 != _zz_500),{_zz_501,{_zz_502,_zz_503}}}}; + assign _zz_491 = (decode_INSTRUCTION & 32'h10103050); + assign _zz_492 = 32'h00000050; + assign _zz_493 = (decode_INSTRUCTION & 32'h12203050); + assign _zz_494 = 32'h10000050; + assign _zz_495 = (decode_INSTRUCTION & 32'h02103050); + assign _zz_496 = 32'h00000050; + assign _zz_497 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_498 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_499 = _zz_92; + assign _zz_500 = 1'b0; + assign _zz_501 = (_zz_92 != 1'b0); + assign _zz_502 = ((_zz_504 == _zz_505) != 1'b0); + assign _zz_503 = {(_zz_506 != 1'b0),{(_zz_507 != _zz_508),{_zz_509,{_zz_510,_zz_511}}}}; + assign _zz_504 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_505 = 32'h02004020; + assign _zz_506 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_507 = {(_zz_512 == _zz_513),(_zz_514 == _zz_515)}; + assign _zz_508 = 2'b00; + assign _zz_509 = ({_zz_516,{_zz_517,_zz_518}} != 3'b000); + assign _zz_510 = (_zz_519 != 1'b0); + assign _zz_511 = {(_zz_520 != _zz_521),{_zz_522,{_zz_523,_zz_524}}}; + assign _zz_512 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_513 = 32'h00005010; + assign _zz_514 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_515 = 32'h00005020; + assign _zz_516 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_517 = ((decode_INSTRUCTION & _zz_525) == 32'h00001010); + assign _zz_518 = ((decode_INSTRUCTION & _zz_526) == 32'h00001010); + assign _zz_519 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_520 = ((decode_INSTRUCTION & _zz_527) == 32'h00002000); + assign _zz_521 = 1'b0; + assign _zz_522 = ({_zz_528,_zz_529} != 2'b00); + assign _zz_523 = (_zz_530 != 1'b0); + assign _zz_524 = {(_zz_531 != _zz_532),{_zz_533,{_zz_534,_zz_535}}}; + assign _zz_525 = 32'h00007034; + assign _zz_526 = 32'h02007054; + assign _zz_527 = 32'h00003000; + assign _zz_528 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_529 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_530 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz_531 = ((decode_INSTRUCTION & _zz_536) == 32'h00000024); + assign _zz_532 = 1'b0; + assign _zz_533 = ({_zz_537,{_zz_538,_zz_539}} != 4'b0000); + assign _zz_534 = (_zz_540 != 1'b0); + assign _zz_535 = {(_zz_541 != _zz_542),{_zz_543,{_zz_544,_zz_545}}}; + assign _zz_536 = 32'h00000064; + assign _zz_537 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_538 = ((decode_INSTRUCTION & _zz_546) == 32'h00000020); + assign _zz_539 = {(_zz_547 == _zz_548),(_zz_549 == _zz_550)}; + assign _zz_540 = ((decode_INSTRUCTION & 32'h10000008) == 32'h00000008); + assign _zz_541 = ((decode_INSTRUCTION & _zz_551) == 32'h10000008); + assign _zz_542 = 1'b0; + assign _zz_543 = ({_zz_552,{_zz_553,_zz_554}} != 6'h0); + assign _zz_544 = ({_zz_555,_zz_556} != 3'b000); + assign _zz_545 = {(_zz_557 != _zz_558),{_zz_559,{_zz_560,_zz_561}}}; + assign _zz_546 = 32'h00000064; + assign _zz_547 = (decode_INSTRUCTION & 32'h08000070); + assign _zz_548 = 32'h08000020; + assign _zz_549 = (decode_INSTRUCTION & 32'h10000070); + assign _zz_550 = 32'h00000020; + assign _zz_551 = 32'h10000008; + assign _zz_552 = ((decode_INSTRUCTION & _zz_562) == 32'h00002040); + assign _zz_553 = (_zz_563 == _zz_564); + assign _zz_554 = {_zz_565,{_zz_566,_zz_567}}; + assign _zz_555 = (_zz_568 == _zz_569); + assign _zz_556 = {_zz_570,_zz_571}; + assign _zz_557 = {_zz_572,{_zz_573,_zz_574}}; + assign _zz_558 = 5'h0; + assign _zz_559 = ({_zz_575,_zz_576} != 5'h0); + assign _zz_560 = (_zz_577 != _zz_578); + assign _zz_561 = {_zz_579,{_zz_580,_zz_581}}; + assign _zz_562 = 32'h00002040; + assign _zz_563 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_564 = 32'h00001040; + assign _zz_565 = ((decode_INSTRUCTION & _zz_582) == 32'h00000040); + assign _zz_566 = (_zz_583 == _zz_584); + assign _zz_567 = {_zz_585,_zz_586}; + assign _zz_568 = (decode_INSTRUCTION & 32'h08000020); + assign _zz_569 = 32'h08000020; + assign _zz_570 = ((decode_INSTRUCTION & _zz_587) == 32'h00000020); + assign _zz_571 = ((decode_INSTRUCTION & _zz_588) == 32'h00000020); + assign _zz_572 = ((decode_INSTRUCTION & _zz_589) == 32'h00000040); + assign _zz_573 = (_zz_590 == _zz_591); + assign _zz_574 = {_zz_592,{_zz_593,_zz_594}}; + assign _zz_575 = _zz_91; + assign _zz_576 = {_zz_595,{_zz_596,_zz_597}}; + assign _zz_577 = {_zz_88,{_zz_598,_zz_599}}; + assign _zz_578 = 7'h0; + assign _zz_579 = ({_zz_600,_zz_601} != 2'b00); + assign _zz_580 = (_zz_602 != _zz_603); + assign _zz_581 = {_zz_604,{_zz_605,_zz_606}}; + assign _zz_582 = 32'h00000050; + assign _zz_583 = (decode_INSTRUCTION & 32'h02100040); + assign _zz_584 = 32'h00000040; + assign _zz_585 = ((decode_INSTRUCTION & _zz_607) == 32'h0); + assign _zz_586 = ((decode_INSTRUCTION & _zz_608) == 32'h10002008); + assign _zz_587 = 32'h10000020; + assign _zz_588 = 32'h00000028; + assign _zz_589 = 32'h00000040; + assign _zz_590 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_591 = 32'h00004020; + assign _zz_592 = ((decode_INSTRUCTION & _zz_609) == 32'h00000010); + assign _zz_593 = _zz_91; + assign _zz_594 = (_zz_610 == _zz_611); + assign _zz_595 = ((decode_INSTRUCTION & _zz_612) == 32'h00002010); + assign _zz_596 = (_zz_613 == _zz_614); + assign _zz_597 = {_zz_615,_zz_616}; + assign _zz_598 = (_zz_617 == _zz_618); + assign _zz_599 = {_zz_619,{_zz_620,_zz_621}}; + assign _zz_600 = _zz_90; + assign _zz_601 = (_zz_622 == _zz_623); + assign _zz_602 = {_zz_90,_zz_624}; + assign _zz_603 = 2'b00; + assign _zz_604 = (_zz_625 != 1'b0); + assign _zz_605 = (_zz_626 != _zz_627); + assign _zz_606 = {_zz_628,{_zz_629,_zz_630}}; + assign _zz_607 = 32'h00000038; + assign _zz_608 = 32'h18002008; + assign _zz_609 = 32'h00000030; + assign _zz_610 = (decode_INSTRUCTION & 32'h02000028); + assign _zz_611 = 32'h00000020; + assign _zz_612 = 32'h00002030; + assign _zz_613 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_614 = 32'h00000010; + assign _zz_615 = ((decode_INSTRUCTION & _zz_631) == 32'h00000020); + assign _zz_616 = ((decode_INSTRUCTION & _zz_632) == 32'h00002020); + assign _zz_617 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_618 = 32'h00001010; + assign _zz_619 = ((decode_INSTRUCTION & _zz_633) == 32'h00002010); + assign _zz_620 = (_zz_634 == _zz_635); + assign _zz_621 = {_zz_636,{_zz_637,_zz_638}}; + assign _zz_622 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_623 = 32'h00000020; + assign _zz_624 = ((decode_INSTRUCTION & _zz_639) == 32'h0); + assign _zz_625 = ((decode_INSTRUCTION & _zz_640) == 32'h00004010); + assign _zz_626 = (_zz_641 == _zz_642); + assign _zz_627 = 1'b0; + assign _zz_628 = ({_zz_643,_zz_644} != 5'h0); + assign _zz_629 = (_zz_645 != _zz_646); + assign _zz_630 = {_zz_647,{_zz_648,_zz_649}}; + assign _zz_631 = 32'h02003020; + assign _zz_632 = 32'h02002068; + assign _zz_633 = 32'h00002010; + assign _zz_634 = (decode_INSTRUCTION & 32'h00002008); + assign _zz_635 = 32'h00002008; + assign _zz_636 = ((decode_INSTRUCTION & _zz_650) == 32'h00000010); + assign _zz_637 = _zz_91; + assign _zz_638 = (_zz_651 == _zz_652); + assign _zz_639 = 32'h00000020; + assign _zz_640 = 32'h00004014; + assign _zz_641 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_642 = 32'h00002010; + assign _zz_643 = (_zz_653 == _zz_654); + assign _zz_644 = {_zz_655,{_zz_656,_zz_657}}; + assign _zz_645 = {_zz_89,_zz_658}; + assign _zz_646 = 2'b00; + assign _zz_647 = ({_zz_659,_zz_660} != 3'b000); + assign _zz_648 = (_zz_661 != _zz_662); + assign _zz_649 = {_zz_663,_zz_664}; + assign _zz_650 = 32'h00000050; + assign _zz_651 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_652 = 32'h0; + assign _zz_653 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_654 = 32'h0; + assign _zz_655 = ((decode_INSTRUCTION & _zz_665) == 32'h0); + assign _zz_656 = (_zz_666 == _zz_667); + assign _zz_657 = {_zz_668,_zz_89}; + assign _zz_658 = ((decode_INSTRUCTION & _zz_669) == 32'h0); + assign _zz_659 = (_zz_670 == _zz_671); + assign _zz_660 = {_zz_672,_zz_673}; + assign _zz_661 = {_zz_88,{_zz_674,_zz_675}}; + assign _zz_662 = 3'b000; + assign _zz_663 = ({_zz_676,_zz_677} != 2'b00); + assign _zz_664 = (_zz_678 != 1'b0); + assign _zz_665 = 32'h00000018; + assign _zz_666 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_667 = 32'h00002000; + assign _zz_668 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_669 = 32'h00000058; + assign _zz_670 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_671 = 32'h00000040; + assign _zz_672 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_673 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_674 = _zz_87; + assign _zz_675 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00000004); + assign _zz_676 = _zz_87; + assign _zz_677 = ((decode_INSTRUCTION & 32'h0000004c) == 32'h00000004); + assign _zz_678 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_679 = execute_INSTRUCTION[31]; + assign _zz_680 = execute_INSTRUCTION[31]; + assign _zz_681 = execute_INSTRUCTION[7]; + assign _zz_682 = 32'h0; + initial begin + $readmemb("VexRiscv.v_toplevel_RegFilePlugin_regFile.bin",RegFilePlugin_regFile); + end + always @ (posedge clk) begin + if(_zz_454) begin + _zz_221 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_455) begin + _zz_222 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_38) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_186 ), //i + .io_cpu_prefetch_isValid (_zz_187 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_188 ), //i + .io_cpu_fetch_isStuck (_zz_189 ), //i + .io_cpu_fetch_isRemoved (_zz_190 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_191 ), //i + .io_cpu_decode_isStuck (_zz_192 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_193 ), //i + .io_cpu_fill_valid (_zz_194 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_9 (_zz_166[2:0] ), //i + ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_195 ), //i + .io_cpu_execute_address (_zz_196[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (_zz_197 ), //i + .io_cpu_execute_args_data (_zz_198[31:0] ), //i + .io_cpu_execute_args_size (_zz_199[1:0] ), //i + .io_cpu_execute_args_isLrsc (_zz_200 ), //i + .io_cpu_execute_args_isAmo (_zz_201 ), //i + .io_cpu_execute_args_amoCtrl_swap (_zz_202 ), //i + .io_cpu_execute_args_amoCtrl_alu (_zz_203[2:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_204 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_205[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_206 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_writeBack_isValid (_zz_207 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_208 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_209[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_210 ), //i + .io_cpu_writeBack_fence_SR (_zz_211 ), //i + .io_cpu_writeBack_fence_SO (_zz_212 ), //i + .io_cpu_writeBack_fence_SI (_zz_213 ), //i + .io_cpu_writeBack_fence_PW (_zz_214 ), //i + .io_cpu_writeBack_fence_PR (_zz_215 ), //i + .io_cpu_writeBack_fence_PO (_zz_216 ), //i + .io_cpu_writeBack_fence_PI (_zz_217 ), //i + .io_cpu_writeBack_fence_FM (_zz_218[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_219 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_220 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_regNext_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_regNext_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_regNext_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_regNext_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_456) + 3'b000 : begin + _zz_223 = DBusCachedPlugin_redoBranch_payload; + end + 3'b001 : begin + _zz_223 = CsrPlugin_jumpInterface_payload; + end + 3'b010 : begin + _zz_223 = BranchPlugin_jumpInterface_payload; + end + 3'b011 : begin + _zz_223 = CsrPlugin_redoInterface_payload; + end + default : begin + _zz_223 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_155) + 2'b00 : begin + _zz_224 = MmuPlugin_ports_0_cache_0_valid; + _zz_225 = MmuPlugin_ports_0_cache_0_exception; + _zz_226 = MmuPlugin_ports_0_cache_0_superPage; + _zz_227 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_228 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_229 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_230 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_231 = MmuPlugin_ports_0_cache_0_allowRead; + _zz_232 = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_233 = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_234 = MmuPlugin_ports_0_cache_0_allowUser; + end + 2'b01 : begin + _zz_224 = MmuPlugin_ports_0_cache_1_valid; + _zz_225 = MmuPlugin_ports_0_cache_1_exception; + _zz_226 = MmuPlugin_ports_0_cache_1_superPage; + _zz_227 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_228 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_229 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_230 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_231 = MmuPlugin_ports_0_cache_1_allowRead; + _zz_232 = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_233 = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_234 = MmuPlugin_ports_0_cache_1_allowUser; + end + 2'b10 : begin + _zz_224 = MmuPlugin_ports_0_cache_2_valid; + _zz_225 = MmuPlugin_ports_0_cache_2_exception; + _zz_226 = MmuPlugin_ports_0_cache_2_superPage; + _zz_227 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_228 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_229 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_230 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_231 = MmuPlugin_ports_0_cache_2_allowRead; + _zz_232 = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_233 = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_234 = MmuPlugin_ports_0_cache_2_allowUser; + end + default : begin + _zz_224 = MmuPlugin_ports_0_cache_3_valid; + _zz_225 = MmuPlugin_ports_0_cache_3_exception; + _zz_226 = MmuPlugin_ports_0_cache_3_superPage; + _zz_227 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_228 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_229 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_230 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_231 = MmuPlugin_ports_0_cache_3_allowRead; + _zz_232 = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_233 = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_234 = MmuPlugin_ports_0_cache_3_allowUser; + end + endcase + end + + always @(*) begin + case(_zz_159) + 2'b00 : begin + _zz_235 = MmuPlugin_ports_1_cache_0_valid; + _zz_236 = MmuPlugin_ports_1_cache_0_exception; + _zz_237 = MmuPlugin_ports_1_cache_0_superPage; + _zz_238 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_239 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_240 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_241 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_242 = MmuPlugin_ports_1_cache_0_allowRead; + _zz_243 = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_244 = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_245 = MmuPlugin_ports_1_cache_0_allowUser; + end + 2'b01 : begin + _zz_235 = MmuPlugin_ports_1_cache_1_valid; + _zz_236 = MmuPlugin_ports_1_cache_1_exception; + _zz_237 = MmuPlugin_ports_1_cache_1_superPage; + _zz_238 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_239 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_240 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_241 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_242 = MmuPlugin_ports_1_cache_1_allowRead; + _zz_243 = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_244 = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_245 = MmuPlugin_ports_1_cache_1_allowUser; + end + 2'b10 : begin + _zz_235 = MmuPlugin_ports_1_cache_2_valid; + _zz_236 = MmuPlugin_ports_1_cache_2_exception; + _zz_237 = MmuPlugin_ports_1_cache_2_superPage; + _zz_238 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_239 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_240 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_241 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_242 = MmuPlugin_ports_1_cache_2_allowRead; + _zz_243 = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_244 = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_245 = MmuPlugin_ports_1_cache_2_allowUser; + end + default : begin + _zz_235 = MmuPlugin_ports_1_cache_3_valid; + _zz_236 = MmuPlugin_ports_1_cache_3_exception; + _zz_237 = MmuPlugin_ports_1_cache_3_superPage; + _zz_238 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_239 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_240 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_241 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_242 = MmuPlugin_ports_1_cache_3_allowRead; + _zz_243 = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_244 = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_245 = MmuPlugin_ports_1_cache_3_allowUser; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `BranchCtrlEnum_defaultEncoding_INC : _zz_1_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_1_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_1_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_1_string = "JALR"; + default : _zz_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_2) + `BranchCtrlEnum_defaultEncoding_INC : _zz_2_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_2_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_2_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_2_string = "JALR"; + default : _zz_2_string = "????"; + endcase + end + always @(*) begin + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; + endcase + end + always @(*) begin + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; + endcase + end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18_string = "BITWISE "; + default : _zz_18_string = "????????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19_string = "BITWISE "; + default : _zz_19_string = "????????"; + endcase + end + always @(*) begin + case(_zz_20) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; + default : _zz_20_string = "????????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_21) + `BranchCtrlEnum_defaultEncoding_INC : _zz_21_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_21_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_21_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_21_string = "JALR"; + default : _zz_21_string = "????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_22) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_22_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_22_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_22_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_22_string = "ECALL"; + default : _zz_22_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_23) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_23_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_23_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_23_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_23_string = "ECALL"; + default : _zz_23_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_24) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_24_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_24_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_24_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_24_string = "ECALL"; + default : _zz_24_string = "?????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_27) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_27_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_27_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_27_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_27_string = "SRA_1 "; + default : _zz_27_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_28) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_28_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_28_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_28_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_28_string = "SRA_1 "; + default : _zz_28_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_31) + `Src2CtrlEnum_defaultEncoding_RS : _zz_31_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_31_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_31_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_31_string = "PC "; + default : _zz_31_string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_33) + `Src1CtrlEnum_defaultEncoding_RS : _zz_33_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_33_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_33_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_33_string = "URS1 "; + default : _zz_33_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_34) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_34_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_34_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_34_string = "BITWISE "; + default : _zz_34_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_35) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_35_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_35_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_35_string = "AND_1"; + default : _zz_35_string = "?????"; + endcase + end + always @(*) begin + case(_zz_39) + `BranchCtrlEnum_defaultEncoding_INC : _zz_39_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_39_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_39_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_39_string = "JALR"; + default : _zz_39_string = "????"; + endcase + end + always @(*) begin + case(_zz_40) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_40_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_40_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_40_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_40_string = "ECALL"; + default : _zz_40_string = "?????"; + endcase + end + always @(*) begin + case(_zz_41) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_41_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_41_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_41_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_41_string = "SRA_1 "; + default : _zz_41_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_42) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_42_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_42_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_42_string = "AND_1"; + default : _zz_42_string = "?????"; + endcase + end + always @(*) begin + case(_zz_43) + `Src2CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_43_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_43_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_43_string = "PC "; + default : _zz_43_string = "???"; + endcase + end + always @(*) begin + case(_zz_44) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; + default : _zz_44_string = "????????"; + endcase + end + always @(*) begin + case(_zz_45) + `Src1CtrlEnum_defaultEncoding_RS : _zz_45_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_45_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_45_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_45_string = "URS1 "; + default : _zz_45_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_48) + `BranchCtrlEnum_defaultEncoding_INC : _zz_48_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_48_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_48_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_48_string = "JALR"; + default : _zz_48_string = "????"; + endcase + end + always @(*) begin + case(_zz_93) + `Src1CtrlEnum_defaultEncoding_RS : _zz_93_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_93_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_93_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_93_string = "URS1 "; + default : _zz_93_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_94) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_94_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_94_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_94_string = "BITWISE "; + default : _zz_94_string = "????????"; + endcase + end + always @(*) begin + case(_zz_95) + `Src2CtrlEnum_defaultEncoding_RS : _zz_95_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_95_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_95_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_95_string = "PC "; + default : _zz_95_string = "???"; + endcase + end + always @(*) begin + case(_zz_96) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_96_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_96_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_96_string = "AND_1"; + default : _zz_96_string = "?????"; + endcase + end + always @(*) begin + case(_zz_97) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_97_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_97_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_97_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_97_string = "SRA_1 "; + default : _zz_97_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_98) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_98_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_98_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_98_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_98_string = "ECALL"; + default : _zz_98_string = "?????"; + endcase + end + always @(*) begin + case(_zz_99) + `BranchCtrlEnum_defaultEncoding_INC : _zz_99_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_99_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_99_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_99_string = "JALR"; + default : _zz_99_string = "????"; + endcase + end + always @(*) begin + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; + default : MmuPlugin_shared_state_1_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_307) + $signed(_zz_315)); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_SHIFT_RIGHT = _zz_317; + assign execute_REGFILE_WRITE_DATA = _zz_101; + assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_196[1 : 0]; + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2 = _zz_107; + assign decode_SRC1 = _zz_102; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; + assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; + assign decode_IS_SFENCE_VMA = _zz_319[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign _zz_5 = _zz_6; + assign decode_ENV_CTRL = _zz_7; + assign _zz_8 = _zz_9; + assign decode_IS_CSR = _zz_320[0]; + assign decode_IS_RS2_SIGNED = _zz_321[0]; + assign decode_IS_RS1_SIGNED = _zz_322[0]; + assign decode_IS_DIV = _zz_323[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_324[0]; + assign _zz_10 = _zz_11; + assign decode_SHIFT_CTRL = _zz_12; + assign _zz_13 = _zz_14; + assign decode_ALU_BITWISE_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_SRC_LESS_UNSIGNED = _zz_325[0]; + assign decode_MEMORY_MANAGMENT = _zz_326[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_327[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_328[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_329[0]; + assign decode_ALU_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_47; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_BRANCH_COND_RESULT = _zz_138; + assign execute_BRANCH_CTRL = _zz_21; + assign execute_PC = decode_to_execute_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_330[0]; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_22; + assign execute_ENV_CTRL = _zz_23; + assign writeBack_ENV_CTRL = _zz_24; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_RS1 = decode_to_execute_RS1; + assign decode_RS2_USE = _zz_331[0]; + assign decode_RS1_USE = _zz_332[0]; + always @ (*) begin + _zz_25 = execute_REGFILE_WRITE_DATA; + if(_zz_246)begin + _zz_25 = execute_CsrPlugin_readData; + end + if(DBusCachedPlugin_forceDatapath)begin + _zz_25 = MmuPlugin_dBusAccess_cmd_payload_address; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_112)begin + if((_zz_113 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_114; + end + end + if(_zz_247)begin + if(_zz_248)begin + if(_zz_116)begin + decode_RS2 = _zz_46; + end + end + end + if(_zz_249)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_118)begin + decode_RS2 = _zz_26; + end + end + end + if(_zz_250)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_120)begin + decode_RS2 = _zz_25; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_112)begin + if((_zz_113 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_114; + end + end + if(_zz_247)begin + if(_zz_248)begin + if(_zz_115)begin + decode_RS1 = _zz_46; + end + end + end + if(_zz_249)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_117)begin + decode_RS1 = _zz_26; + end + end + end + if(_zz_250)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_119)begin + decode_RS1 = _zz_25; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_26 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_26 = _zz_109; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_26 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(_zz_251)begin + _zz_26 = memory_MulDivIterativePlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_27; + assign execute_SHIFT_CTRL = _zz_28; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_29 = decode_PC; + assign _zz_30 = decode_RS2; + assign decode_SRC2_CTRL = _zz_31; + assign _zz_32 = decode_RS1; + assign decode_SRC1_CTRL = _zz_33; + assign decode_SRC_USE_SUB_LESS = _zz_333[0]; + assign decode_SRC_ADD_ZERO = _zz_334[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_34; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_35; + assign _zz_36 = writeBack_INSTRUCTION; + assign _zz_37 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_38 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_38 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_335[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_457) == 32'h00001073),{(_zz_458 == _zz_459),{_zz_460,{_zz_461,_zz_462}}}}}}} != 25'h0); + assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; + assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; + always @ (*) begin + _zz_46 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_46 = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_305) + 2'b00 : begin + _zz_46 = _zz_367; + end + default : begin + _zz_46 = _zz_368; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO; + assign execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_AMO = _zz_336[0]; + assign decode_MEMORY_LRSC = _zz_337[0]; + assign decode_MEMORY_ENABLE = _zz_338[0]; + assign decode_FLUSH_ALL = _zz_339[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_252)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_253)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_254)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_255)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_48; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_49 = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_49 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_50 = execute_FORMAL_PC_NEXT; + if(CsrPlugin_redoInterface_valid)begin + _zz_50 = CsrPlugin_redoInterface_payload; + end + end + + always @ (*) begin + _zz_51 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_51 = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + case(_zz_166) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid)begin + decode_arbitration_haltByOther = 1'b1; + end + if((decode_arbitration_isValid && (_zz_110 || _zz_111)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_256)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_256)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((_zz_219 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_257)begin + if((! execute_CsrPlugin_wfiWake))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_246)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_258)begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushIt = 1'b0; + if(_zz_258)begin + if(_zz_259)begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_258)begin + if(_zz_259)begin + execute_arbitration_flushNext = 1'b1; + end + end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(_zz_251)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_260)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_261)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_260)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_261)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_258)begin + if(_zz_259)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_262)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + _zz_52 = 1'b0; + if(DebugPlugin_godmode)begin + _zz_52 = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_inWfi = 1'b0; + if(_zz_257)begin + CsrPlugin_inWfi = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_260)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_261)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_260)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_261)begin + case(_zz_263) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + 2'b01 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_sepc; + end + default : begin + end + endcase + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode)begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + end + end + + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_redoInterface_valid,{CsrPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != 5'h0); + assign _zz_53 = {IBusCachedPlugin_predictionJumpInterface_valid,{CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; + assign _zz_54 = (_zz_53 & (~ _zz_340)); + assign _zz_55 = _zz_54[3]; + assign _zz_56 = _zz_54[4]; + assign _zz_57 = (_zz_54[1] || _zz_55); + assign _zz_58 = (_zz_54[2] || _zz_55); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_223; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_342); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_59 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_59); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_59); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_60); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_60); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_61); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_61); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_62; + assign _zz_62 = ((1'b0 && (! _zz_63)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_63 = _zz_64; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_63; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_65)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_65 = _zz_66; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_65; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_67; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + always @ (*) begin + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(_zz_166) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + end + + assign _zz_68 = _zz_343[11]; + always @ (*) begin + _zz_69[18] = _zz_68; + _zz_69[17] = _zz_68; + _zz_69[16] = _zz_68; + _zz_69[15] = _zz_68; + _zz_69[14] = _zz_68; + _zz_69[13] = _zz_68; + _zz_69[12] = _zz_68; + _zz_69[11] = _zz_68; + _zz_69[10] = _zz_68; + _zz_69[9] = _zz_68; + _zz_69[8] = _zz_68; + _zz_69[7] = _zz_68; + _zz_69[6] = _zz_68; + _zz_69[5] = _zz_68; + _zz_69[4] = _zz_68; + _zz_69[3] = _zz_68; + _zz_69[2] = _zz_68; + _zz_69[1] = _zz_68; + _zz_69[0] = _zz_68; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_344[31])); + if(_zz_74)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_70 = _zz_345[19]; + always @ (*) begin + _zz_71[10] = _zz_70; + _zz_71[9] = _zz_70; + _zz_71[8] = _zz_70; + _zz_71[7] = _zz_70; + _zz_71[6] = _zz_70; + _zz_71[5] = _zz_70; + _zz_71[4] = _zz_70; + _zz_71[3] = _zz_70; + _zz_71[2] = _zz_70; + _zz_71[1] = _zz_70; + _zz_71[0] = _zz_70; + end + + assign _zz_72 = _zz_346[11]; + always @ (*) begin + _zz_73[18] = _zz_72; + _zz_73[17] = _zz_72; + _zz_73[16] = _zz_72; + _zz_73[15] = _zz_72; + _zz_73[14] = _zz_72; + _zz_73[13] = _zz_72; + _zz_73[12] = _zz_72; + _zz_73[11] = _zz_72; + _zz_73[10] = _zz_72; + _zz_73[9] = _zz_72; + _zz_73[8] = _zz_72; + _zz_73[7] = _zz_72; + _zz_73[6] = _zz_72; + _zz_73[5] = _zz_72; + _zz_73[4] = _zz_72; + _zz_73[3] = _zz_72; + _zz_73[2] = _zz_72; + _zz_73[1] = _zz_72; + _zz_73[0] = _zz_72; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_74 = _zz_347[1]; + end + default : begin + _zz_74 = _zz_348[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_75 = _zz_349[19]; + always @ (*) begin + _zz_76[10] = _zz_75; + _zz_76[9] = _zz_75; + _zz_76[8] = _zz_75; + _zz_76[7] = _zz_75; + _zz_76[6] = _zz_75; + _zz_76[5] = _zz_75; + _zz_76[4] = _zz_75; + _zz_76[3] = _zz_75; + _zz_76[2] = _zz_75; + _zz_76[1] = _zz_75; + _zz_76[0] = _zz_75; + end + + assign _zz_77 = _zz_350[11]; + always @ (*) begin + _zz_78[18] = _zz_77; + _zz_78[17] = _zz_77; + _zz_78[16] = _zz_77; + _zz_78[15] = _zz_77; + _zz_78[14] = _zz_77; + _zz_78[13] = _zz_77; + _zz_78[12] = _zz_77; + _zz_78[11] = _zz_77; + _zz_78[10] = _zz_77; + _zz_78[9] = _zz_77; + _zz_78[8] = _zz_77; + _zz_78[7] = _zz_77; + _zz_78[6] = _zz_77; + _zz_78[5] = _zz_77; + _zz_78[4] = _zz_77; + _zz_78[3] = _zz_77; + _zz_78[2] = _zz_77; + _zz_78[1] = _zz_77; + _zz_78[0] = _zz_77; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_76,{{{_zz_480,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_78,{{{_zz_481,_zz_482},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_187 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_188 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_189 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_188; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_191 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_192 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_193 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_255)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_253)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @ (*) begin + _zz_194 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_253)begin + _zz_194 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_254)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_252)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_254)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_252)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_186 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_220 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + always @ (*) begin + _zz_47 = 1'b0; + if(decode_INSTRUCTION[25])begin + if(decode_MEMORY_LRSC)begin + _zz_47 = 1'b1; + end + if(decode_MEMORY_AMO)begin + _zz_47 = 1'b1; + end + end + end + + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + _zz_195 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_264)begin + if(_zz_265)begin + _zz_195 = 1'b1; + end + end + end + end + + always @ (*) begin + _zz_196 = execute_SRC_ADD; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_264)begin + _zz_196 = MmuPlugin_dBusAccess_cmd_payload_address; + end + end + end + + always @ (*) begin + _zz_197 = execute_MEMORY_WR; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_264)begin + _zz_197 = MmuPlugin_dBusAccess_cmd_payload_write; + end + end + end + + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_81 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_81 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_81 = execute_RS2[31 : 0]; + end + endcase + end + + always @ (*) begin + _zz_198 = _zz_81; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_264)begin + _zz_198 = MmuPlugin_dBusAccess_cmd_payload_data; + end + end + end + + always @ (*) begin + _zz_199 = execute_DBusCachedPlugin_size; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_264)begin + _zz_199 = MmuPlugin_dBusAccess_cmd_payload_size; + end + end + end + + assign _zz_219 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + always @ (*) begin + _zz_200 = 1'b0; + if(execute_MEMORY_LRSC)begin + _zz_200 = 1'b1; + end + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_264)begin + _zz_200 = 1'b0; + end + end + end + + always @ (*) begin + _zz_201 = execute_MEMORY_AMO; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_264)begin + _zz_201 = 1'b0; + end + end + end + + assign _zz_203 = execute_INSTRUCTION[31 : 29]; + assign _zz_202 = execute_INSTRUCTION[27]; + always @ (*) begin + _zz_204 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + if(memory_IS_DBUS_SHARING)begin + _zz_204 = 1'b1; + end + end + + assign _zz_205 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_204; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_205; + always @ (*) begin + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + if(memory_IS_DBUS_SHARING)begin + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b1; + end + end + + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @ (*) begin + _zz_206 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_52 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_206 = 1'b1; + end + end + + always @ (*) begin + _zz_207 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_IS_DBUS_SHARING)begin + _zz_207 = 1'b1; + end + end + + assign _zz_208 = (CsrPlugin_privilege == 2'b00); + assign _zz_209 = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_266)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_266)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_266)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_351}; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_352}; + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_82 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_83[31] = _zz_82; + _zz_83[30] = _zz_82; + _zz_83[29] = _zz_82; + _zz_83[28] = _zz_82; + _zz_83[27] = _zz_82; + _zz_83[26] = _zz_82; + _zz_83[25] = _zz_82; + _zz_83[24] = _zz_82; + _zz_83[23] = _zz_82; + _zz_83[22] = _zz_82; + _zz_83[21] = _zz_82; + _zz_83[20] = _zz_82; + _zz_83[19] = _zz_82; + _zz_83[18] = _zz_82; + _zz_83[17] = _zz_82; + _zz_83[16] = _zz_82; + _zz_83[15] = _zz_82; + _zz_83[14] = _zz_82; + _zz_83[13] = _zz_82; + _zz_83[12] = _zz_82; + _zz_83[11] = _zz_82; + _zz_83[10] = _zz_82; + _zz_83[9] = _zz_82; + _zz_83[8] = _zz_82; + _zz_83[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_84 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_85[31] = _zz_84; + _zz_85[30] = _zz_84; + _zz_85[29] = _zz_84; + _zz_85[28] = _zz_84; + _zz_85[27] = _zz_84; + _zz_85[26] = _zz_84; + _zz_85[25] = _zz_84; + _zz_85[24] = _zz_84; + _zz_85[23] = _zz_84; + _zz_85[22] = _zz_84; + _zz_85[21] = _zz_84; + _zz_85[20] = _zz_84; + _zz_85[19] = _zz_84; + _zz_85[18] = _zz_84; + _zz_85[17] = _zz_84; + _zz_85[16] = _zz_84; + _zz_85[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_304) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_83; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_85; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + always @ (*) begin + MmuPlugin_dBusAccess_cmd_ready = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_264)begin + if(_zz_265)begin + MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); + end + end + end + end + + always @ (*) begin + DBusCachedPlugin_forceDatapath = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_264)begin + DBusCachedPlugin_forceDatapath = 1'b1; + end + end + end + + assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1_io_cpu_writeBack_isWrite)) && (dataCache_1_io_cpu_redo || (! dataCache_1_io_cpu_writeBack_haltIt))); + assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1_io_cpu_writeBack_data; + assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1_io_cpu_writeBack_unalignedAccess || dataCache_1_io_cpu_writeBack_accessError); + assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1_io_cpu_redo; + assign _zz_87 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_88 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_89 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); + assign _zz_90 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_91 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_92 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_86 = {(((decode_INSTRUCTION & _zz_483) == 32'h02000050) != 1'b0),{({_zz_88,_zz_484} != 2'b00),{(_zz_485 != 1'b0),{(_zz_486 != _zz_487),{_zz_488,{_zz_489,_zz_490}}}}}}; + assign _zz_93 = _zz_86[2 : 1]; + assign _zz_45 = _zz_93; + assign _zz_94 = _zz_86[7 : 6]; + assign _zz_44 = _zz_94; + assign _zz_95 = _zz_86[9 : 8]; + assign _zz_43 = _zz_95; + assign _zz_96 = _zz_86[22 : 21]; + assign _zz_42 = _zz_96; + assign _zz_97 = _zz_86[24 : 23]; + assign _zz_41 = _zz_97; + assign _zz_98 = _zz_86[31 : 30]; + assign _zz_40 = _zz_98; + assign _zz_99 = _zz_86[34 : 33]; + assign _zz_39 = _zz_99; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_221; + assign decode_RegFilePlugin_rs2Data = _zz_222; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_37 && writeBack_arbitration_isFiring); + if(_zz_100)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_36[11 : 7]; + if(_zz_100)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_46; + if(_zz_100)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_101 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_101 = {31'd0, _zz_353}; + end + default : begin + _zz_101 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_102 = _zz_32; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_102 = {29'd0, _zz_354}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_102 = {decode_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_102 = {27'd0, _zz_355}; + end + endcase + end + + assign _zz_103 = _zz_356[11]; + always @ (*) begin + _zz_104[19] = _zz_103; + _zz_104[18] = _zz_103; + _zz_104[17] = _zz_103; + _zz_104[16] = _zz_103; + _zz_104[15] = _zz_103; + _zz_104[14] = _zz_103; + _zz_104[13] = _zz_103; + _zz_104[12] = _zz_103; + _zz_104[11] = _zz_103; + _zz_104[10] = _zz_103; + _zz_104[9] = _zz_103; + _zz_104[8] = _zz_103; + _zz_104[7] = _zz_103; + _zz_104[6] = _zz_103; + _zz_104[5] = _zz_103; + _zz_104[4] = _zz_103; + _zz_104[3] = _zz_103; + _zz_104[2] = _zz_103; + _zz_104[1] = _zz_103; + _zz_104[0] = _zz_103; + end + + assign _zz_105 = _zz_357[11]; + always @ (*) begin + _zz_106[19] = _zz_105; + _zz_106[18] = _zz_105; + _zz_106[17] = _zz_105; + _zz_106[16] = _zz_105; + _zz_106[15] = _zz_105; + _zz_106[14] = _zz_105; + _zz_106[13] = _zz_105; + _zz_106[12] = _zz_105; + _zz_106[11] = _zz_105; + _zz_106[10] = _zz_105; + _zz_106[9] = _zz_105; + _zz_106[8] = _zz_105; + _zz_106[7] = _zz_105; + _zz_106[6] = _zz_105; + _zz_106[5] = _zz_105; + _zz_106[4] = _zz_105; + _zz_106[3] = _zz_105; + _zz_106[2] = _zz_105; + _zz_106[1] = _zz_105; + _zz_106[0] = _zz_105; + end + + always @ (*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_107 = _zz_30; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_107 = {_zz_104,decode_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_107 = {_zz_106,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_107 = _zz_29; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_358; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_108[0] = execute_SRC1[31]; + _zz_108[1] = execute_SRC1[30]; + _zz_108[2] = execute_SRC1[29]; + _zz_108[3] = execute_SRC1[28]; + _zz_108[4] = execute_SRC1[27]; + _zz_108[5] = execute_SRC1[26]; + _zz_108[6] = execute_SRC1[25]; + _zz_108[7] = execute_SRC1[24]; + _zz_108[8] = execute_SRC1[23]; + _zz_108[9] = execute_SRC1[22]; + _zz_108[10] = execute_SRC1[21]; + _zz_108[11] = execute_SRC1[20]; + _zz_108[12] = execute_SRC1[19]; + _zz_108[13] = execute_SRC1[18]; + _zz_108[14] = execute_SRC1[17]; + _zz_108[15] = execute_SRC1[16]; + _zz_108[16] = execute_SRC1[15]; + _zz_108[17] = execute_SRC1[14]; + _zz_108[18] = execute_SRC1[13]; + _zz_108[19] = execute_SRC1[12]; + _zz_108[20] = execute_SRC1[11]; + _zz_108[21] = execute_SRC1[10]; + _zz_108[22] = execute_SRC1[9]; + _zz_108[23] = execute_SRC1[8]; + _zz_108[24] = execute_SRC1[7]; + _zz_108[25] = execute_SRC1[6]; + _zz_108[26] = execute_SRC1[5]; + _zz_108[27] = execute_SRC1[4]; + _zz_108[28] = execute_SRC1[3]; + _zz_108[29] = execute_SRC1[2]; + _zz_108[30] = execute_SRC1[1]; + _zz_108[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_108 : execute_SRC1); + always @ (*) begin + _zz_109[0] = memory_SHIFT_RIGHT[31]; + _zz_109[1] = memory_SHIFT_RIGHT[30]; + _zz_109[2] = memory_SHIFT_RIGHT[29]; + _zz_109[3] = memory_SHIFT_RIGHT[28]; + _zz_109[4] = memory_SHIFT_RIGHT[27]; + _zz_109[5] = memory_SHIFT_RIGHT[26]; + _zz_109[6] = memory_SHIFT_RIGHT[25]; + _zz_109[7] = memory_SHIFT_RIGHT[24]; + _zz_109[8] = memory_SHIFT_RIGHT[23]; + _zz_109[9] = memory_SHIFT_RIGHT[22]; + _zz_109[10] = memory_SHIFT_RIGHT[21]; + _zz_109[11] = memory_SHIFT_RIGHT[20]; + _zz_109[12] = memory_SHIFT_RIGHT[19]; + _zz_109[13] = memory_SHIFT_RIGHT[18]; + _zz_109[14] = memory_SHIFT_RIGHT[17]; + _zz_109[15] = memory_SHIFT_RIGHT[16]; + _zz_109[16] = memory_SHIFT_RIGHT[15]; + _zz_109[17] = memory_SHIFT_RIGHT[14]; + _zz_109[18] = memory_SHIFT_RIGHT[13]; + _zz_109[19] = memory_SHIFT_RIGHT[12]; + _zz_109[20] = memory_SHIFT_RIGHT[11]; + _zz_109[21] = memory_SHIFT_RIGHT[10]; + _zz_109[22] = memory_SHIFT_RIGHT[9]; + _zz_109[23] = memory_SHIFT_RIGHT[8]; + _zz_109[24] = memory_SHIFT_RIGHT[7]; + _zz_109[25] = memory_SHIFT_RIGHT[6]; + _zz_109[26] = memory_SHIFT_RIGHT[5]; + _zz_109[27] = memory_SHIFT_RIGHT[4]; + _zz_109[28] = memory_SHIFT_RIGHT[3]; + _zz_109[29] = memory_SHIFT_RIGHT[2]; + _zz_109[30] = memory_SHIFT_RIGHT[1]; + _zz_109[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_110 = 1'b0; + if(_zz_267)begin + if(_zz_268)begin + if(_zz_115)begin + _zz_110 = 1'b1; + end + end + end + if(_zz_269)begin + if(_zz_270)begin + if(_zz_117)begin + _zz_110 = 1'b1; + end + end + end + if(_zz_271)begin + if(_zz_272)begin + if(_zz_119)begin + _zz_110 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_110 = 1'b0; + end + end + + always @ (*) begin + _zz_111 = 1'b0; + if(_zz_267)begin + if(_zz_268)begin + if(_zz_116)begin + _zz_111 = 1'b1; + end + end + end + if(_zz_269)begin + if(_zz_270)begin + if(_zz_118)begin + _zz_111 = 1'b1; + end + end + end + if(_zz_271)begin + if(_zz_272)begin + if(_zz_120)begin + _zz_111 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_111 = 1'b0; + end + end + + assign _zz_115 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_116 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_117 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_118 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_119 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_120 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + always @ (*) begin + case(_zz_273) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_273) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_365) + $signed(_zz_366)); + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; + if(_zz_251)begin + if(_zz_274)begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; + if(_zz_275)begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); + assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_370); + end + if(memory_MulDivIterativePlugin_div_counter_willClear)begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_121 = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_121[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_371); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_372 : _zz_373); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_374[31:0]; + assign _zz_122 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_123 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_124 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_125[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_125[31 : 0] = execute_RS1; + end + + always @ (*) begin + CsrPlugin_privilege = _zz_126; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0; + assign CsrPlugin_sip_SEIP_OR = (CsrPlugin_sip_SEIP_SOFT || CsrPlugin_sip_SEIP_INPUT); + always @ (*) begin + CsrPlugin_redoInterface_valid = 1'b0; + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + CsrPlugin_redoInterface_valid = 1'b1; + end + end + end + + assign CsrPlugin_redoInterface_payload = decode_PC; + assign _zz_127 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); + assign _zz_128 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); + assign _zz_129 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); + assign _zz_130 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_131 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_132 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + case(CsrPlugin_exceptionPortCtrl_exceptionContext_code) + 4'b0000 : begin + if(((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0001 : begin + if(((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0010 : begin + if(((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0100 : begin + if(((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0101 : begin + if(((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0110 : begin + if(((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0111 : begin + if(((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b1000 : begin + if(((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b1001 : begin + if(((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b1100 : begin + if(((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b1101 : begin + if(((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b1111 : begin + if(((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + default : begin + end + endcase + end + + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_133 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_134 = _zz_384[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_256)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b01 : begin + CsrPlugin_xtvec_mode = CsrPlugin_stvec_mode; + end + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b01 : begin + CsrPlugin_xtvec_base = CsrPlugin_stvec_base; + end + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_770)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_771)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_256)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_324)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_260)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_261)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_321)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_320)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_322)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_323)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_384)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(_zz_276)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_277)begin + CsrPlugin_selfException_valid = 1'b1; + end + if(_zz_278)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_277)begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(_zz_278)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + 2'b01 : begin + CsrPlugin_selfException_payload_code = 4'b1001; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_276)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_276)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + always @ (*) begin + execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; + end + if(execute_CsrPlugin_csr_324)begin + execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; + end + end + + always @ (*) begin + case(_zz_306) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid)begin + case(_zz_279) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_135))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + always @ (*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_279) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_136 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_136 == 3'b000)) begin + _zz_137 = execute_BranchPlugin_eq; + end else if((_zz_136 == 3'b001)) begin + _zz_137 = (! execute_BranchPlugin_eq); + end else if((((_zz_136 & 3'b101) == 3'b101))) begin + _zz_137 = (! execute_SRC_LESS); + end else begin + _zz_137 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_138 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_138 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_138 = 1'b1; + end + default : begin + _zz_138 = _zz_137; + end + endcase + end + + assign _zz_139 = _zz_386[11]; + always @ (*) begin + _zz_140[19] = _zz_139; + _zz_140[18] = _zz_139; + _zz_140[17] = _zz_139; + _zz_140[16] = _zz_139; + _zz_140[15] = _zz_139; + _zz_140[14] = _zz_139; + _zz_140[13] = _zz_139; + _zz_140[12] = _zz_139; + _zz_140[11] = _zz_139; + _zz_140[10] = _zz_139; + _zz_140[9] = _zz_139; + _zz_140[8] = _zz_139; + _zz_140[7] = _zz_139; + _zz_140[6] = _zz_139; + _zz_140[5] = _zz_139; + _zz_140[4] = _zz_139; + _zz_140[3] = _zz_139; + _zz_140[2] = _zz_139; + _zz_140[1] = _zz_139; + _zz_140[0] = _zz_139; + end + + assign _zz_141 = _zz_387[19]; + always @ (*) begin + _zz_142[10] = _zz_141; + _zz_142[9] = _zz_141; + _zz_142[8] = _zz_141; + _zz_142[7] = _zz_141; + _zz_142[6] = _zz_141; + _zz_142[5] = _zz_141; + _zz_142[4] = _zz_141; + _zz_142[3] = _zz_141; + _zz_142[2] = _zz_141; + _zz_142[1] = _zz_141; + _zz_142[0] = _zz_141; + end + + assign _zz_143 = _zz_388[11]; + always @ (*) begin + _zz_144[18] = _zz_143; + _zz_144[17] = _zz_143; + _zz_144[16] = _zz_143; + _zz_144[15] = _zz_143; + _zz_144[14] = _zz_143; + _zz_144[13] = _zz_143; + _zz_144[12] = _zz_143; + _zz_144[11] = _zz_143; + _zz_144[10] = _zz_143; + _zz_144[9] = _zz_143; + _zz_144[8] = _zz_143; + _zz_144[7] = _zz_143; + _zz_144[6] = _zz_143; + _zz_144[5] = _zz_143; + _zz_144[4] = _zz_143; + _zz_144[3] = _zz_143; + _zz_144[2] = _zz_143; + _zz_144[1] = _zz_143; + _zz_144[0] = _zz_143; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_145 = (_zz_389[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_145 = _zz_390[1]; + end + default : begin + _zz_145 = _zz_391[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_145); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_146 = _zz_392[11]; + always @ (*) begin + _zz_147[19] = _zz_146; + _zz_147[18] = _zz_146; + _zz_147[17] = _zz_146; + _zz_147[16] = _zz_146; + _zz_147[15] = _zz_146; + _zz_147[14] = _zz_146; + _zz_147[13] = _zz_146; + _zz_147[12] = _zz_146; + _zz_147[11] = _zz_146; + _zz_147[10] = _zz_146; + _zz_147[9] = _zz_146; + _zz_147[8] = _zz_146; + _zz_147[7] = _zz_146; + _zz_147[6] = _zz_146; + _zz_147[5] = _zz_146; + _zz_147[4] = _zz_146; + _zz_147[3] = _zz_146; + _zz_147[2] = _zz_146; + _zz_147[1] = _zz_146; + _zz_147[0] = _zz_146; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_147,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_149,{{{_zz_679,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_151,{{{_zz_680,_zz_681},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_395}; + end + end + endcase + end + + assign _zz_148 = _zz_393[19]; + always @ (*) begin + _zz_149[10] = _zz_148; + _zz_149[9] = _zz_148; + _zz_149[8] = _zz_148; + _zz_149[7] = _zz_148; + _zz_149[6] = _zz_148; + _zz_149[5] = _zz_148; + _zz_149[4] = _zz_148; + _zz_149[3] = _zz_148; + _zz_149[2] = _zz_148; + _zz_149[1] = _zz_148; + _zz_149[0] = _zz_148; + end + + assign _zz_150 = _zz_394[11]; + always @ (*) begin + _zz_151[18] = _zz_150; + _zz_151[17] = _zz_150; + _zz_151[16] = _zz_150; + _zz_151[15] = _zz_150; + _zz_151[14] = _zz_150; + _zz_151[13] = _zz_150; + _zz_151[12] = _zz_150; + _zz_151[11] = _zz_150; + _zz_151[10] = _zz_150; + _zz_151[9] = _zz_150; + _zz_151[8] = _zz_150; + _zz_151[7] = _zz_150; + _zz_151[6] = _zz_150; + _zz_151[5] = _zz_150; + _zz_151[4] = _zz_150; + _zz_151[3] = _zz_150; + _zz_151[2] = _zz_150; + _zz_151[1] = _zz_150; + _zz_151[0] = _zz_150; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + assign MmuPlugin_ports_0_dirty = 1'b0; + always @ (*) begin + MmuPlugin_ports_0_requireMmuLockupCalc = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + if((CsrPlugin_privilege == 2'b11))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + end + + always @ (*) begin + MmuPlugin_ports_0_cacheHitsCalc[0] = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[1] = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[2] = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[3] = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + end + + assign MmuPlugin_ports_0_cacheHit = (MmuPlugin_ports_0_cacheHitsCalc != 4'b0000); + assign _zz_152 = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign _zz_153 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_152); + assign _zz_154 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_152); + assign _zz_155 = {_zz_154,_zz_153}; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_224; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_225; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_226; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_227; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_228; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_229; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_230; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_231; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_232; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_233; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_234; + always @ (*) begin + MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; + if(_zz_280)begin + if(_zz_281)begin + MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; + end + end + end + + assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0; + assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); + always @ (*) begin + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_397); + if(MmuPlugin_ports_0_entryToReplace_willClear)begin + MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); + end else begin + IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; + end else begin + IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; + end else begin + IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_0_dirty) && MmuPlugin_ports_0_cacheHit) && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); + end else begin + IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_0_dirty || (! MmuPlugin_ports_0_cacheHit)); + end else begin + IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; + end else begin + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1011) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1110)) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111)); + assign IBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_0_requireMmuLockupCalc); + assign IBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_0_cacheHitsCalc[0]; + assign IBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_0_cache_0_physicalAddress_1,(MmuPlugin_ports_0_cache_0_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_0_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_0_cacheHitsCalc[1]; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_0_cache_1_physicalAddress_1,(MmuPlugin_ports_0_cache_1_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_1_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_0_cacheHitsCalc[2]; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_0_cache_2_physicalAddress_1,(MmuPlugin_ports_0_cache_2_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_2_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_0_cache_3_physicalAddress_1,(MmuPlugin_ports_0_cache_3_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_3_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_ports_1_dirty = 1'b0; + always @ (*) begin + MmuPlugin_ports_1_requireMmuLockupCalc = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end + if((CsrPlugin_privilege == 2'b11))begin + if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end + end + end + + always @ (*) begin + MmuPlugin_ports_1_cacheHitsCalc[0] = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[1] = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[2] = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[3] = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + end + + assign MmuPlugin_ports_1_cacheHit = (MmuPlugin_ports_1_cacheHitsCalc != 4'b0000); + assign _zz_156 = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign _zz_157 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_156); + assign _zz_158 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_156); + assign _zz_159 = {_zz_158,_zz_157}; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_235; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_236; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_237; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_238; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_239; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_240; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_241; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_242; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_243; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_244; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_245; + always @ (*) begin + MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; + if(_zz_280)begin + if(_zz_282)begin + MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; + end + end + end + + assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; + assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); + always @ (*) begin + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_399); + if(MmuPlugin_ports_1_entryToReplace_willClear)begin + MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); + end else begin + DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; + end else begin + DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; + end else begin + DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_1_dirty) && MmuPlugin_ports_1_cacheHit) && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); + end else begin + DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_1_dirty || (! MmuPlugin_ports_1_cacheHit)); + end else begin + DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; + end else begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1011) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1110)) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111)); + assign DBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_1_requireMmuLockupCalc); + assign DBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_1_cacheHitsCalc[0]; + assign DBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_1_cache_0_physicalAddress_1,(MmuPlugin_ports_1_cache_0_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_0_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_1_cacheHitsCalc[1]; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_1_cache_1_physicalAddress_1,(MmuPlugin_ports_1_cache_1_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_1_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_1_cacheHitsCalc[2]; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_shared_dBusRsp_pte_V = _zz_400[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = _zz_401[0]; + assign MmuPlugin_shared_dBusRsp_pte_W = _zz_402[0]; + assign MmuPlugin_shared_dBusRsp_pte_X = _zz_403[0]; + assign MmuPlugin_shared_dBusRsp_pte_U = _zz_404[0]; + assign MmuPlugin_shared_dBusRsp_pte_G = _zz_405[0]; + assign MmuPlugin_shared_dBusRsp_pte_A = _zz_406[0]; + assign MmuPlugin_shared_dBusRsp_pte_D = _zz_407[0]; + assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; + assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; + assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; + assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_shared_dBusRspStaged_payload_error); + assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X); + always @ (*) begin + MmuPlugin_dBusAccess_cmd_valid = 1'b0; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + MmuPlugin_dBusAccess_cmd_valid = 1'b1; + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + MmuPlugin_dBusAccess_cmd_valid = 1'b1; + end + default : begin + end + endcase + end + + assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; + assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; + always @ (*) begin + MmuPlugin_dBusAccess_cmd_payload_address = 32'h0; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},2'b00}; + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},2'b00}; + end + default : begin + end + endcase + end + + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'h0; + assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; + always @ (*) begin + _zz_160[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); + _zz_160[1] = (((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)); + end + + assign _zz_161 = _zz_160; + always @ (*) begin + _zz_162[0] = _zz_161[1]; + _zz_162[1] = _zz_161[0]; + end + + assign _zz_163 = (_zz_162 & (~ _zz_408)); + always @ (*) begin + _zz_164[0] = _zz_163[1]; + _zz_164[1] = _zz_163[0]; + end + + assign MmuPlugin_shared_refills = _zz_164; + assign _zz_165 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); + assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[0]); + assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[1]); + assign _zz_33 = _zz_45; + assign _zz_20 = decode_ALU_CTRL; + assign _zz_18 = _zz_44; + assign _zz_34 = decode_to_execute_ALU_CTRL; + assign _zz_31 = _zz_43; + assign _zz_17 = decode_ALU_BITWISE_CTRL; + assign _zz_15 = _zz_42; + assign _zz_35 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_14 = decode_SHIFT_CTRL; + assign _zz_11 = execute_SHIFT_CTRL; + assign _zz_12 = _zz_41; + assign _zz_28 = decode_to_execute_SHIFT_CTRL; + assign _zz_27 = execute_to_memory_SHIFT_CTRL; + assign _zz_9 = decode_ENV_CTRL; + assign _zz_6 = execute_ENV_CTRL; + assign _zz_4 = memory_ENV_CTRL; + assign _zz_7 = _zz_40; + assign _zz_23 = decode_to_execute_ENV_CTRL; + assign _zz_22 = execute_to_memory_ENV_CTRL; + assign _zz_24 = memory_to_writeBack_ENV_CTRL; + assign _zz_2 = decode_BRANCH_CTRL; + assign _zz_48 = _zz_39; + assign _zz_21 = decode_to_execute_BRANCH_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(_zz_166) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_167 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_167[0 : 0] = 1'b1; + end + end + + always @ (*) begin + _zz_168 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_168[1 : 0] = 2'b10; + end + end + + always @ (*) begin + _zz_169 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_169[1 : 0] = 2'b11; + end + end + + always @ (*) begin + _zz_170 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_170[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_170[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_170[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_170[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_170[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_170[1 : 1] = CsrPlugin_sstatus_SIE; + _zz_170[19 : 19] = MmuPlugin_status_mxr; + _zz_170[18 : 18] = MmuPlugin_status_sum; + _zz_170[17 : 17] = MmuPlugin_status_mprv; + end + end + + always @ (*) begin + _zz_171 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_171[11 : 11] = CsrPlugin_mip_MEIP; + _zz_171[7 : 7] = CsrPlugin_mip_MTIP; + _zz_171[3 : 3] = CsrPlugin_mip_MSIP; + _zz_171[5 : 5] = CsrPlugin_sip_STIP; + _zz_171[1 : 1] = CsrPlugin_sip_SSIP; + _zz_171[9 : 9] = CsrPlugin_sip_SEIP_OR; + end + end + + always @ (*) begin + _zz_172 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_172[11 : 11] = CsrPlugin_mie_MEIE; + _zz_172[7 : 7] = CsrPlugin_mie_MTIE; + _zz_172[3 : 3] = CsrPlugin_mie_MSIE; + _zz_172[9 : 9] = CsrPlugin_sie_SEIE; + _zz_172[5 : 5] = CsrPlugin_sie_STIE; + _zz_172[1 : 1] = CsrPlugin_sie_SSIE; + end + end + + always @ (*) begin + _zz_173 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_173[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_174 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_174[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_175 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_175[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_175[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_176 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_176[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_256)begin + _zz_177[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_177[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_177[1 : 1] = CsrPlugin_sstatus_SIE; + _zz_177[19 : 19] = MmuPlugin_status_mxr; + _zz_177[18 : 18] = MmuPlugin_status_sum; + _zz_177[17 : 17] = MmuPlugin_status_mprv; + end + end + + always @ (*) begin + _zz_178 = 32'h0; + if(execute_CsrPlugin_csr_324)begin + _zz_178[5 : 5] = CsrPlugin_sip_STIP; + _zz_178[1 : 1] = CsrPlugin_sip_SSIP; + _zz_178[9 : 9] = CsrPlugin_sip_SEIP_OR; + end + end + + always @ (*) begin + _zz_179 = 32'h0; + if(execute_CsrPlugin_csr_260)begin + _zz_179[9 : 9] = CsrPlugin_sie_SEIE; + _zz_179[5 : 5] = CsrPlugin_sie_STIE; + _zz_179[1 : 1] = CsrPlugin_sie_SSIE; + end + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_261)begin + _zz_180[31 : 2] = CsrPlugin_stvec_base; + _zz_180[1 : 0] = CsrPlugin_stvec_mode; + end + end + + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_321)begin + _zz_181[31 : 0] = CsrPlugin_sepc; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_320)begin + _zz_182[31 : 0] = CsrPlugin_sscratch; + end + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_322)begin + _zz_183[31 : 31] = CsrPlugin_scause_interrupt; + _zz_183[3 : 0] = CsrPlugin_scause_exceptionCode; + end + end + + always @ (*) begin + _zz_184 = 32'h0; + if(execute_CsrPlugin_csr_323)begin + _zz_184[31 : 0] = CsrPlugin_stval; + end + end + + always @ (*) begin + _zz_185 = 32'h0; + if(execute_CsrPlugin_csr_384)begin + _zz_185[31 : 31] = MmuPlugin_satp_mode; + _zz_185[30 : 22] = MmuPlugin_satp_asid; + _zz_185[19 : 0] = MmuPlugin_satp_ppn; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_167 | _zz_168) | (_zz_169 | _zz_682)) | ((_zz_170 | _zz_171) | (_zz_172 | _zz_173))) | (((_zz_174 | _zz_175) | (_zz_176 | _zz_177)) | ((_zz_178 | _zz_179) | (_zz_180 | _zz_181)))) | ((_zz_182 | _zz_183) | (_zz_184 | _zz_185))); + always @ (posedge clk or posedge reset) begin + if (reset) begin + IBusCachedPlugin_fetchPc_pcReg <= 32'h80000000; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_64 <= 1'b0; + _zz_66 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_79; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + dBus_rsp_regNext_valid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_80; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_100 <= 1'b1; + _zz_112 <= 1'b0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + _zz_126 <= 2'b11; + CsrPlugin_mtvec_mode <= 2'b00; + CsrPlugin_mtvec_base <= 30'h20000008; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_medeleg_IAM <= 1'b0; + CsrPlugin_medeleg_IAF <= 1'b0; + CsrPlugin_medeleg_II <= 1'b0; + CsrPlugin_medeleg_LAM <= 1'b0; + CsrPlugin_medeleg_LAF <= 1'b0; + CsrPlugin_medeleg_SAM <= 1'b0; + CsrPlugin_medeleg_SAF <= 1'b0; + CsrPlugin_medeleg_EU <= 1'b0; + CsrPlugin_medeleg_ES <= 1'b0; + CsrPlugin_medeleg_IPF <= 1'b0; + CsrPlugin_medeleg_LPF <= 1'b0; + CsrPlugin_medeleg_SPF <= 1'b0; + CsrPlugin_mideleg_ST <= 1'b0; + CsrPlugin_mideleg_SE <= 1'b0; + CsrPlugin_mideleg_SS <= 1'b0; + CsrPlugin_sstatus_SIE <= 1'b0; + CsrPlugin_sstatus_SPIE <= 1'b0; + CsrPlugin_sstatus_SPP <= 1'b1; + CsrPlugin_sip_SEIP_SOFT <= 1'b0; + CsrPlugin_sip_STIP <= 1'b0; + CsrPlugin_sip_SSIP <= 1'b0; + CsrPlugin_sie_SEIE <= 1'b0; + CsrPlugin_sie_STIE <= 1'b0; + CsrPlugin_sie_SSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + MmuPlugin_status_sum <= 1'b0; + MmuPlugin_status_mxr <= 1'b0; + MmuPlugin_status_mprv <= 1'b0; + MmuPlugin_satp_mode <= 1'b0; + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_0_entryToReplace_value <= 2'b00; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_entryToReplace_value <= 2'b00; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_166 <= 3'b000; + execute_to_memory_IS_DBUS_SHARING <= 1'b0; + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_64 <= 1'b0; + end + if(_zz_62)begin + _zz_64 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_66 <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_66 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + end + if(_zz_283)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + dBus_rsp_regNext_valid <= dBus_rsp_valid; + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_100 <= 1'b0; + _zz_112 <= (_zz_37 && writeBack_arbitration_isFiring); + memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_284)begin + if(_zz_285)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_286)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_287)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(_zz_288)begin + if(_zz_289)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_290)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_291)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_292)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_293)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_294)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_260)begin + _zz_126 <= CsrPlugin_targetPrivilege; + case(CsrPlugin_targetPrivilege) + 2'b01 : begin + CsrPlugin_sstatus_SIE <= 1'b0; + CsrPlugin_sstatus_SPIE <= CsrPlugin_sstatus_SIE; + CsrPlugin_sstatus_SPP <= CsrPlugin_privilege[0 : 0]; + end + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_261)begin + case(_zz_263) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + _zz_126 <= CsrPlugin_mstatus_MPP; + end + 2'b01 : begin + CsrPlugin_sstatus_SPP <= 1'b0; + CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE; + CsrPlugin_sstatus_SPIE <= 1'b1; + _zz_126 <= {1'b0,CsrPlugin_sstatus_SPP}; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_132,{_zz_131,{_zz_130,{_zz_129,{_zz_128,_zz_127}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); + MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext; + if(contextSwitching)begin + if(MmuPlugin_ports_0_cache_0_exception)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_1_exception)begin + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_2_exception)begin + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_3_exception)begin + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + end + end + MmuPlugin_ports_1_entryToReplace_value <= MmuPlugin_ports_1_entryToReplace_valueNext; + if(contextSwitching)begin + if(MmuPlugin_ports_1_cache_0_exception)begin + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_1_exception)begin + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_2_exception)begin + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_3_exception)begin + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + end + end + MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + if(_zz_295)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if((MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception))begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + end + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + end + end + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; + end + end + default : begin + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + end + end + end + endcase + if(_zz_280)begin + if(_zz_281)begin + if(_zz_296)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b1; + end + if(_zz_297)begin + MmuPlugin_ports_0_cache_1_valid <= 1'b1; + end + if(_zz_298)begin + MmuPlugin_ports_0_cache_2_valid <= 1'b1; + end + if(_zz_299)begin + MmuPlugin_ports_0_cache_3_valid <= 1'b1; + end + end + if(_zz_282)begin + if(_zz_300)begin + MmuPlugin_ports_1_cache_0_valid <= 1'b1; + end + if(_zz_301)begin + MmuPlugin_ports_1_cache_1_valid <= 1'b1; + end + if(_zz_302)begin + MmuPlugin_ports_1_cache_2_valid <= 1'b1; + end + if(_zz_303)begin + MmuPlugin_ports_1_cache_3_valid <= 1'b1; + end + end + end + if((writeBack_arbitration_isValid && writeBack_IS_SFENCE_VMA))begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_DBUS_SHARING <= memory_IS_DBUS_SHARING; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_166) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_166 <= 3'b001; + end + end + 3'b001 : begin + _zz_166 <= 3'b010; + end + 3'b010 : begin + _zz_166 <= 3'b011; + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_166 <= 3'b100; + end + end + 3'b100 : begin + _zz_166 <= 3'b000; + end + default : begin + end + endcase + if(MmuPlugin_dBusAccess_rsp_valid)begin + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_409[0]; + CsrPlugin_mstatus_MIE <= _zz_410[0]; + CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; + CsrPlugin_sstatus_SPIE <= _zz_411[0]; + CsrPlugin_sstatus_SIE <= _zz_412[0]; + MmuPlugin_status_mxr <= _zz_413[0]; + MmuPlugin_status_sum <= _zz_414[0]; + MmuPlugin_status_mprv <= _zz_415[0]; + end + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sip_STIP <= _zz_417[0]; + CsrPlugin_sip_SSIP <= _zz_418[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_419[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_420[0]; + CsrPlugin_mie_MTIE <= _zz_421[0]; + CsrPlugin_mie_MSIE <= _zz_422[0]; + CsrPlugin_sie_SEIE <= _zz_423[0]; + CsrPlugin_sie_STIE <= _zz_424[0]; + CsrPlugin_sie_SSIE <= _zz_425[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_770)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_medeleg_IAM <= _zz_426[0]; + CsrPlugin_medeleg_IAF <= _zz_427[0]; + CsrPlugin_medeleg_II <= _zz_428[0]; + CsrPlugin_medeleg_LAM <= _zz_429[0]; + CsrPlugin_medeleg_LAF <= _zz_430[0]; + CsrPlugin_medeleg_SAM <= _zz_431[0]; + CsrPlugin_medeleg_SAF <= _zz_432[0]; + CsrPlugin_medeleg_EU <= _zz_433[0]; + CsrPlugin_medeleg_ES <= _zz_434[0]; + CsrPlugin_medeleg_IPF <= _zz_435[0]; + CsrPlugin_medeleg_LPF <= _zz_436[0]; + CsrPlugin_medeleg_SPF <= _zz_437[0]; + end + end + if(execute_CsrPlugin_csr_771)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mideleg_SE <= _zz_438[0]; + CsrPlugin_mideleg_ST <= _zz_439[0]; + CsrPlugin_mideleg_SS <= _zz_440[0]; + end + end + if(execute_CsrPlugin_csr_256)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; + CsrPlugin_sstatus_SPIE <= _zz_441[0]; + CsrPlugin_sstatus_SIE <= _zz_442[0]; + MmuPlugin_status_mxr <= _zz_443[0]; + MmuPlugin_status_sum <= _zz_444[0]; + MmuPlugin_status_mprv <= _zz_445[0]; + end + end + if(execute_CsrPlugin_csr_324)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sip_STIP <= _zz_446[0]; + CsrPlugin_sip_SSIP <= _zz_447[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_448[0]; + end + end + if(execute_CsrPlugin_csr_260)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sie_SEIE <= _zz_449[0]; + CsrPlugin_sie_STIE <= _zz_450[0]; + CsrPlugin_sie_SSIE <= _zz_451[0]; + end + end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + end + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_mode <= _zz_453[0]; + end + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_67 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_283)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + dBus_rsp_regNext_payload_last <= dBus_rsp_payload_last; + dBus_rsp_regNext_payload_data <= dBus_rsp_payload_data; + dBus_rsp_regNext_payload_error <= dBus_rsp_payload_error; + _zz_113 <= _zz_36[11 : 7]; + _zz_114 <= _zz_46; + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(_zz_251)begin + if(_zz_274)begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_result <= _zz_375[31:0]; + end + end + end + if(_zz_275)begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_124 ? (~ _zz_125) : _zz_125) + _zz_381); + memory_MulDivIterativePlugin_rs2 <= ((_zz_123 ? (~ execute_RS2) : execute_RS2) + _zz_383); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_124 ^ (_zz_123 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_sip_SEIP_INPUT <= externalInterruptS; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_256)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_134 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_134 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_284)begin + if(_zz_285)begin + CsrPlugin_interrupt_code <= 4'b0101; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + if(_zz_286)begin + CsrPlugin_interrupt_code <= 4'b0001; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + if(_zz_287)begin + CsrPlugin_interrupt_code <= 4'b1001; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + end + if(_zz_288)begin + if(_zz_289)begin + CsrPlugin_interrupt_code <= 4'b0101; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_290)begin + CsrPlugin_interrupt_code <= 4'b0001; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_291)begin + CsrPlugin_interrupt_code <= 4'b1001; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_292)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_293)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_294)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_260)begin + case(CsrPlugin_targetPrivilege) + 2'b01 : begin + CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_sepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + MmuPlugin_shared_dBusRspStaged_payload_data <= MmuPlugin_dBusAccess_rsp_payload_data; + MmuPlugin_shared_dBusRspStaged_payload_error <= MmuPlugin_dBusAccess_rsp_payload_error; + MmuPlugin_shared_dBusRspStaged_payload_redo <= MmuPlugin_dBusAccess_rsp_payload_redo; + if((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)))begin + MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; + MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_shared_pteBuffer_X <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_shared_pteBuffer_U <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_shared_pteBuffer_G <= MmuPlugin_shared_dBusRsp_pte_G; + MmuPlugin_shared_pteBuffer_A <= MmuPlugin_shared_dBusRsp_pte_A; + MmuPlugin_shared_pteBuffer_D <= MmuPlugin_shared_dBusRsp_pte_D; + MmuPlugin_shared_pteBuffer_RSW <= MmuPlugin_shared_dBusRsp_pte_RSW; + MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; + end + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + if(_zz_295)begin + MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; + MmuPlugin_shared_vpn_1 <= _zz_165[31 : 22]; + MmuPlugin_shared_vpn_0 <= _zz_165[21 : 12]; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + end + default : begin + end + endcase + if(_zz_280)begin + if(_zz_281)begin + if(_zz_296)begin + MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_297)begin + MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_298)begin + MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_299)begin + MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + if(_zz_282)begin + if(_zz_300)begin + MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_301)begin + MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_302)begin + MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_303)begin + MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= _zz_29; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= execute_PC; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_51; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_50; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_49; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_13; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_10; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_8; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_5; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_3; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= _zz_32; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= _zz_30; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1 <= decode_SRC1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2 <= decode_SRC2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_25; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_26; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_770 <= (decode_INSTRUCTION[31 : 20] == 12'h302); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_771 <= (decode_INSTRUCTION[31 : 20] == 12'h303); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_256 <= (decode_INSTRUCTION[31 : 20] == 12'h100); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_324 <= (decode_INSTRUCTION[31 : 20] == 12'h144); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_260 <= (decode_INSTRUCTION[31 : 20] == 12'h104); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_261 <= (decode_INSTRUCTION[31 : 20] == 12'h105); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_321 <= (decode_INSTRUCTION[31 : 20] == 12'h141); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_320 <= (decode_INSTRUCTION[31 : 20] == 12'h140); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_322 <= (decode_INSTRUCTION[31 : 20] == 12'h142); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_323 <= (decode_INSTRUCTION[31 : 20] == 12'h143); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_384 <= (decode_INSTRUCTION[31 : 20] == 12'h180); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_416[0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_261)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_stvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_stvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_321)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_320)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_322)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_scause_interrupt <= _zz_452[0]; + CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end + end + if(execute_CsrPlugin_csr_323)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_stval <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_asid <= execute_CsrPlugin_writeData[30 : 22]; + MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; + end + end + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_46; + end + _zz_135 <= debug_bus_cmd_payload_address[2]; + if(_zz_258)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk or posedge debugReset) begin + if (debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_279) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(_zz_258)begin + if(_zz_259)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_262)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_isLrsc, + input io_cpu_execute_args_isAmo, + input io_cpu_execute_args_amoCtrl_swap, + input [2:0] io_cpu_execute_args_amoCtrl_alu, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_memory_mmuRsp_ways_0_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_0_physical, + input io_cpu_memory_mmuRsp_ways_1_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_1_physical, + input io_cpu_memory_mmuRsp_ways_2_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_2_physical, + input io_cpu_memory_mmuRsp_ways_3_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_3_physical, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire _zz_19; + wire _zz_20; + wire _zz_21; + wire _zz_22; + wire [2:0] _zz_23; + wire [0:0] _zz_24; + wire [0:0] _zz_25; + wire [9:0] _zz_26; + wire [9:0] _zz_27; + wire [31:0] _zz_28; + wire [31:0] _zz_29; + wire [31:0] _zz_30; + wire [31:0] _zz_31; + wire [1:0] _zz_32; + wire [31:0] _zz_33; + wire [1:0] _zz_34; + wire [1:0] _zz_35; + wire [0:0] _zz_36; + wire [0:0] _zz_37; + wire [0:0] _zz_38; + wire [2:0] _zz_39; + wire [1:0] _zz_40; + wire [21:0] _zz_41; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_isLrsc; + reg stageA_request_isAmo; + reg stageA_request_amoCtrl_swap; + reg [2:0] stageA_request_amoCtrl_alu; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_isLrsc; + reg stageB_request_isAmo; + reg stageB_request_amoCtrl_swap; + reg [2:0] stageB_request_amoCtrl_alu; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_mmuRsp_ways_0_sel; + reg [31:0] stageB_mmuRsp_ways_0_physical; + reg stageB_mmuRsp_ways_1_sel; + reg [31:0] stageB_mmuRsp_ways_1_physical; + reg stageB_mmuRsp_ways_2_sel; + reg [31:0] stageB_mmuRsp_ways_2_physical; + reg stageB_mmuRsp_ways_3_sel; + reg [31:0] stageB_mmuRsp_ways_3_physical; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + reg stageB_lrSc_reserved; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + reg [31:0] stageB_requestDataBypass; + wire stageB_amo_compare; + wire stageB_amo_unsigned; + wire [31:0] stageB_amo_addSub; + wire stageB_amo_less; + wire stageB_amo_selectRf; + reg [31:0] stageB_amo_result; + reg [31:0] stageB_amo_resultReg; + reg stageB_amo_internal_resultRegValid; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + reg [21:0] ways_0_tags [0:127]; + reg [7:0] ways_0_data_symbol0 [0:1023]; + reg [7:0] ways_0_data_symbol1 [0:1023]; + reg [7:0] ways_0_data_symbol2 [0:1023]; + reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_42; + reg [7:0] _zz_43; + reg [7:0] _zz_44; + reg [7:0] _zz_45; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_15 = (stageB_waysHit || (stageB_request_wr && (! stageB_request_isAmo))); + assign _zz_16 = (! stageB_amo_internal_resultRegValid); + assign _zz_17 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign _zz_18 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_19 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign _zz_20 = (((! stageB_request_wr) || stageB_request_isAmo) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign _zz_21 = (! stageB_flusher_hold); + assign _zz_22 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_23 = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,2'b00}); + assign _zz_24 = _zz_4[0 : 0]; + assign _zz_25 = _zz_4[1 : 1]; + assign _zz_26 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_27 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_28 = ($signed(_zz_29) + $signed(_zz_33)); + assign _zz_29 = ($signed(_zz_30) + $signed(_zz_31)); + assign _zz_30 = stageB_request_data; + assign _zz_31 = (stageB_amo_compare ? (~ stageB_dataMux) : stageB_dataMux); + assign _zz_32 = (stageB_amo_compare ? _zz_34 : _zz_35); + assign _zz_33 = {{30{_zz_32[1]}}, _zz_32}; + assign _zz_34 = 2'b01; + assign _zz_35 = 2'b00; + assign _zz_36 = 1'b1; + assign _zz_37 = (! stageB_lrSc_reserved); + assign _zz_38 = loader_counter_willIncrement; + assign _zz_39 = {2'd0, _zz_38}; + assign _zz_40 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_41 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_41; + end + end + + always @ (*) begin + _zz_11 = {_zz_45, _zz_44, _zz_43, _zz_42}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_42 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_43 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_44 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_45 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_24[0]; + assign ways_0_tagsReadRsp_error = _zz_25[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + if(stageB_request_isAmo)begin + if(_zz_16)begin + dataWriteCmd_valid = 1'b0; + end + end + if(_zz_17)begin + dataWriteCmd_valid = 1'b0; + end + end + end + end + end + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_18)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_18)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(_zz_18)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(_zz_18)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_36[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(_zz_18)begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_26)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_27)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(! _zz_15) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_14)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(_zz_19)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_15)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(stageB_request_isAmo)begin + if(_zz_16)begin + io_cpu_writeBack_haltIt = 1'b1; + end + end + if(_zz_17)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + always @ (*) begin + stageB_requestDataBypass = stageB_request_data; + if(stageB_request_isAmo)begin + stageB_requestDataBypass = stageB_amo_resultReg; + end + end + + assign stageB_amo_compare = stageB_request_amoCtrl_alu[2]; + assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == 2'b11); + assign stageB_amo_addSub = _zz_28; + assign stageB_amo_less = ((stageB_request_data[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : stageB_request_data[31])); + assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less)); + always @ (*) begin + case(_zz_23) + 3'b000 : begin + stageB_amo_result = stageB_amo_addSub; + end + 3'b001 : begin + stageB_amo_result = (stageB_request_data ^ stageB_dataMux); + end + 3'b010 : begin + stageB_amo_result = (stageB_request_data | stageB_dataMux); + end + 3'b011 : begin + stageB_amo_result = (stageB_request_data & stageB_dataMux); + end + default : begin + stageB_amo_result = (stageB_amo_selectRf ? stageB_request_data : stageB_dataMux); + end + endcase + end + + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_request_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + if(_zz_20)begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; + end + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_14)begin + io_mem_cmd_valid = (! memCmdSent); + if(_zz_19)begin + io_mem_cmd_valid = 1'b0; + end + end else begin + if(_zz_15)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + if(stageB_request_isAmo)begin + if(_zz_16)begin + io_mem_cmd_valid = 1'b0; + end + end + if(_zz_20)begin + io_mem_cmd_valid = 1'b0; + end + if(_zz_17)begin + io_mem_cmd_valid = 1'b0; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(! _zz_15) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + if((stageB_request_isLrsc && stageB_request_wr))begin + io_cpu_writeBack_data = {31'd0, _zz_37}; + end + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_18)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_39); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; + stageA_request_isAmo <= io_cpu_execute_args_isAmo; + stageA_request_amoCtrl_swap <= io_cpu_execute_args_amoCtrl_swap; + stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_isLrsc <= stageA_request_isLrsc; + stageB_request_isAmo <= stageA_request_isAmo; + stageB_request_amoCtrl_swap <= stageA_request_amoCtrl_swap; + stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + stageB_mmuRsp_ways_0_sel <= io_cpu_memory_mmuRsp_ways_0_sel; + stageB_mmuRsp_ways_0_physical <= io_cpu_memory_mmuRsp_ways_0_physical; + stageB_mmuRsp_ways_1_sel <= io_cpu_memory_mmuRsp_ways_1_sel; + stageB_mmuRsp_ways_1_physical <= io_cpu_memory_mmuRsp_ways_1_physical; + stageB_mmuRsp_ways_2_sel <= io_cpu_memory_mmuRsp_ways_2_sel; + stageB_mmuRsp_ways_2_physical <= io_cpu_memory_mmuRsp_ways_2_physical; + stageB_mmuRsp_ways_3_sel <= io_cpu_memory_mmuRsp_ways_3_sel; + stageB_mmuRsp_ways_3_physical <= io_cpu_memory_mmuRsp_ways_3_physical; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if(stageB_flusher_valid)begin + if(_zz_21)begin + if(_zz_22)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + stageB_amo_internal_resultRegValid <= io_cpu_writeBack_isStuck; + stageB_amo_resultReg <= stageB_amo_result; + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk or posedge reset) begin + if (reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + stageB_lrSc_reserved <= 1'b0; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_21)begin + if(! _zz_22) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + if(((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc))begin + stageB_lrSc_reserved <= (! stageB_request_wr); + end + if(_zz_13)begin + stageB_lrSc_reserved <= stageB_lrSc_reserved; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_18)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_40[0:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + input io_cpu_fetch_mmuRsp_ways_0_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_0_physical, + input io_cpu_fetch_mmuRsp_ways_1_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_1_physical, + input io_cpu_fetch_mmuRsp_ways_2_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_2_physical, + input io_cpu_fetch_mmuRsp_ways_3_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_3_physical, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_9, + input [31:0] _zz_10, + input clk, + input reset +); + reg [31:0] _zz_11; + reg [21:0] _zz_12; + wire _zz_13; + wire _zz_14; + wire [0:0] _zz_15; + wire [0:0] _zz_16; + wire [21:0] _zz_17; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_mmuRsp_ways_0_sel; + reg [31:0] decodeStage_mmuRsp_ways_0_physical; + reg decodeStage_mmuRsp_ways_1_sel; + reg [31:0] decodeStage_mmuRsp_ways_1_physical; + reg decodeStage_mmuRsp_ways_2_sel; + reg [31:0] decodeStage_mmuRsp_ways_2_physical; + reg decodeStage_mmuRsp_ways_3_sel; + reg [31:0] decodeStage_mmuRsp_ways_3_physical; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + reg [31:0] banks_0 [0:1023]; + reg [21:0] ways_0_tags [0:127]; + + assign _zz_13 = (! lineLoader_flushCounter[7]); + assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_15 = _zz_8[0 : 0]; + assign _zz_16 = _zz_8[1 : 1]; + assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_11 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_12 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_13)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_12; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk or posedge reset) begin + if (reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_14)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_13)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_14)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + decodeStage_mmuRsp_ways_0_sel <= io_cpu_fetch_mmuRsp_ways_0_sel; + decodeStage_mmuRsp_ways_0_physical <= io_cpu_fetch_mmuRsp_ways_0_physical; + decodeStage_mmuRsp_ways_1_sel <= io_cpu_fetch_mmuRsp_ways_1_sel; + decodeStage_mmuRsp_ways_1_physical <= io_cpu_fetch_mmuRsp_ways_1_physical; + decodeStage_mmuRsp_ways_2_sel <= io_cpu_fetch_mmuRsp_ways_2_sel; + decodeStage_mmuRsp_ways_2_physical <= io_cpu_fetch_mmuRsp_ways_2_physical; + decodeStage_mmuRsp_ways_3_sel <= io_cpu_fetch_mmuRsp_ways_3_sel; + decodeStage_mmuRsp_ways_3_physical <= io_cpu_fetch_mmuRsp_ways_3_physical; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + if((_zz_9 != 3'b000))begin + io_cpu_fetch_data_regNextWhen <= _zz_10; + end + end + + +endmodule diff --git a/BENCHMARK/vexriscv/vexriscv_small.v b/BENCHMARK/vexriscv/vexriscv_small.v new file mode 100644 index 0000000..2b4f567 --- /dev/null +++ b/BENCHMARK/vexriscv/vexriscv_small.v @@ -0,0 +1,3127 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : 36b3cd918896c94c4e8a224d97c559ab6dbf3ec9 + + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define EnvCtrlEnum_defaultEncoding_type [0:0] +`define EnvCtrlEnum_defaultEncoding_NONE 1'b0 +`define EnvCtrlEnum_defaultEncoding_XRET 1'b1 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv ( + output iBus_cmd_valid, + input iBus_cmd_ready, + output [31:0] iBus_cmd_payload_pc, + input iBus_rsp_valid, + input iBus_rsp_payload_error, + input [31:0] iBus_rsp_payload_inst, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [1:0] dBus_cmd_payload_size, + input dBus_rsp_ready, + input dBus_rsp_error, + input [31:0] dBus_rsp_data, + input clk, + input reset +); + wire _zz_107; + wire _zz_108; + reg [31:0] _zz_109; + reg [31:0] _zz_110; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_111; + wire _zz_112; + wire _zz_113; + wire _zz_114; + wire [1:0] _zz_115; + wire _zz_116; + wire _zz_117; + wire _zz_118; + wire _zz_119; + wire _zz_120; + wire _zz_121; + wire _zz_122; + wire _zz_123; + wire _zz_124; + wire _zz_125; + wire _zz_126; + wire _zz_127; + wire [1:0] _zz_128; + wire _zz_129; + wire [0:0] _zz_130; + wire [0:0] _zz_131; + wire [0:0] _zz_132; + wire [0:0] _zz_133; + wire [0:0] _zz_134; + wire [0:0] _zz_135; + wire [0:0] _zz_136; + wire [0:0] _zz_137; + wire [0:0] _zz_138; + wire [0:0] _zz_139; + wire [0:0] _zz_140; + wire [1:0] _zz_141; + wire [1:0] _zz_142; + wire [2:0] _zz_143; + wire [31:0] _zz_144; + wire [2:0] _zz_145; + wire [0:0] _zz_146; + wire [2:0] _zz_147; + wire [0:0] _zz_148; + wire [2:0] _zz_149; + wire [0:0] _zz_150; + wire [2:0] _zz_151; + wire [0:0] _zz_152; + wire [2:0] _zz_153; + wire [0:0] _zz_154; + wire [2:0] _zz_155; + wire [4:0] _zz_156; + wire [11:0] _zz_157; + wire [11:0] _zz_158; + wire [31:0] _zz_159; + wire [31:0] _zz_160; + wire [31:0] _zz_161; + wire [31:0] _zz_162; + wire [31:0] _zz_163; + wire [31:0] _zz_164; + wire [31:0] _zz_165; + wire [31:0] _zz_166; + wire [32:0] _zz_167; + wire [19:0] _zz_168; + wire [11:0] _zz_169; + wire [11:0] _zz_170; + wire [0:0] _zz_171; + wire [0:0] _zz_172; + wire [0:0] _zz_173; + wire [0:0] _zz_174; + wire [0:0] _zz_175; + wire [0:0] _zz_176; + wire _zz_177; + wire _zz_178; + wire [31:0] _zz_179; + wire [31:0] _zz_180; + wire [31:0] _zz_181; + wire [31:0] _zz_182; + wire _zz_183; + wire [1:0] _zz_184; + wire [1:0] _zz_185; + wire _zz_186; + wire [0:0] _zz_187; + wire [18:0] _zz_188; + wire [31:0] _zz_189; + wire [31:0] _zz_190; + wire [31:0] _zz_191; + wire [31:0] _zz_192; + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire [0:0] _zz_196; + wire [0:0] _zz_197; + wire _zz_198; + wire [0:0] _zz_199; + wire [15:0] _zz_200; + wire [31:0] _zz_201; + wire _zz_202; + wire _zz_203; + wire [0:0] _zz_204; + wire [0:0] _zz_205; + wire [0:0] _zz_206; + wire [0:0] _zz_207; + wire _zz_208; + wire [0:0] _zz_209; + wire [12:0] _zz_210; + wire [31:0] _zz_211; + wire [31:0] _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire [1:0] _zz_216; + wire [1:0] _zz_217; + wire _zz_218; + wire [0:0] _zz_219; + wire [9:0] _zz_220; + wire [31:0] _zz_221; + wire [31:0] _zz_222; + wire [31:0] _zz_223; + wire [31:0] _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire [0:0] _zz_228; + wire [0:0] _zz_229; + wire _zz_230; + wire [0:0] _zz_231; + wire [6:0] _zz_232; + wire [31:0] _zz_233; + wire [0:0] _zz_234; + wire [4:0] _zz_235; + wire [1:0] _zz_236; + wire [1:0] _zz_237; + wire _zz_238; + wire [0:0] _zz_239; + wire [3:0] _zz_240; + wire [31:0] _zz_241; + wire [31:0] _zz_242; + wire _zz_243; + wire [0:0] _zz_244; + wire [1:0] _zz_245; + wire [31:0] _zz_246; + wire [31:0] _zz_247; + wire _zz_248; + wire [0:0] _zz_249; + wire [2:0] _zz_250; + wire [0:0] _zz_251; + wire [0:0] _zz_252; + wire _zz_253; + wire [0:0] _zz_254; + wire [0:0] _zz_255; + wire [31:0] _zz_256; + wire _zz_257; + wire _zz_258; + wire [31:0] _zz_259; + wire [31:0] _zz_260; + wire [31:0] _zz_261; + wire _zz_262; + wire [0:0] _zz_263; + wire [0:0] _zz_264; + wire [31:0] _zz_265; + wire [31:0] _zz_266; + wire [0:0] _zz_267; + wire [1:0] _zz_268; + wire [1:0] _zz_269; + wire [1:0] _zz_270; + wire [1:0] _zz_271; + wire [1:0] _zz_272; + wire [31:0] _zz_273; + wire [31:0] _zz_274; + wire [31:0] _zz_275; + wire [31:0] _zz_276; + wire [31:0] _zz_277; + wire [31:0] _zz_278; + wire [31:0] _zz_279; + wire [31:0] _zz_280; + wire [31:0] _zz_281; + wire [31:0] _zz_282; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] decode_SRC2; + wire [31:0] decode_SRC1; + wire decode_SRC2_FORCE_ZERO; + wire [31:0] decode_RS2; + wire [31:0] decode_RS1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_1; + wire `BranchCtrlEnum_defaultEncoding_type _zz_2; + wire `BranchCtrlEnum_defaultEncoding_type _zz_3; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_4; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_5; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_6; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_7; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_8; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_9; + wire decode_SRC_LESS_UNSIGNED; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_10; + wire `AluCtrlEnum_defaultEncoding_type _zz_11; + wire `AluCtrlEnum_defaultEncoding_type _zz_12; + wire `EnvCtrlEnum_defaultEncoding_type _zz_13; + wire `EnvCtrlEnum_defaultEncoding_type _zz_14; + wire `EnvCtrlEnum_defaultEncoding_type _zz_15; + wire `EnvCtrlEnum_defaultEncoding_type _zz_16; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_17; + wire `EnvCtrlEnum_defaultEncoding_type _zz_18; + wire `EnvCtrlEnum_defaultEncoding_type _zz_19; + wire decode_IS_CSR; + wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire decode_MEMORY_ENABLE; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_20; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_21; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_22; + wire [31:0] _zz_23; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_24; + wire [31:0] _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_27; + wire [31:0] execute_SRC2; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_28; + wire [31:0] _zz_29; + wire _zz_30; + reg _zz_31; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire `BranchCtrlEnum_defaultEncoding_type _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_34; + wire `AluCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_defaultEncoding_type _zz_36; + wire `Src2CtrlEnum_defaultEncoding_type _zz_37; + wire `Src1CtrlEnum_defaultEncoding_type _zz_38; + reg [31:0] _zz_39; + wire [31:0] execute_SRC1; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_40; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_41; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_42; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_43; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + reg [31:0] _zz_44; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + wire decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + wire decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + wire execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusSimplePlugin_fetcherHalt; + reg IBusSimplePlugin_incomingInstruction; + wire IBusSimplePlugin_pcValids_0; + wire IBusSimplePlugin_pcValids_1; + wire IBusSimplePlugin_pcValids_2; + wire IBusSimplePlugin_pcValids_3; + wire CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire IBusSimplePlugin_externalFlush; + wire IBusSimplePlugin_jump_pcLoad_valid; + wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; + wire [1:0] _zz_45; + wire IBusSimplePlugin_fetchPc_output_valid; + wire IBusSimplePlugin_fetchPc_output_ready; + wire [31:0] IBusSimplePlugin_fetchPc_output_payload; + reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusSimplePlugin_fetchPc_correction; + reg IBusSimplePlugin_fetchPc_correctionReg; + wire IBusSimplePlugin_fetchPc_corrected; + reg IBusSimplePlugin_fetchPc_pcRegPropagate; + reg IBusSimplePlugin_fetchPc_booted; + reg IBusSimplePlugin_fetchPc_inc; + reg [31:0] IBusSimplePlugin_fetchPc_pc; + reg IBusSimplePlugin_fetchPc_flushed; + wire IBusSimplePlugin_iBusRsp_redoFetch; + wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; + reg IBusSimplePlugin_iBusRsp_stages_0_halt; + wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_halt; + wire _zz_46; + wire _zz_47; + wire IBusSimplePlugin_iBusRsp_flush; + wire _zz_48; + wire _zz_49; + reg _zz_50; + reg IBusSimplePlugin_iBusRsp_readyForError; + wire IBusSimplePlugin_iBusRsp_output_valid; + wire IBusSimplePlugin_iBusRsp_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; + wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + wire IBusSimplePlugin_iBusRsp_output_payload_isRvc; + wire IBusSimplePlugin_injector_decodeInput_valid; + wire IBusSimplePlugin_injector_decodeInput_ready; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; + wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; + reg _zz_51; + reg [31:0] _zz_52; + reg _zz_53; + reg [31:0] _zz_54; + reg _zz_55; + reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + reg IBusSimplePlugin_injector_nextPcCalc_valids_4; + reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; + wire IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_ready; + wire [31:0] IBusSimplePlugin_cmd_payload_pc; + wire IBusSimplePlugin_pending_inc; + wire IBusSimplePlugin_pending_dec; + reg [2:0] IBusSimplePlugin_pending_value; + wire [2:0] IBusSimplePlugin_pending_next; + wire IBusSimplePlugin_cmdFork_canEmit; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire IBusSimplePlugin_rspJoin_rspBuffer_flush; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; + reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire IBusSimplePlugin_rspJoin_join_valid; + wire IBusSimplePlugin_rspJoin_join_ready; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; + wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_payload_isRvc; + wire IBusSimplePlugin_rspJoin_exceptionDetected; + wire _zz_56; + wire _zz_57; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_58; + reg [3:0] _zz_59; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_60; + reg [31:0] _zz_61; + wire _zz_62; + reg [31:0] _zz_63; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + wire [1:0] CsrPlugin_mtvec_mode; + wire [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_64; + wire _zz_65; + wire _zz_66; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + wire [1:0] CsrPlugin_targetPrivilege; + wire [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + wire [24:0] _zz_67; + wire _zz_68; + wire _zz_69; + wire _zz_70; + wire _zz_71; + wire _zz_72; + wire `Src1CtrlEnum_defaultEncoding_type _zz_73; + wire `Src2CtrlEnum_defaultEncoding_type _zz_74; + wire `EnvCtrlEnum_defaultEncoding_type _zz_75; + wire `AluCtrlEnum_defaultEncoding_type _zz_76; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_77; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_78; + wire `BranchCtrlEnum_defaultEncoding_type _zz_79; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_80; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_81; + reg [31:0] _zz_82; + wire _zz_83; + reg [19:0] _zz_84; + wire _zz_85; + reg [19:0] _zz_86; + reg [31:0] _zz_87; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_88; + reg _zz_89; + reg _zz_90; + reg _zz_91; + reg [4:0] _zz_92; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_93; + reg _zz_94; + reg _zz_95; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_96; + reg [10:0] _zz_97; + wire _zz_98; + reg [19:0] _zz_99; + wire _zz_100; + reg [18:0] _zz_101; + reg [31:0] _zz_102; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg [31:0] decode_to_execute_SRC1; + reg [31:0] decode_to_execute_SRC2; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_834; + reg [31:0] _zz_103; + reg [31:0] _zz_104; + reg [31:0] _zz_105; + reg [31:0] _zz_106; + `ifndef SYNTHESIS + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_1_string; + reg [31:0] _zz_2_string; + reg [31:0] _zz_3_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_4_string; + reg [71:0] _zz_5_string; + reg [71:0] _zz_6_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_7_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_10_string; + reg [63:0] _zz_11_string; + reg [63:0] _zz_12_string; + reg [31:0] _zz_13_string; + reg [31:0] _zz_14_string; + reg [31:0] _zz_15_string; + reg [31:0] _zz_16_string; + reg [31:0] decode_ENV_CTRL_string; + reg [31:0] _zz_17_string; + reg [31:0] _zz_18_string; + reg [31:0] _zz_19_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_20_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_21_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_24_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_26_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_27_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_28_string; + reg [31:0] _zz_32_string; + reg [71:0] _zz_33_string; + reg [39:0] _zz_34_string; + reg [63:0] _zz_35_string; + reg [31:0] _zz_36_string; + reg [23:0] _zz_37_string; + reg [95:0] _zz_38_string; + reg [31:0] memory_ENV_CTRL_string; + reg [31:0] _zz_40_string; + reg [31:0] execute_ENV_CTRL_string; + reg [31:0] _zz_41_string; + reg [31:0] writeBack_ENV_CTRL_string; + reg [31:0] _zz_42_string; + reg [95:0] _zz_73_string; + reg [23:0] _zz_74_string; + reg [31:0] _zz_75_string; + reg [63:0] _zz_76_string; + reg [39:0] _zz_77_string; + reg [71:0] _zz_78_string; + reg [31:0] _zz_79_string; + reg [31:0] decode_to_execute_ENV_CTRL_string; + reg [31:0] execute_to_memory_ENV_CTRL_string; + reg [31:0] memory_to_writeBack_ENV_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_111 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_112 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_113 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_114 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_115 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_116 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_117 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_118 = (1'b1 || (! 1'b1)); + assign _zz_119 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_120 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_121 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_122 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_123 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_124 = ((_zz_64 && 1'b1) && (! 1'b0)); + assign _zz_125 = ((_zz_65 && 1'b1) && (! 1'b0)); + assign _zz_126 = ((_zz_66 && 1'b1) && (! 1'b0)); + assign _zz_127 = (! execute_arbitration_isStuckByOthers); + assign _zz_128 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_129 = execute_INSTRUCTION[13]; + assign _zz_130 = _zz_67[17 : 17]; + assign _zz_131 = _zz_67[12 : 12]; + assign _zz_132 = _zz_67[10 : 10]; + assign _zz_133 = _zz_67[9 : 9]; + assign _zz_134 = _zz_67[8 : 8]; + assign _zz_135 = _zz_67[3 : 3]; + assign _zz_136 = _zz_67[11 : 11]; + assign _zz_137 = _zz_67[4 : 4]; + assign _zz_138 = _zz_67[2 : 2]; + assign _zz_139 = _zz_67[20 : 20]; + assign _zz_140 = _zz_67[7 : 7]; + assign _zz_141 = (_zz_45 & (~ _zz_142)); + assign _zz_142 = (_zz_45 - 2'b01); + assign _zz_143 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_144 = {29'd0, _zz_143}; + assign _zz_145 = (IBusSimplePlugin_pending_value + _zz_147); + assign _zz_146 = IBusSimplePlugin_pending_inc; + assign _zz_147 = {2'd0, _zz_146}; + assign _zz_148 = IBusSimplePlugin_pending_dec; + assign _zz_149 = {2'd0, _zz_148}; + assign _zz_150 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_151 = {2'd0, _zz_150}; + assign _zz_152 = IBusSimplePlugin_pending_dec; + assign _zz_153 = {2'd0, _zz_152}; + assign _zz_154 = execute_SRC_LESS; + assign _zz_155 = 3'b100; + assign _zz_156 = decode_INSTRUCTION[19 : 15]; + assign _zz_157 = decode_INSTRUCTION[31 : 20]; + assign _zz_158 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_159 = ($signed(_zz_160) + $signed(_zz_163)); + assign _zz_160 = ($signed(_zz_161) + $signed(_zz_162)); + assign _zz_161 = execute_SRC1; + assign _zz_162 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_163 = (execute_SRC_USE_SUB_LESS ? _zz_164 : _zz_165); + assign _zz_164 = 32'h00000001; + assign _zz_165 = 32'h0; + assign _zz_166 = (_zz_167 >>> 1); + assign _zz_167 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_168 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_169 = execute_INSTRUCTION[31 : 20]; + assign _zz_170 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_171 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_172 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_173 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_174 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_175 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_176 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_177 = 1'b1; + assign _zz_178 = 1'b1; + assign _zz_179 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_180 = 32'h00000004; + assign _zz_181 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_182 = 32'h00000040; + assign _zz_183 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); + assign _zz_184 = {(_zz_189 == _zz_190),(_zz_191 == _zz_192)}; + assign _zz_185 = 2'b00; + assign _zz_186 = ({_zz_193,_zz_194} != 2'b00); + assign _zz_187 = (_zz_195 != 1'b0); + assign _zz_188 = {(_zz_196 != _zz_197),{_zz_198,{_zz_199,_zz_200}}}; + assign _zz_189 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_190 = 32'h40001010; + assign _zz_191 = (decode_INSTRUCTION & 32'h00007054); + assign _zz_192 = 32'h00001010; + assign _zz_193 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_194 = ((decode_INSTRUCTION & 32'h00003054) == 32'h00001010); + assign _zz_195 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_196 = ((decode_INSTRUCTION & _zz_201) == 32'h00002000); + assign _zz_197 = 1'b0; + assign _zz_198 = ({_zz_202,_zz_203} != 2'b00); + assign _zz_199 = ({_zz_204,_zz_205} != 2'b00); + assign _zz_200 = {(_zz_206 != _zz_207),{_zz_208,{_zz_209,_zz_210}}}; + assign _zz_201 = 32'h00003000; + assign _zz_202 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_203 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_204 = ((decode_INSTRUCTION & _zz_211) == 32'h00006000); + assign _zz_205 = ((decode_INSTRUCTION & _zz_212) == 32'h00004000); + assign _zz_206 = _zz_69; + assign _zz_207 = 1'b0; + assign _zz_208 = ({_zz_213,_zz_214} != 2'b00); + assign _zz_209 = (_zz_215 != 1'b0); + assign _zz_210 = {(_zz_216 != _zz_217),{_zz_218,{_zz_219,_zz_220}}}; + assign _zz_211 = 32'h00006004; + assign _zz_212 = 32'h00005004; + assign _zz_213 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_214 = ((decode_INSTRUCTION & 32'h00003040) == 32'h00000040); + assign _zz_215 = ((decode_INSTRUCTION & 32'h00003050) == 32'h00000050); + assign _zz_216 = {(_zz_221 == _zz_222),(_zz_223 == _zz_224)}; + assign _zz_217 = 2'b00; + assign _zz_218 = ({_zz_225,_zz_226} != 2'b00); + assign _zz_219 = (_zz_227 != 1'b0); + assign _zz_220 = {(_zz_228 != _zz_229),{_zz_230,{_zz_231,_zz_232}}}; + assign _zz_221 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_222 = 32'h00001050; + assign _zz_223 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_224 = 32'h00002050; + assign _zz_225 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_226 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_227 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_228 = ((decode_INSTRUCTION & _zz_233) == 32'h00000010); + assign _zz_229 = 1'b0; + assign _zz_230 = (_zz_71 != 1'b0); + assign _zz_231 = ({_zz_234,_zz_235} != 6'h0); + assign _zz_232 = {(_zz_236 != _zz_237),{_zz_238,{_zz_239,_zz_240}}}; + assign _zz_233 = 32'h00000010; + assign _zz_234 = _zz_72; + assign _zz_235 = {(_zz_241 == _zz_242),{_zz_243,{_zz_244,_zz_245}}}; + assign _zz_236 = {_zz_70,(_zz_246 == _zz_247)}; + assign _zz_237 = 2'b00; + assign _zz_238 = ({_zz_70,_zz_248} != 2'b00); + assign _zz_239 = ({_zz_249,_zz_250} != 4'b0000); + assign _zz_240 = {(_zz_251 != _zz_252),{_zz_253,{_zz_254,_zz_255}}}; + assign _zz_241 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_242 = 32'h00001010; + assign _zz_243 = ((decode_INSTRUCTION & _zz_256) == 32'h00002010); + assign _zz_244 = _zz_71; + assign _zz_245 = {_zz_257,_zz_258}; + assign _zz_246 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_247 = 32'h00000020; + assign _zz_248 = ((decode_INSTRUCTION & _zz_259) == 32'h0); + assign _zz_249 = (_zz_260 == _zz_261); + assign _zz_250 = {_zz_262,{_zz_263,_zz_264}}; + assign _zz_251 = (_zz_265 == _zz_266); + assign _zz_252 = 1'b0; + assign _zz_253 = ({_zz_267,_zz_268} != 3'b000); + assign _zz_254 = (_zz_269 != _zz_270); + assign _zz_255 = (_zz_271 != _zz_272); + assign _zz_256 = 32'h00002010; + assign _zz_257 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_258 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_259 = 32'h00000020; + assign _zz_260 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_261 = 32'h0; + assign _zz_262 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); + assign _zz_263 = _zz_69; + assign _zz_264 = ((decode_INSTRUCTION & _zz_273) == 32'h00001000); + assign _zz_265 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_266 = 32'h0; + assign _zz_267 = ((decode_INSTRUCTION & _zz_274) == 32'h00000040); + assign _zz_268 = {(_zz_275 == _zz_276),(_zz_277 == _zz_278)}; + assign _zz_269 = {(_zz_279 == _zz_280),_zz_68}; + assign _zz_270 = 2'b00; + assign _zz_271 = {(_zz_281 == _zz_282),_zz_68}; + assign _zz_272 = 2'b00; + assign _zz_273 = 32'h00005004; + assign _zz_274 = 32'h00000044; + assign _zz_275 = (decode_INSTRUCTION & 32'h00002014); + assign _zz_276 = 32'h00002010; + assign _zz_277 = (decode_INSTRUCTION & 32'h40004034); + assign _zz_278 = 32'h40000030; + assign _zz_279 = (decode_INSTRUCTION & 32'h00000014); + assign _zz_280 = 32'h00000004; + assign _zz_281 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_282 = 32'h00000004; + always @ (posedge clk) begin + if(_zz_177) begin + _zz_109 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_178) begin + _zz_110 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_31) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_push_valid (iBus_rsp_valid ), //i + .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o + .io_push_payload_error (iBus_rsp_payload_error ), //i + .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i + .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o + .io_pop_ready (_zz_107 ), //i + .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o + .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o + .io_flush (_zz_108 ), //i + .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_1) + `BranchCtrlEnum_defaultEncoding_INC : _zz_1_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_1_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_1_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_1_string = "JALR"; + default : _zz_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_2) + `BranchCtrlEnum_defaultEncoding_INC : _zz_2_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_2_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_2_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_2_string = "JALR"; + default : _zz_2_string = "????"; + endcase + end + always @(*) begin + case(_zz_3) + `BranchCtrlEnum_defaultEncoding_INC : _zz_3_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_3_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_3_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_3_string = "JALR"; + default : _zz_3_string = "????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_4) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_4_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_4_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_4_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_4_string = "SRA_1 "; + default : _zz_4_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_5) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_5_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_5_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_5_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_5_string = "SRA_1 "; + default : _zz_5_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_6) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_6_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_6_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_6_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_6_string = "SRA_1 "; + default : _zz_6_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_7_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_7_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_7_string = "AND_1"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_8_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_8_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_8_string = "AND_1"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_9_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_9_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_9_string = "AND_1"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_10) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_10_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_10_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_10_string = "BITWISE "; + default : _zz_10_string = "????????"; + endcase + end + always @(*) begin + case(_zz_11) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_11_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_11_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_11_string = "BITWISE "; + default : _zz_11_string = "????????"; + endcase + end + always @(*) begin + case(_zz_12) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_12_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_12_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_12_string = "BITWISE "; + default : _zz_12_string = "????????"; + endcase + end + always @(*) begin + case(_zz_13) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_13_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_13_string = "XRET"; + default : _zz_13_string = "????"; + endcase + end + always @(*) begin + case(_zz_14) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_14_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_14_string = "XRET"; + default : _zz_14_string = "????"; + endcase + end + always @(*) begin + case(_zz_15) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_15_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_15_string = "XRET"; + default : _zz_15_string = "????"; + endcase + end + always @(*) begin + case(_zz_16) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_16_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_16_string = "XRET"; + default : _zz_16_string = "????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET"; + default : decode_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_17) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_17_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_17_string = "XRET"; + default : _zz_17_string = "????"; + endcase + end + always @(*) begin + case(_zz_18) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_18_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_18_string = "XRET"; + default : _zz_18_string = "????"; + endcase + end + always @(*) begin + case(_zz_19) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_19_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_19_string = "XRET"; + default : _zz_19_string = "????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_20) + `BranchCtrlEnum_defaultEncoding_INC : _zz_20_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_20_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_20_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_20_string = "JALR"; + default : _zz_20_string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_21) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21_string = "SRA_1 "; + default : _zz_21_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_24) + `Src2CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_24_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_24_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_24_string = "PC "; + default : _zz_24_string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_27) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_27_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_27_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_27_string = "BITWISE "; + default : _zz_27_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_28) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_28_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_28_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_28_string = "AND_1"; + default : _zz_28_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32) + `BranchCtrlEnum_defaultEncoding_INC : _zz_32_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_32_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_32_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_32_string = "JALR"; + default : _zz_32_string = "????"; + endcase + end + always @(*) begin + case(_zz_33) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; + default : _zz_33_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_34) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_34_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_34_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_34_string = "AND_1"; + default : _zz_34_string = "?????"; + endcase + end + always @(*) begin + case(_zz_35) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_35_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_35_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_35_string = "BITWISE "; + default : _zz_35_string = "????????"; + endcase + end + always @(*) begin + case(_zz_36) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_36_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_36_string = "XRET"; + default : _zz_36_string = "????"; + endcase + end + always @(*) begin + case(_zz_37) + `Src2CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_37_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_37_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_37_string = "PC "; + default : _zz_37_string = "???"; + endcase + end + always @(*) begin + case(_zz_38) + `Src1CtrlEnum_defaultEncoding_RS : _zz_38_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_38_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_38_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_38_string = "URS1 "; + default : _zz_38_string = "????????????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET"; + default : memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_40) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_40_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_40_string = "XRET"; + default : _zz_40_string = "????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET"; + default : execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_41) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_41_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_41_string = "XRET"; + default : _zz_41_string = "????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET"; + default : writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_42) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_42_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_42_string = "XRET"; + default : _zz_42_string = "????"; + endcase + end + always @(*) begin + case(_zz_73) + `Src1CtrlEnum_defaultEncoding_RS : _zz_73_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_73_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_73_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_73_string = "URS1 "; + default : _zz_73_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_74) + `Src2CtrlEnum_defaultEncoding_RS : _zz_74_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_74_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_74_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_74_string = "PC "; + default : _zz_74_string = "???"; + endcase + end + always @(*) begin + case(_zz_75) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_75_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_75_string = "XRET"; + default : _zz_75_string = "????"; + endcase + end + always @(*) begin + case(_zz_76) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_76_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_76_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_76_string = "BITWISE "; + default : _zz_76_string = "????????"; + endcase + end + always @(*) begin + case(_zz_77) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_77_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_77_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_77_string = "AND_1"; + default : _zz_77_string = "?????"; + endcase + end + always @(*) begin + case(_zz_78) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_78_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_78_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_78_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_78_string = "SRA_1 "; + default : _zz_78_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_79) + `BranchCtrlEnum_defaultEncoding_INC : _zz_79_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_79_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_79_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_79_string = "JALR"; + default : _zz_79_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; + default : decode_to_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; + default : execute_to_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; + default : memory_to_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + `endif + + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_95; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_81; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_SRC2 = _zz_87; + assign decode_SRC1 = _zz_82; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_RS2 = decode_RegFilePlugin_rs2Data; + assign decode_RS1 = decode_RegFilePlugin_rs1Data; + assign decode_BRANCH_CTRL = _zz_1; + assign _zz_2 = _zz_3; + assign decode_SHIFT_CTRL = _zz_4; + assign _zz_5 = _zz_6; + assign decode_ALU_BITWISE_CTRL = _zz_7; + assign _zz_8 = _zz_9; + assign decode_SRC_LESS_UNSIGNED = _zz_130[0]; + assign decode_ALU_CTRL = _zz_10; + assign _zz_11 = _zz_12; + assign _zz_13 = _zz_14; + assign _zz_15 = _zz_16; + assign decode_ENV_CTRL = _zz_17; + assign _zz_18 = _zz_19; + assign decode_IS_CSR = _zz_131[0]; + assign decode_MEMORY_STORE = _zz_132[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_133[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_134[0]; + assign decode_MEMORY_ENABLE = _zz_135[0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_CTRL = _zz_20; + assign decode_RS2_USE = _zz_136[0]; + assign decode_RS1_USE = _zz_137[0]; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign execute_SHIFT_CTRL = _zz_21; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_22 = decode_PC; + assign _zz_23 = decode_RS2; + assign decode_SRC2_CTRL = _zz_24; + assign _zz_25 = decode_RS1; + assign decode_SRC1_CTRL = _zz_26; + assign decode_SRC_USE_SUB_LESS = _zz_138[0]; + assign decode_SRC_ADD_ZERO = _zz_139[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_27; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_ALU_BITWISE_CTRL = _zz_28; + assign _zz_29 = writeBack_INSTRUCTION; + assign _zz_30 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_31 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_31 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_140[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + always @ (*) begin + _zz_39 = execute_REGFILE_WRITE_DATA; + if(_zz_111)begin + _zz_39 = execute_CsrPlugin_readData; + end + if(_zz_112)begin + _zz_39 = _zz_88; + end + end + + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_40; + assign execute_ENV_CTRL = _zz_41; + assign writeBack_ENV_CTRL = _zz_42; + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + always @ (*) begin + _zz_43 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_43 = writeBack_DBusSimplePlugin_rspFormated; + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = 1'b0; + always @ (*) begin + _zz_44 = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_44 = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + assign decode_arbitration_haltItself = 1'b0; + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + if((decode_arbitration_isValid && (_zz_89 || _zz_90)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + assign decode_arbitration_flushNext = 1'b0; + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_57)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_111)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_112)begin + if((! execute_LightShifterPlugin_done))begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + assign execute_arbitration_flushNext = 1'b0; + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(_zz_113)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_114)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusSimplePlugin_fetcherHalt = 1'b0; + if(_zz_113)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_114)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_incomingInstruction = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + end + + assign CsrPlugin_inWfi = 1'b0; + assign CsrPlugin_thirdPartyWake = 1'b0; + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_113)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_114)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_113)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_114)begin + case(_zz_115) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusSimplePlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid} != 2'b00); + assign _zz_45 = {BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}; + assign IBusSimplePlugin_jump_pcLoad_payload = (_zz_141[0] ? CsrPlugin_jumpInterface_payload : BranchPlugin_jumpInterface_payload); + always @ (*) begin + IBusSimplePlugin_fetchPc_correction = 1'b0; + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); + always @ (*) begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_144); + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; + end + IBusSimplePlugin_fetchPc_pc[0] = 1'b0; + IBusSimplePlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_flushed = 1'b0; + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); + assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; + assign IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; + assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; + assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; + assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; + always @ (*) begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_46 = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_46); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_46); + assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; + assign _zz_47 = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_47); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_47); + assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_48; + assign _zz_48 = ((1'b0 && (! _zz_49)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_49 = _zz_50; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_49; + assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; + always @ (*) begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b1; + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + if((! IBusSimplePlugin_pcValids_0))begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_51; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_52; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_53; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_54; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_55; + assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; + assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; + assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; + assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; + assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; + assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; + assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; + assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; + assign IBusSimplePlugin_pending_next = (_zz_145 - _zz_149); + assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); + assign IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); + assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_0_input_payload[31 : 2],2'b00}; + assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign _zz_107 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_107); + assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; + always @ (*) begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; + end + end + + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; + assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign _zz_56 = (! IBusSimplePlugin_rspJoin_exceptionDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_56); + assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_56); + assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; + assign _zz_57 = 1'b0; + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_57)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_58 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_58 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_58 = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_58; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_59 = 4'b0001; + end + 2'b01 : begin + _zz_59 = 4'b0011; + end + default : begin + _zz_59 = 4'b1111; + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_59 <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_60 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_61[31] = _zz_60; + _zz_61[30] = _zz_60; + _zz_61[29] = _zz_60; + _zz_61[28] = _zz_60; + _zz_61[27] = _zz_60; + _zz_61[26] = _zz_60; + _zz_61[25] = _zz_60; + _zz_61[24] = _zz_60; + _zz_61[23] = _zz_60; + _zz_61[22] = _zz_60; + _zz_61[21] = _zz_60; + _zz_61[20] = _zz_60; + _zz_61[19] = _zz_60; + _zz_61[18] = _zz_60; + _zz_61[17] = _zz_60; + _zz_61[16] = _zz_60; + _zz_61[15] = _zz_60; + _zz_61[14] = _zz_60; + _zz_61[13] = _zz_60; + _zz_61[12] = _zz_60; + _zz_61[11] = _zz_60; + _zz_61[10] = _zz_60; + _zz_61[9] = _zz_60; + _zz_61[8] = _zz_60; + _zz_61[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_62 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_63[31] = _zz_62; + _zz_63[30] = _zz_62; + _zz_63[29] = _zz_62; + _zz_63[28] = _zz_62; + _zz_63[27] = _zz_62; + _zz_63[26] = _zz_62; + _zz_63[25] = _zz_62; + _zz_63[24] = _zz_62; + _zz_63[23] = _zz_62; + _zz_63[22] = _zz_62; + _zz_63[21] = _zz_62; + _zz_63[20] = _zz_62; + _zz_63[19] = _zz_62; + _zz_63[18] = _zz_62; + _zz_63[17] = _zz_62; + _zz_63[16] = _zz_62; + _zz_63[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_128) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_61; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_63; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign CsrPlugin_mtvec_mode = 2'b00; + assign CsrPlugin_mtvec_base = 30'h00000008; + assign _zz_64 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_65 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_66 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exception = 1'b0; + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + assign CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + assign CsrPlugin_trapCause = CsrPlugin_interrupt_code; + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_116)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_116)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_116)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_129) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_68 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_69 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_70 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_71 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz_72 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_67 = {({_zz_72,(_zz_179 == _zz_180)} != 2'b00),{((_zz_181 == _zz_182) != 1'b0),{(_zz_183 != 1'b0),{(_zz_184 != _zz_185),{_zz_186,{_zz_187,_zz_188}}}}}}; + assign _zz_73 = _zz_67[1 : 0]; + assign _zz_38 = _zz_73; + assign _zz_74 = _zz_67[6 : 5]; + assign _zz_37 = _zz_74; + assign _zz_75 = _zz_67[13 : 13]; + assign _zz_36 = _zz_75; + assign _zz_76 = _zz_67[16 : 15]; + assign _zz_35 = _zz_76; + assign _zz_77 = _zz_67[19 : 18]; + assign _zz_34 = _zz_77; + assign _zz_78 = _zz_67[22 : 21]; + assign _zz_33 = _zz_78; + assign _zz_79 = _zz_67[24 : 23]; + assign _zz_32 = _zz_79; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_109; + assign decode_RegFilePlugin_rs2Data = _zz_110; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_30 && writeBack_arbitration_isFiring); + if(_zz_80)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_29[11 : 7]; + if(_zz_80)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_43; + if(_zz_80)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_81 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_81 = {31'd0, _zz_154}; + end + default : begin + _zz_81 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_82 = _zz_25; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_82 = {29'd0, _zz_155}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_82 = {decode_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_82 = {27'd0, _zz_156}; + end + endcase + end + + assign _zz_83 = _zz_157[11]; + always @ (*) begin + _zz_84[19] = _zz_83; + _zz_84[18] = _zz_83; + _zz_84[17] = _zz_83; + _zz_84[16] = _zz_83; + _zz_84[15] = _zz_83; + _zz_84[14] = _zz_83; + _zz_84[13] = _zz_83; + _zz_84[12] = _zz_83; + _zz_84[11] = _zz_83; + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7] = _zz_83; + _zz_84[6] = _zz_83; + _zz_84[5] = _zz_83; + _zz_84[4] = _zz_83; + _zz_84[3] = _zz_83; + _zz_84[2] = _zz_83; + _zz_84[1] = _zz_83; + _zz_84[0] = _zz_83; + end + + assign _zz_85 = _zz_158[11]; + always @ (*) begin + _zz_86[19] = _zz_85; + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15] = _zz_85; + _zz_86[14] = _zz_85; + _zz_86[13] = _zz_85; + _zz_86[12] = _zz_85; + _zz_86[11] = _zz_85; + _zz_86[10] = _zz_85; + _zz_86[9] = _zz_85; + _zz_86[8] = _zz_85; + _zz_86[7] = _zz_85; + _zz_86[6] = _zz_85; + _zz_86[5] = _zz_85; + _zz_86[4] = _zz_85; + _zz_86[3] = _zz_85; + _zz_86[2] = _zz_85; + _zz_86[1] = _zz_85; + _zz_86[0] = _zz_85; + end + + always @ (*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_87 = _zz_23; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_87 = {_zz_84,decode_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_87 = {_zz_86,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_87 = _zz_22; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_159; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_88 = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_88 = _zz_166; + end + endcase + end + + always @ (*) begin + _zz_89 = 1'b0; + if(_zz_91)begin + if((_zz_92 == decode_INSTRUCTION[19 : 15]))begin + _zz_89 = 1'b1; + end + end + if(_zz_117)begin + if(_zz_118)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_89 = 1'b1; + end + end + end + if(_zz_119)begin + if(_zz_120)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_89 = 1'b1; + end + end + end + if(_zz_121)begin + if(_zz_122)begin + if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_89 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_89 = 1'b0; + end + end + + always @ (*) begin + _zz_90 = 1'b0; + if(_zz_91)begin + if((_zz_92 == decode_INSTRUCTION[24 : 20]))begin + _zz_90 = 1'b1; + end + end + if(_zz_117)begin + if(_zz_118)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_90 = 1'b1; + end + end + end + if(_zz_119)begin + if(_zz_120)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_90 = 1'b1; + end + end + end + if(_zz_121)begin + if(_zz_122)begin + if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_90 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_90 = 1'b0; + end + end + + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_93 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_93 == 3'b000)) begin + _zz_94 = execute_BranchPlugin_eq; + end else if((_zz_93 == 3'b001)) begin + _zz_94 = (! execute_BranchPlugin_eq); + end else if((((_zz_93 & 3'b101) == 3'b101))) begin + _zz_94 = (! execute_SRC_LESS); + end else begin + _zz_94 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_95 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_95 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_95 = 1'b1; + end + default : begin + _zz_95 = _zz_94; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_96 = _zz_168[19]; + always @ (*) begin + _zz_97[10] = _zz_96; + _zz_97[9] = _zz_96; + _zz_97[8] = _zz_96; + _zz_97[7] = _zz_96; + _zz_97[6] = _zz_96; + _zz_97[5] = _zz_96; + _zz_97[4] = _zz_96; + _zz_97[3] = _zz_96; + _zz_97[2] = _zz_96; + _zz_97[1] = _zz_96; + _zz_97[0] = _zz_96; + end + + assign _zz_98 = _zz_169[11]; + always @ (*) begin + _zz_99[19] = _zz_98; + _zz_99[18] = _zz_98; + _zz_99[17] = _zz_98; + _zz_99[16] = _zz_98; + _zz_99[15] = _zz_98; + _zz_99[14] = _zz_98; + _zz_99[13] = _zz_98; + _zz_99[12] = _zz_98; + _zz_99[11] = _zz_98; + _zz_99[10] = _zz_98; + _zz_99[9] = _zz_98; + _zz_99[8] = _zz_98; + _zz_99[7] = _zz_98; + _zz_99[6] = _zz_98; + _zz_99[5] = _zz_98; + _zz_99[4] = _zz_98; + _zz_99[3] = _zz_98; + _zz_99[2] = _zz_98; + _zz_99[1] = _zz_98; + _zz_99[0] = _zz_98; + end + + assign _zz_100 = _zz_170[11]; + always @ (*) begin + _zz_101[18] = _zz_100; + _zz_101[17] = _zz_100; + _zz_101[16] = _zz_100; + _zz_101[15] = _zz_100; + _zz_101[14] = _zz_100; + _zz_101[13] = _zz_100; + _zz_101[12] = _zz_100; + _zz_101[11] = _zz_100; + _zz_101[10] = _zz_100; + _zz_101[9] = _zz_100; + _zz_101[8] = _zz_100; + _zz_101[7] = _zz_100; + _zz_101[6] = _zz_100; + _zz_101[5] = _zz_100; + _zz_101[4] = _zz_100; + _zz_101[3] = _zz_100; + _zz_101[2] = _zz_100; + _zz_101[1] = _zz_100; + _zz_101[0] = _zz_100; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_102 = {{_zz_97,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_102 = {_zz_99,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_102 = {{_zz_101,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_102; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign _zz_26 = _zz_38; + assign _zz_24 = _zz_37; + assign _zz_19 = decode_ENV_CTRL; + assign _zz_16 = execute_ENV_CTRL; + assign _zz_14 = memory_ENV_CTRL; + assign _zz_17 = _zz_36; + assign _zz_41 = decode_to_execute_ENV_CTRL; + assign _zz_40 = execute_to_memory_ENV_CTRL; + assign _zz_42 = memory_to_writeBack_ENV_CTRL; + assign _zz_12 = decode_ALU_CTRL; + assign _zz_10 = _zz_35; + assign _zz_27 = decode_to_execute_ALU_CTRL; + assign _zz_9 = decode_ALU_BITWISE_CTRL; + assign _zz_7 = _zz_34; + assign _zz_28 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_6 = decode_SHIFT_CTRL; + assign _zz_4 = _zz_33; + assign _zz_21 = decode_to_execute_SHIFT_CTRL; + assign _zz_3 = decode_BRANCH_CTRL; + assign _zz_1 = _zz_32; + assign _zz_20 = decode_to_execute_BRANCH_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + _zz_103 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_103[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_103[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_103[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_104 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_104[11 : 11] = CsrPlugin_mip_MEIP; + _zz_104[7 : 7] = CsrPlugin_mip_MTIP; + _zz_104[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_105 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_105[11 : 11] = CsrPlugin_mie_MEIE; + _zz_105[7 : 7] = CsrPlugin_mie_MTIE; + _zz_105[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_106 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_106[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_106[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + assign execute_CsrPlugin_readData = ((_zz_103 | _zz_104) | (_zz_105 | _zz_106)); + assign _zz_108 = 1'b0; + always @ (posedge clk or posedge reset) begin + if (reset) begin + IBusSimplePlugin_fetchPc_pcReg <= 32'h80000000; + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + IBusSimplePlugin_fetchPc_booted <= 1'b0; + IBusSimplePlugin_fetchPc_inc <= 1'b0; + _zz_50 <= 1'b0; + _zz_51 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusSimplePlugin_pending_value <= 3'b000; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + _zz_80 <= 1'b1; + execute_LightShifterPlugin_isActive <= 1'b0; + _zz_91 <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + end else begin + if(IBusSimplePlugin_fetchPc_correction)begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + end + IBusSimplePlugin_fetchPc_booted <= 1'b1; + if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin + IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + end + if(IBusSimplePlugin_iBusRsp_flush)begin + _zz_50 <= 1'b0; + end + if(_zz_48)begin + _zz_50 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(decode_arbitration_removeIt)begin + _zz_51 <= 1'b0; + end + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_51 <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_151); + if(IBusSimplePlugin_iBusRsp_flush)begin + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_153); + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_123)begin + if(_zz_124)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_125)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_126)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_113)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_114)begin + case(_zz_115) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_66,{_zz_65,_zz_64}} != 3'b000) || CsrPlugin_thirdPartyWake); + _zz_80 <= 1'b0; + if(_zz_112)begin + if(_zz_127)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + _zz_91 <= (_zz_30 && writeBack_arbitration_isFiring); + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_171[0]; + CsrPlugin_mstatus_MIE <= _zz_172[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_174[0]; + CsrPlugin_mie_MTIE <= _zz_175[0]; + CsrPlugin_mie_MSIE <= _zz_176[0]; + end + end + end + end + + always @ (posedge clk) begin + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_52 <= IBusSimplePlugin_iBusRsp_output_payload_pc; + _zz_53 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + _zz_54 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + _zz_55 <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; + end + if(IBusSimplePlugin_injector_decodeInput_ready)begin + IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_123)begin + if(_zz_124)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_125)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_126)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_113)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= decode_PC; + end + default : begin + end + endcase + end + if(_zz_112)begin + if(_zz_127)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); + end + end + _zz_92 <= _zz_29[11 : 7]; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= _zz_22; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= execute_PC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_44; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_18; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_15; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_13; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_8; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_5; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= _zz_23; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1 <= decode_SRC1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2 <= decode_SRC2; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_39; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_173[0]; + end + end + end + + +endmodule + +module StreamFifoLowLatency ( + input io_push_valid, + output io_push_ready, + input io_push_payload_error, + input [31:0] io_push_payload_inst, + output reg io_pop_valid, + input io_pop_ready, + output reg io_pop_payload_error, + output reg [31:0] io_pop_payload_inst, + input io_flush, + output [0:0] io_occupancy, + input clk, + input reset +); + wire _zz_4; + wire [0:0] _zz_5; + reg _zz_1; + reg pushPtr_willIncrement; + reg pushPtr_willClear; + wire pushPtr_willOverflowIfInc; + wire pushPtr_willOverflow; + reg popPtr_willIncrement; + reg popPtr_willClear; + wire popPtr_willOverflowIfInc; + wire popPtr_willOverflow; + wire ptrMatch; + reg risingOccupancy; + wire empty; + wire full; + wire pushing; + wire popping; + wire [32:0] _zz_2; + reg [32:0] _zz_3; + + assign _zz_4 = (! empty); + assign _zz_5 = _zz_2[0 : 0]; + always @ (*) begin + _zz_1 = 1'b0; + if(pushing)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + pushPtr_willIncrement = 1'b0; + if(pushing)begin + pushPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + pushPtr_willClear = 1'b0; + if(io_flush)begin + pushPtr_willClear = 1'b1; + end + end + + assign pushPtr_willOverflowIfInc = 1'b1; + assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); + always @ (*) begin + popPtr_willIncrement = 1'b0; + if(popping)begin + popPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + popPtr_willClear = 1'b0; + if(io_flush)begin + popPtr_willClear = 1'b1; + end + end + + assign popPtr_willOverflowIfInc = 1'b1; + assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); + assign ptrMatch = 1'b1; + assign empty = (ptrMatch && (! risingOccupancy)); + assign full = (ptrMatch && risingOccupancy); + assign pushing = (io_push_valid && io_push_ready); + assign popping = (io_pop_valid && io_pop_ready); + assign io_push_ready = (! full); + always @ (*) begin + if(_zz_4)begin + io_pop_valid = 1'b1; + end else begin + io_pop_valid = io_push_valid; + end + end + + assign _zz_2 = _zz_3; + always @ (*) begin + if(_zz_4)begin + io_pop_payload_error = _zz_5[0]; + end else begin + io_pop_payload_error = io_push_payload_error; + end + end + + always @ (*) begin + if(_zz_4)begin + io_pop_payload_inst = _zz_2[32 : 1]; + end else begin + io_pop_payload_inst = io_push_payload_inst; + end + end + + assign io_occupancy = (risingOccupancy && ptrMatch); + always @ (posedge clk or posedge reset) begin + if (reset) begin + risingOccupancy <= 1'b0; + end else begin + if((pushing != popping))begin + risingOccupancy <= pushing; + end + if(io_flush)begin + risingOccupancy <= 1'b0; + end + end + end + + always @ (posedge clk) begin + if(_zz_1)begin + _zz_3 <= {io_push_payload_inst,io_push_payload_error}; + end + end + + +endmodule diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_arch_exploration.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_arch_exploration.openfpga new file mode 100644 index 0000000..272b369 --- /dev/null +++ b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_arch_exploration.openfpga @@ -0,0 +1,74 @@ +# This script is designed to generate Verilog testbenches +# with a fixed device layout +# It will only output netlists to be used by verification tools +# including +# - Verilog testbenches, used by ModelSim +# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime +# +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin #--verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file arch_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench \ + --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} \ + --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ + --print_top_testbench \ +# --print_preconfig_top_testbench \ disabled for now due to disk space limitation on github actions + --print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \ + --explicit_port_mapping +# Exclude signal initialization since it does not help simulator converge +# due to the lack of reset pins for flip-flops +#--include_signal_init + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_auto_clock.xml b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_auto_clock.xml new file mode 100644 index 0000000..d9f8401 --- /dev/null +++ b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_auto_clock.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SCRIPT/repo_setup.py b/SCRIPT/repo_setup.py index a2a988a..38cd7fb 100644 --- a/SCRIPT/repo_setup.py +++ b/SCRIPT/repo_setup.py @@ -26,6 +26,9 @@ parser = argparse.ArgumentParser(description='Setup repository'); parser.add_argument('--openfpga_root_path', default='../OpenFPGA', help='Specify the root directory of OpenFPGA project'); +parser.add_argument('--noruns', + action='store_true', + help='Just setup SOFA, don\'t do task runs'); args = parser.parse_args(); ##################################################################### @@ -116,19 +119,22 @@ logging.info("Processed for " + str(num_task_config_file_processed) + "openfpga openfpga_task_src_dir = skywater_openfpga_homepath + "/SCRIPT/skywater_openfpga_task"; openfpga_task_des_dir = openfpga_root_path + "/openfpga_flow/tasks/skywater_openfpga_task"; -if (os.path.isdir(openfpga_task_des_dir) or os.path.isfile(openfpga_task_des_dir)): - logging.warning("There is already a skywater_openfpga_task directory/file at " + openfpga_task_des_dir); - logging.error("Failed to create symbolic link!"); - exit(1); -elif (os.path.islink(openfpga_task_des_dir)): +if (os.path.islink(openfpga_task_des_dir)): logging.warning("There is already a skywater_openfpga_task symbolic link at " + openfpga_task_des_dir); os.unlink(openfpga_task_des_dir); logging.warning("Removed the symbolic link"); +elif (os.path.isdir(openfpga_task_des_dir) or os.path.isfile(openfpga_task_des_dir)): + logging.warning("There is already a skywater_openfpga_task directory/file at " + openfpga_task_des_dir); + logging.error("Failed to create symbolic link!"); + exit(1); os.symlink(openfpga_task_src_dir, openfpga_task_des_dir, True); logging.info("Created OpenFPGA task symbolic link at " + openfpga_task_des_dir); +if (args.noruns): + exit(0); + ##################################################################### # Execute openfpga task runs ##################################################################### diff --git a/SCRIPT/skywater_openfpga_task/vexriscv/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/vexriscv/generate_testbench/config/task_template.conf new file mode 100644 index 0000000..f8a570b --- /dev/null +++ b/SCRIPT/skywater_openfpga_task/vexriscv/generate_testbench/config/task_template.conf @@ -0,0 +1,39 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_130nm/130nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr +arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml + +[OpenFPGA_SHELL] +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_arch_exploration.openfpga +openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_auto_clock.xml +openfpga_vpr_device_layout=auto +openfpga_vpr_route_chan_width=40 # Don't care +openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr +openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml # Don't care + +[ARCHITECTURES] +arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/vexriscv/vexriscv_small.v + +[SYNTHESIS_PARAM] +bench0_top = VexRiscv + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +# none