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[Arch] Now use timing variables in the architecture file

This commit is contained in:
tangxifan 2021-05-25 17:11:30 -06:00
parent 7d5eabbb36
commit 77a8a8644a
2 changed files with 106 additions and 107 deletions
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33
ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm_timing_tt_025C_1v80.yml Normal file
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@ -0,0 +1,33 @@
L1_SB_MUX_DELAY: 1.44e-9
L2_SB_MUX_DELAY: 1.44e-9
L4_SB_MUX_DELAY: 1.44e-9
CB_MUX_DELAY: 1.38e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT2_DELAY: 0.92e-9
LUT3_DELAY: 0.92e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.21e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
MULT9_A2Y_DELAY_MAX: 1.523e-9
MULT9_A2Y_DELAY_MIN: 0.776e-9
MULT9_B2Y_DELAY_MAX: 1.523e-9
MULT9_B2Y_DELAY_MIN: 0.776e-9
MULT18_A2Y_DELAY_MAX: 1.523e-9
MULT18_A2Y_DELAY_MIN: 0.776e-9
MULT18_B2Y_DELAY_MAX: 1.523e-9
MULT18_B2Y_DELAY_MIN: 0.776e-9

180
ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm.xml
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@ -89,7 +89,7 @@
</model> </model>
<model name="frac_lut4"> <model name="frac_lut4">
<input_ports> <input_ports>
<port name="in"/> <port name="in" combinational_sink_ports="lut2_out lut3_out lut4_out"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="lut2_out"/> <port name="lut2_out"/>
@ -371,28 +371,28 @@
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="L1_mux" R="0" Cin="0" Cout="0" Tdel="${L1_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="L2_mux" R="0" Cin="0" Cout="0" Tdel="${L2_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="L4_mux" R="0" Cin="0" Cout="0" Tdel="${L4_SB_MUX_DELAY}" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="0" Cout="0." Cin="0" Tdel="${CB_MUX_DELAY}" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="${L1_WIRE_R}" Cmetal="${L1_WIRE_C}">
<mux name="L1_mux"/> <mux name="L1_mux"/>
<sb type="pattern">1 1</sb> <sb type="pattern">1 1</sb>
<cb type="pattern">1</cb> <cb type="pattern">1</cb>
</segment> </segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="${L2_WIRE_R}" Cmetal="${L2_WIRE_C}">
<mux name="L2_mux"/> <mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb> <sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb> <cb type="pattern">1 1</cb>
</segment> </segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="${L4_WIRE_R}" Cmetal="${L4_WIRE_C}">
<mux name="L4_mux"/> <mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
@ -421,10 +421,10 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -440,7 +440,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="${INPAD_DELAY}" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -450,7 +450,7 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -522,6 +522,9 @@
<output name="lut2_out" num_pins="2"/> <output name="lut2_out" num_pins="2"/>
<output name="lut3_out" num_pins="2"/> <output name="lut3_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/> <output name="lut4_out" num_pins="1"/>
<delay_constant max="${LUT2_DELAY}" in_port="frac_lut4.in" out_port="frac_lut4.lut2_out"/>
<delay_constant max="${LUT3_DELAY}" in_port="frac_lut4.in" out_port="frac_lut4.lut3_out"/>
<delay_constant max="${LUT4_DELAY}" in_port="frac_lut4.in" out_port="frac_lut4.lut4_out"/>
</pb_type> </pb_type>
<pb_type name="carry_follower" blif_model=".subckt carry_follower_physical" num_pb="1"> <pb_type name="carry_follower" blif_model=".subckt carry_follower_physical" num_pb="1">
<input name="a" num_pins="1"/> <input name="a" num_pins="1"/>
@ -552,10 +555,10 @@
<input name="R" num_pins="1"/> <input name="R" num_pins="1"/>
<output name="Q" num_pins="1"/> <output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/> <clock name="C" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="C"/> <T_setup value="${FF_T_SETUP}" port="ff.D" clock="C"/>
<T_setup value="66e-12" port="ff.DI" clock="C"/> <T_setup value="${FF_T_SETUP}" port="ff.DI" clock="C"/>
<T_setup value="66e-12" port="ff.R" clock="C"/> <T_setup value="${FF_T_SETUP}" port="ff.R" clock="C"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="C"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct_frac_logic_in" input="fabric.in" output="frac_logic.in"/> <direct name="direct_frac_logic_in" input="fabric.in" output="frac_logic.in"/>
@ -567,20 +570,20 @@
<complete name="complete_ff_clk" input="fabric.clk" output="ff[1:0].C"/> <complete name="complete_ff_clk" input="fabric.clk" output="ff[1:0].C"/>
<complete name="complete_ff_reset" input="fabric.reset" output="ff[1:0].R"/> <complete name="complete_ff_reset" input="fabric.reset" output="ff[1:0].R"/>
<direct name="direct_frac_logic2ff0" input="frac_logic.out[0:0]" output="ff[0:0].D"> <direct name="direct_frac_logic2ff0" input="frac_logic.out[0:0]" output="ff[0:0].D">
<delay_constant max="45e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct_frac_logic2ff1" input="frac_logic.out[1:1]" output="ff[1:1].D"> <direct name="direct_frac_logic2ff1" input="frac_logic.out[1:1]" output="ff[1:1].D">
<delay_constant max="45e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/> <delay_constant max="${LUT_OUT1_TO_FF_D_DELAY}" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
</direct> </direct>
<mux name="mux_seq_comb_selector0" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux_seq_comb_selector0" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="${LUT_OUT0_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux_seq_comb_selector1" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux_seq_comb_selector1" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="${LUT_OUT1_TO_FLE_OUT_DELAY}" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -608,8 +611,8 @@
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="lut2_out" num_pins="2"/> <output name="lut2_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/> <output name="lut4_out" num_pins="1"/>
<delay_constant max="0.3e-9" in_port="adder_lut4.in" out_port="adder_lut4.lut2_out"/> <delay_constant max="${LUT2_DELAY}" in_port="adder_lut4.in" out_port="adder_lut4.lut2_out"/>
<delay_constant max="0.3e-9" in_port="adder_lut4.in" out_port="adder_lut4.lut4_out"/> <delay_constant max="${LUT4_DELAY}" in_port="adder_lut4.in" out_port="adder_lut4.lut4_out"/>
</pb_type> </pb_type>
<pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1"> <pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1">
<input name="a" num_pins="1"/> <input name="a" num_pins="1"/>
@ -675,18 +678,10 @@
<input name="in" num_pins="3" port_class="lut_in"/> <input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out"> <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
235e-12 ${LUT3_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
@ -700,8 +695,8 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="latch.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="latch.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="latch.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ff.D" output="latch.D"/> <direct name="direct1" input="ff.D" output="latch.D"/>
@ -714,8 +709,8 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="C" num_pins="1" port_class="clock"/> <clock name="C" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="dff.D" clock="C"/> <T_setup value="${FF_T_SETUP}" port="dff.D" clock="C"/>
<T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="dff.Q" clock="C"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ff.D" output="dff.D"/> <direct name="direct1" input="ff.D" output="dff.D"/>
@ -729,9 +724,9 @@
<input name="R" num_pins="1"/> <input name="R" num_pins="1"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="C" num_pins="1" port_class="clock"/> <clock name="C" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="dffr.D" clock="C"/> <T_setup value="${FF_T_SETUP}" port="dffr.D" clock="C"/>
<T_setup value="66e-12" port="dffr.R" clock="C"/> <T_setup value="${FF_T_SETUP}" port="dffr.R" clock="C"/>
<T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="dffr.Q" clock="C"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ff.D" output="dffr.D"/> <direct name="direct1" input="ff.D" output="dffr.D"/>
@ -746,9 +741,9 @@
<input name="RN" num_pins="1"/> <input name="RN" num_pins="1"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="C" num_pins="1" port_class="clock"/> <clock name="C" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="dffrn.D" clock="C"/> <T_setup value="${FF_T_SETUP}" port="dffrn.D" clock="C"/>
<T_setup value="66e-12" port="dffrn.RN" clock="C"/> <T_setup value="${FF_T_SETUP}" port="dffrn.RN" clock="C"/>
<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="dffrn.Q" clock="C"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ff.D" output="dffrn.D"/> <direct name="direct1" input="ff.D" output="dffrn.D"/>
@ -768,8 +763,8 @@
</direct> </direct>
<mux name="mux_seq_comb_selector" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]"> <mux name="mux_seq_comb_selector" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/> <delay_constant max="${LUT3_OUT_TO_FLE_OUT_DELAY}" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -802,20 +797,11 @@
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
261e-12 ${LUT4_DELAY}
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
@ -829,8 +815,8 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="latch.D" clock="clk"/> <T_setup value="${FF_T_SETUP}" port="latch.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="latch.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ff.D" output="latch.D"/> <direct name="direct1" input="ff.D" output="latch.D"/>
@ -843,8 +829,8 @@
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="C" num_pins="1" port_class="clock"/> <clock name="C" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="dff.D" clock="C"/> <T_setup value="${FF_T_SETUP}" port="dff.D" clock="C"/>
<T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="dff.Q" clock="C"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ff.D" output="dff.D"/> <direct name="direct1" input="ff.D" output="dff.D"/>
@ -858,9 +844,9 @@
<input name="R" num_pins="1"/> <input name="R" num_pins="1"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="C" num_pins="1" port_class="clock"/> <clock name="C" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="dffr.D" clock="C"/> <T_setup value="${FF_T_SETUP}" port="dffr.D" clock="C"/>
<T_setup value="66e-12" port="dffr.R" clock="C"/> <T_setup value="${FF_T_SETUP}" port="dffr.R" clock="C"/>
<T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="dffr.Q" clock="C"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ff.D" output="dffr.D"/> <direct name="direct1" input="ff.D" output="dffr.D"/>
@ -875,9 +861,9 @@
<input name="RN" num_pins="1"/> <input name="RN" num_pins="1"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="C" num_pins="1" port_class="clock"/> <clock name="C" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="dffrn.D" clock="C"/> <T_setup value="${FF_T_SETUP}" port="dffrn.D" clock="C"/>
<T_setup value="66e-12" port="dffrn.RN" clock="C"/> <T_setup value="${FF_T_SETUP}" port="dffrn.RN" clock="C"/>
<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/> <T_clock_to_Q max="${FF_T_CLK2Q}" port="dffrn.Q" clock="C"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ff.D" output="dffrn.D"/> <direct name="direct1" input="ff.D" output="dffrn.D"/>
@ -897,8 +883,8 @@
</direct> </direct>
<mux name="mux_seq_comb_selector" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux_seq_comb_selector" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="${FF0_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
@ -915,57 +901,37 @@
<!-- We use direct connections to reduce the area to the most <!-- We use direct connections to reduce the area to the most
The global local routing is going to compensate the loss in routability The global local routing is going to compensate the loss in routability
--> -->
<!-- FIXME: The implicit port definition results in I0[0] connected to
in[2]. Such twisted connection is not expected.
I[0] should be connected to in[0]
-->
<direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]"> <direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]"> <direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]"> <direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]"> <direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]"> <direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]"> <direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]"> <direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]"> <direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]"> <direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]"> <direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]"> <direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]"> <direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]"> <direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]"> <direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]"> <direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]"> <direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk"> <complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete> </complete>
@ -981,7 +947,7 @@
<!-- Scan chain links --> <!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in"> <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/> <delay_constant max="0" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct> </direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out"> <direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct> </direct>
@ -991,7 +957,7 @@
<direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin"> <direct name="carry_chain_in" input="clb.cin" output="fle[0:0].cin">
<!-- Put all inter-block carry chain delay on this one edge --> <!-- Put all inter-block carry chain delay on this one edge -->
<pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/> <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
<delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/> <delay_constant max="0" in_port="clb.cin" out_port="fle[0:0].cin"/>
</direct> </direct>
<direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout"> <direct name="carry_chain_out" input="fle[7:7].cout" output="clb.cout">
<pack_pattern name="chain" in_port="fle[7:7].cout" out_port="clb.cout"/> <pack_pattern name="chain" in_port="fle[7:7].cout" out_port="clb.cout"/>
@ -1019,8 +985,8 @@
<input name="A" num_pins="9"/> <input name="A" num_pins="9"/>
<input name="B" num_pins="9"/> <input name="B" num_pins="9"/>
<output name="Y" num_pins="18"/> <output name="Y" num_pins="18"/>
<delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_9x9.A" out_port="mult_9x9.Y"/> <delay_constant max="${MULT9_A2Y_DELAY_MAX}" min="${MULT9_A2Y_DELAY_MIN}" in_port="mult_9x9.A" out_port="mult_9x9.Y"/>
<delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_9x9.B" out_port="mult_9x9.Y"/> <delay_constant max="${MULT9_B2Y_DELAY_MAX}" min="${MULT9_B2Y_DELAY_MIN}" in_port="mult_9x9.B" out_port="mult_9x9.Y"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="a2a" input="mult_9x9_slice.A_cfg" output="mult_9x9.A"> <direct name="a2a" input="mult_9x9_slice.A_cfg" output="mult_9x9.A">
@ -1038,22 +1004,22 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="a2a_0" input="mult_18.a[0:8]" output="mult_9x9_slice[0].A_cfg[0:8]"> <direct name="a2a_0" input="mult_18.a[0:8]" output="mult_9x9_slice[0].A_cfg[0:8]">
<delay_constant max="134e-12" min="74e-12" in_port="mult_18.a[0:8]" out_port="mult_9x9_slice[0].A_cfg[0:8]"/> <delay_constant max="0" min="0" in_port="mult_18.a[0:8]" out_port="mult_9x9_slice[0].A_cfg[0:8]"/>
</direct> </direct>
<direct name="a2a_1" input="mult_18.a[9:17]" output="mult_9x9_slice[1].A_cfg[0:8]"> <direct name="a2a_1" input="mult_18.a[9:17]" output="mult_9x9_slice[1].A_cfg[0:8]">
<delay_constant max="134e-12" min="74e-12" in_port="mult_18.a[9:17]" out_port="mult_9x9_slice[1].A_cfg[0:8]"/> <delay_constant max="0" min="0" in_port="mult_18.a[9:17]" out_port="mult_9x9_slice[1].A_cfg[0:8]"/>
</direct> </direct>
<direct name="b2b_0" input="mult_18.b[0:8]" output="mult_9x9_slice[0].B_cfg[0:8]"> <direct name="b2b_0" input="mult_18.b[0:8]" output="mult_9x9_slice[0].B_cfg[0:8]">
<delay_constant max="134e-12" min="74e-12" in_port="mult_18.b[0:7]" out_port="mult_9x9_slice[0].B_cfg[0:8]"/> <delay_constant max="0" min="0" in_port="mult_18.b[0:7]" out_port="mult_9x9_slice[0].B_cfg[0:8]"/>
</direct> </direct>
<direct name="b2b_1" input="mult_18.b[9:17]" output="mult_9x9_slice[1].B_cfg[0:8]"> <direct name="b2b_1" input="mult_18.b[9:17]" output="mult_9x9_slice[1].B_cfg[0:8]">
<delay_constant max="134e-12" min="74e-12" in_port="mult_18.b[9:17]" out_port="mult_9x9_slice[1].B_cfg[0:8]"/> <delay_constant max="0" min="0" in_port="mult_18.b[9:17]" out_port="mult_9x9_slice[1].B_cfg[0:8]"/>
</direct> </direct>
<direct name="out2out_0" input="mult_9x9_slice[0].OUT_cfg[0:17]" output="mult_18.out[0:17]"> <direct name="out2out_0" input="mult_9x9_slice[0].OUT_cfg[0:17]" output="mult_18.out[0:17]">
<delay_constant max="1.93e-9" min="74e-12" in_port="mult_9x9_slice[0].OUT_cfg[0:17]" out_port="mult_18.out[0:17]"/> <delay_constant max="0" min="0" in_port="mult_9x9_slice[0].OUT_cfg[0:17]" out_port="mult_18.out[0:17]"/>
</direct> </direct>
<direct name="out2out_1" input="mult_9x9_slice[1].OUT_cfg[0:17]" output="mult_18.out[18:35]"> <direct name="out2out_1" input="mult_9x9_slice[1].OUT_cfg[0:17]" output="mult_18.out[18:35]">
<delay_constant max="1.93e-9" min="74e-12" in_port="mult_9x9_slice[1].OUT_cfg[0:17]" out_port="mult_18.out[18:35]"/> <delay_constant max="0" min="0" in_port="mult_9x9_slice[1].OUT_cfg[0:17]" out_port="mult_18.out[18:35]"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
@ -1066,8 +1032,8 @@
<input name="A" num_pins="18"/> <input name="A" num_pins="18"/>
<input name="B" num_pins="18"/> <input name="B" num_pins="18"/>
<output name="Y" num_pins="36"/> <output name="Y" num_pins="36"/>
<delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_18x18.A" out_port="mult_18x18.Y"/> <delay_constant max="${MULT18_A2Y_DELAY_MAX}" min="${MULT18_A2Y_DELAY_MIN}" in_port="mult_18x18.A" out_port="mult_18x18.Y"/>
<delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_18x18.B" out_port="mult_18x18.Y"/> <delay_constant max="${MULT18_B2Y_DELAY_MAX}" min="${MULT18_B2Y_DELAY_MIN}" in_port="mult_18x18.B" out_port="mult_18x18.Y"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="a2a" input="mult_18x18_slice.A_cfg" output="mult_18x18.A"> <direct name="a2a" input="mult_18x18_slice.A_cfg" output="mult_18x18.A">
@ -1085,13 +1051,13 @@
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="a2a" input="mult_18.a" output="mult_18x18_slice.A_cfg"> <direct name="a2a" input="mult_18.a" output="mult_18x18_slice.A_cfg">
<delay_constant max="134e-12" min="74e-12" in_port="mult_18.a" out_port="mult_18x18_slice.A_cfg"/> <delay_constant max="0" min="0" in_port="mult_18.a" out_port="mult_18x18_slice.A_cfg"/>
</direct> </direct>
<direct name="b2b" input="mult_18.b" output="mult_18x18_slice.B_cfg"> <direct name="b2b" input="mult_18.b" output="mult_18x18_slice.B_cfg">
<delay_constant max="134e-12" min="74e-12" in_port="mult_18.b" out_port="mult_18x18_slice.B_cfg"/> <delay_constant max="0" min="0" in_port="mult_18.b" out_port="mult_18x18_slice.B_cfg"/>
</direct> </direct>
<direct name="out2out" input="mult_18x18_slice.OUT_cfg" output="mult_18.out"> <direct name="out2out" input="mult_18x18_slice.OUT_cfg" output="mult_18.out">
<delay_constant max="1.93e-9" min="74e-12" in_port="mult_18x18_slice.OUT_cfg" out_port="mult_18.out"/> <delay_constant max="0" min="0" in_port="mult_18x18_slice.OUT_cfg" out_port="mult_18.out"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>