diff --git a/BENCHMARK/and2/and2.act b/BENCHMARK/and2/and2.act
new file mode 100644
index 0000000..0f77bc6
--- /dev/null
+++ b/BENCHMARK/and2/and2.act
@@ -0,0 +1,3 @@
+a 0.5 0.5
+b 0.5 0.5
+c 0.25 0.25
diff --git a/BENCHMARK/and2/and2.blif b/BENCHMARK/and2/and2.blif
new file mode 100644
index 0000000..d13bdc5
--- /dev/null
+++ b/BENCHMARK/and2/and2.blif
@@ -0,0 +1,8 @@
+.model and2
+.inputs a b
+.outputs c
+
+.names a b c
+11 1
+
+.end
diff --git a/BENCHMARK/and2/and2.v b/BENCHMARK/and2/and2.v
new file mode 100644
index 0000000..a23293c
--- /dev/null
+++ b/BENCHMARK/and2/and2.v
@@ -0,0 +1,18 @@
+/////////////////////////////////////////
+//  Functionality: 2-input AND 
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module and2(
+  a,
+  b,
+  c);
+
+input wire a;
+input wire b;
+output wire c;
+
+assign c = a & b;
+
+endmodule
diff --git a/BENCHMARK/and2_latch/and2_latch.act b/BENCHMARK/and2_latch/and2_latch.act
new file mode 100644
index 0000000..61bbe1f
--- /dev/null
+++ b/BENCHMARK/and2_latch/and2_latch.act
@@ -0,0 +1,6 @@
+a 0.492800 0.201000
+b 0.502000 0.197200
+clk 0.500000 2.000000
+d 0.240200 0.171200
+c 0.240200 0.044100
+n1 0.240200 0.044100
diff --git a/BENCHMARK/and2_latch/and2_latch.blif b/BENCHMARK/and2_latch/and2_latch.blif
new file mode 100644
index 0000000..96450e3
--- /dev/null
+++ b/BENCHMARK/and2_latch/and2_latch.blif
@@ -0,0 +1,14 @@
+# Benchmark "and2_latch" written by ABC on Wed Mar 11 10:36:28 2020
+.model and2_latch
+.inputs a b clk
+.outputs c d
+
+.latch n1 d  re clk 0
+
+.names a b c
+11 1
+
+.names c n1
+1 1
+
+.end
diff --git a/BENCHMARK/and2_latch/and2_latch.v b/BENCHMARK/and2_latch/and2_latch.v
new file mode 100644
index 0000000..135454d
--- /dev/null
+++ b/BENCHMARK/and2_latch/and2_latch.v
@@ -0,0 +1,29 @@
+/////////////////////////////////////////
+//  Functionality: 2-input AND with clocked 
+//                 and combinational outputs 
+//  Author:        Xifan Tang
+////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+module and2_latch(
+  a,
+  b,
+  clk,
+  c,
+  d);
+
+input wire clk;
+
+input wire a;
+input wire b;
+output wire c;
+output reg d;
+
+assign c = a & b;
+
+always @(posedge clk) begin
+  d <= c;
+end
+
+endmodule
diff --git a/BENCHMARK/counter/counter.v b/BENCHMARK/counter/counter.v
new file mode 100644
index 0000000..2160532
--- /dev/null
+++ b/BENCHMARK/counter/counter.v
@@ -0,0 +1,16 @@
+module counter(clk_counter, q_counter, rst_counter);
+
+    input clk_counter;
+    input rst_counter;
+    output [7:0] q_counter;
+    reg [7:0] q_counter;
+
+    always @ (posedge clk_counter)
+    begin
+        if(rst_counter)
+		q_counter <= 8'b00000000;
+	else
+		q_counter <= q_counter + 1;
+    end
+
+endmodule
diff --git a/BENCHMARK/counter/counter_tb.v b/BENCHMARK/counter/counter_tb.v
new file mode 100644
index 0000000..accfd82
--- /dev/null
+++ b/BENCHMARK/counter/counter_tb.v
@@ -0,0 +1,24 @@
+module counter_tb;
+
+	reg clk_counter, rst_counter;
+	wire [7:0] q_counter;
+
+	counter_original C_1(
+		clk_counter, 
+		q_counter, 
+		rst_counter);
+	
+	initial begin
+		#0 rst_counter = 1'b1; clk_counter = 1'b0;
+		#100 rst_counter = 1'b0;
+	end
+
+	always begin
+		#10 clk_counter = ~clk_counter;
+	end
+	
+	initial begin
+		#5000 $stop;
+	end
+
+endmodule
\ No newline at end of file