From 72db7fc7c088ca00f864814d8e67bad75267616d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 8 Nov 2020 11:47:08 -0700 Subject: [PATCH] [Script] Adapt openfpga task-run configuration to use the fabric key scripts --- .../generate_fabric/config/task_template.conf | 3 ++- .../generate_sdc/config/task_template.conf | 3 ++- .../generate_testbench/config/task_template.conf | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf index 2d690ad..a172e5d 100644 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf @@ -16,13 +16,14 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf index 86a19dd..c017e78 100644 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf @@ -16,12 +16,13 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf index 58349ae..55cb178 100644 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf @@ -16,13 +16,14 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml