From 70d0ecdcac7d3c988cf922b592669bbd07272429 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 15 Jan 2021 00:10:53 -0700 Subject: [PATCH] Added files to sync --- .github/workflows/perform_precheck.sh | 8 ++++++++ SynRepoConfig/sync_files_qlsofa_hd.csv | 2 +- SynRepoConfig/sync_files_sofa_chd.csv | 2 +- SynRepoConfig/sync_files_sofa_hd.csv | 2 +- 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/.github/workflows/perform_precheck.sh b/.github/workflows/perform_precheck.sh index c85e736..0361025 100644 --- a/.github/workflows/perform_precheck.sh +++ b/.github/workflows/perform_precheck.sh @@ -8,6 +8,13 @@ cd ./${DEST_DIR} echo "[Info] Running in directory ${PWD}" cp ../SOFA-Chips/${SCAN_DIRECTORY}/fpga_top_icv_in_design.gds.gz ./gds/ +if test -f "./gds/fpga_top_icv_in_design.gds.gz.sha1"; then + sha1sum --status -c ./gds/fpga_top_icv_in_design.gds.gz.sha1 + status=$? + [ $status -eq 0 ] && echo "SHA1 matched GDS is already merged ... skipping drc" && exit +fi +fpga_top_sha1=$(sha1sum ./gds/fpga_top_icv_in_design.gds.gz) + make uncompress echo "[Info] All files are uncompressed" @@ -80,3 +87,4 @@ if [[ 0 -eq $(git cat-file -e $CARAVEL_COMPARE_COMMIT) ]]; then /usr/local/workspace/${DEST_DIR}/checks/compare_caravel.txt echo "[Info] Create compare_caravel.txt" fi +echo $fpga_top_sha1 > ./gds/fpga_top_icv_in_design.gds.gz.sha1 diff --git a/SynRepoConfig/sync_files_qlsofa_hd.csv b/SynRepoConfig/sync_files_qlsofa_hd.csv index e93b11f..d6f2a8c 100644 --- a/SynRepoConfig/sync_files_qlsofa_hd.csv +++ b/SynRepoConfig/sync_files_qlsofa_hd.csv @@ -2,4 +2,4 @@ SrcLoc, DestLoc FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/ FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v -SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v +HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v diff --git a/SynRepoConfig/sync_files_sofa_chd.csv b/SynRepoConfig/sync_files_sofa_chd.csv index 89e0555..dc50024 100644 --- a/SynRepoConfig/sync_files_sofa_chd.csv +++ b/SynRepoConfig/sync_files_sofa_chd.csv @@ -2,4 +2,4 @@ SrcLoc, DestLoc FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/ FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v -SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v +HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v diff --git a/SynRepoConfig/sync_files_sofa_hd.csv b/SynRepoConfig/sync_files_sofa_hd.csv index 1bc6d22..0df69ae 100644 --- a/SynRepoConfig/sync_files_sofa_hd.csv +++ b/SynRepoConfig/sync_files_sofa_hd.csv @@ -2,4 +2,4 @@ SrcLoc, DestLoc FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/ FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v -SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v +HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v