From 6e99257bedf72dcc4b2254ef400fd92caeb859be Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 25 May 2021 18:19:54 -0600
Subject: [PATCH] [Arch] Now use SuperLUT4 to implement adder LUT functions

---
 ...c_dsp18_skywater130nm_fdhd_cc_openfpga.xml |  17 ++-
 ...sp18_skywater130nm_timing_tt_025C_1v80.yml |   9 +-
 ...LR_caravel_io_frac_dsp18_skywater130nm.xml | 101 +++++-------------
 3 files changed, 45 insertions(+), 82 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_frac_dsp18_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_frac_dsp18_skywater130nm_fdhd_cc_openfpga.xml
index d6f5571..f6b47fd 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_frac_dsp18_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_frac_dsp18_skywater130nm_fdhd_cc_openfpga.xml
@@ -171,7 +171,7 @@
       <port type="clock" prefix="C" lib_name="CK" size="1" default_val="0" />
       <port type="sram" prefix="mode" lib_name="MODE" size="1" mode_select="true" circuit_model_name="CUSTOM_CCFF" default_val="0"/>
     </circuit_model>
-    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
+    <circuit_model type="lut" name="frac_lut4_arith" prefix="frac_lut4_arith" dump_structural_verilog="true" verilog_netlist="frac_lut4_arith.v">
       <design_technology type="cmos" fracturable_lut="true"/>
       <input_buffer exist="false"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
@@ -180,11 +180,12 @@
       <lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
       <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
       <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
-      <port type="output" prefix="lut2_out" size="2" lut_frac_level="2" lut_output_mask="2,3"/>
+      <port type="input" prefix="cin" size="1" is_harden_lut_port="true"/>
       <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
       <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
+      <port type="output" prefix="cout" size="1" is_harden_lut_port="true"/>
       <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="CUSTOM_CCFF" default_val="1"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="CUSTOM_CCFF" default_val="1"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
     <circuit_model type="ccff" name="CUSTOM_CCFF" prefix="CUSTOM_CCFF" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
@@ -273,15 +274,13 @@
     <!-- physical pb_type binding in complex block CLB -->
     <!-- physical mode will be the default mode if not specified -->
     <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="CARRY_MUX2"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" circuit_model_name="frac_lut4_arith" mode_bits="00"/>
     <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="CUSTOM_DATAFF" mode_bits="0"/>
     <!-- Binding operating pb_type to physical pb_type -->
     <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1"/>
-    <pb_type name="clb.fle[arithmetic].soft_adder.carry_follower" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.carry_follower"/>
+    <pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="11"/>
     <!-- Binding operating pb_types in mode 'n2_lut3' -->
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="01" physical_pb_type_index_factor="0.5">
       <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
       <port name="in" physical_mode_port="in[0:2]"/>
       <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
@@ -295,7 +294,7 @@
       <port name="RN" physical_mode_port="R"/>
     </pb_type>
     <!-- Binding operating pb_types in mode 'ble4' -->
-    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="00">
       <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
       <port name="in" physical_mode_port="in[0:3]"/>
       <port name="out" physical_mode_port="lut4_out"/>
diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm_timing_tt_025C_1v80.yml
index a3a3d18..9580625 100644
--- a/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm_timing_tt_025C_1v80.yml
+++ b/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm_timing_tt_025C_1v80.yml
@@ -18,11 +18,18 @@ LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
 FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
 LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
 FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
-LUT2_DELAY: 0.92e-9
+LUT_CIN2LUT3_OUT_DELAY: 1.21e-9
+LUT_CIN2LUT4_OUT_DELAY: 1.21e-9
+LUT_CIN2COUT_DELAY: 1.21e-9
+LUT_IN2COUT_DELAY: 1.21e-9
 LUT3_DELAY: 0.92e-9
 LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
 LUT4_DELAY: 1.21e-9
 LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
+ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9
+ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9
+ADDER_LUT4_IN2OUT_DELAY: 1.21e-9
+ADDER_LUT4_IN2COUT_DELAY: 1.21e-9
 MULT9_A2Y_DELAY_MAX: 1.523e-9
 MULT9_A2Y_DELAY_MIN: 0.776e-9
 MULT9_B2Y_DELAY_MAX: 1.523e-9
diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm.xml
index 507e16f..70b7e90 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_frac_dsp18_skywater130nm.xml
@@ -70,40 +70,22 @@
     </model>
     <model name="adder_lut4">
       <input_ports>
-        <port name="in" combinational_sink_ports="lut2_out lut4_out"/>
+        <port name="in" combinational_sink_ports="lut4_out cout"/>
+        <port name="cin" combinational_sink_ports="lut4_out cout"/>
       </input_ports>
       <output_ports>
-        <port name="lut2_out"/>
         <port name="lut4_out"/>
-      </output_ports>
-    </model>
-    <model name="carry_follower">
-      <input_ports>
-        <port name="a" combinational_sink_ports="cout"/>
-        <port name="b" combinational_sink_ports="cout"/>
-        <port name="cin" combinational_sink_ports="cout"/>
-      </input_ports>
-      <output_ports>
         <port name="cout"/>
       </output_ports>
     </model>
-    <model name="frac_lut4">
+    <model name="frac_lut4_arith">
       <input_ports>
-        <port name="in" combinational_sink_ports="lut2_out lut3_out lut4_out"/>
+        <port name="in" combinational_sink_ports="lut3_out lut4_out cout"/>
+        <port name="cin" combinational_sink_ports="lut3_out lut4_out cout"/>
       </input_ports>
       <output_ports>
-        <port name="lut2_out"/>
         <port name="lut3_out"/>
         <port name="lut4_out"/>
-      </output_ports>
-    </model>
-    <model name="carry_follower_physical">
-      <input_ports>
-        <port name="a" combinational_sink_ports="cout"/>
-        <port name="b" combinational_sink_ports="cout"/>
-        <port name="cin" combinational_sink_ports="cout"/>
-      </input_ports>
-      <output_ports>
         <port name="cout"/>
       </output_ports>
     </model>
@@ -517,35 +499,26 @@
               <output name="out" num_pins="2"/>
               <output name="cout" num_pins="1"/>
               <!-- Define LUT -->
-              <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
+              <pb_type name="frac_lut4_arith" blif_model=".subckt frac_lut4_arith" num_pb="1">
                 <input name="in" num_pins="4"/>
-                <output name="lut2_out" num_pins="2"/>
+                <input name="cin" num_pins="1"/>
                 <output name="lut3_out" num_pins="2"/>
                 <output name="lut4_out" num_pins="1"/>
-                <delay_constant max="${LUT2_DELAY}" in_port="frac_lut4.in" out_port="frac_lut4.lut2_out"/>
-                <delay_constant max="${LUT3_DELAY}" in_port="frac_lut4.in" out_port="frac_lut4.lut3_out"/>
-                <delay_constant max="${LUT4_DELAY}" in_port="frac_lut4.in" out_port="frac_lut4.lut4_out"/>
-              </pb_type>
-              <pb_type name="carry_follower" blif_model=".subckt carry_follower_physical" num_pb="1">
-                <input name="a" num_pins="1"/>
-                <input name="b" num_pins="1"/>
-                <input name="cin" num_pins="1"/>
                 <output name="cout" num_pins="1"/>
-                <delay_constant max="0.3e-9" in_port="carry_follower.a" out_port="carry_follower.cout"/>
-                <delay_constant max="0.3e-9" in_port="carry_follower.b" out_port="carry_follower.cout"/>
-                <delay_constant max="0.3e-9" in_port="carry_follower.cin" out_port="carry_follower.cout"/>
+                <delay_constant max="${LUT_CIN2LUT3_OUT_DELAY}" in_port="frac_lut4_arith.cin" out_port="frac_lut4_arith.lut3_out"/>
+                <delay_constant max="${LUT_CIN2LUT4_OUT_DELAY}" in_port="frac_lut4_arith.cin" out_port="frac_lut4_arith.lut4_out"/>
+                <delay_constant max="${LUT_CIN2COUT_DELAY}" in_port="frac_lut4_arith.cin" out_port="frac_lut4_arith.cout"/>
+                <delay_constant max="${LUT3_DELAY}" in_port="frac_lut4_arith.in" out_port="frac_lut4_arith.lut3_out"/>
+                <delay_constant max="${LUT4_DELAY}" in_port="frac_lut4_arith.in" out_port="frac_lut4_arith.lut4_out"/>
+                <delay_constant max="${LUT_IN2COUT_DELAY}" in_port="frac_lut4_arith.in" out_port="frac_lut4_arith.cout"/>
               </pb_type>
               <interconnect>
-                <direct name="direct1" input="frac_logic.in[0:1]" output="frac_lut4.in[0:1]"/>
-                <direct name="direct2" input="frac_logic.in[3:3]" output="frac_lut4.in[3:3]"/>
-                <direct name="direct3" input="frac_logic.cin" output="carry_follower.b"/>
-                <direct name="direct4" input="frac_lut4.lut2_out[1:1]" output="carry_follower.a"/>
-                <direct name="direct5" input="frac_lut4.lut2_out[0:0]" output="carry_follower.cin"/>
-                <direct name="direct6" input="carry_follower.cout" output="frac_logic.cout"/>
-                <direct name="direct7" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
+                <direct name="direct_in" input="frac_logic.in[0:3]" output="frac_lut4_arith.in[0:3]"/>
+                <direct name="direct_cin" input="frac_logic.cin" output="frac_lut4_arith.cin"/>
+                <direct name="direct_cout" input="frac_lut4_arith.cout" output="frac_logic.cout"/>
+                <direct name="direct_lut_out" input="frac_lut4_arith.lut3_out[1]" output="frac_logic.out[1]"/>
                 <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
-                <mux name="mux2" input="frac_logic.cin frac_logic.in[2:2]" output="frac_lut4.in[2:2]"/>
+                <mux name="mux1" input="frac_lut4_arith.lut4_out frac_lut4_arith.lut3_out[0]" output="frac_logic.out[0]"/>
               </interconnect>
             </pb_type>
             <!-- Define flip-flop with scan-chain capability, DI is the scan-chain data input -->
@@ -608,43 +581,27 @@
             <output name="cout" num_pins="1"/>
             <!-- Define special LUT marco to be used as adder -->
             <pb_type name="adder_lut4" blif_model=".subckt adder_lut4" num_pb="1">
-              <input name="in" num_pins="4"/>
-              <output name="lut2_out" num_pins="2"/>
-              <output name="lut4_out" num_pins="1"/>
-              <delay_constant max="${LUT2_DELAY}" in_port="adder_lut4.in" out_port="adder_lut4.lut2_out"/>
-              <delay_constant max="${LUT4_DELAY}" in_port="adder_lut4.in" out_port="adder_lut4.lut4_out"/>
-            </pb_type>
-            <pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
               <input name="cin" num_pins="1"/>
+              <input name="in" num_pins="4"/>
+              <output name="lut4_out" num_pins="1"/>
               <output name="cout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="carry_follower.a" out_port="carry_follower.cout"/>
-              <delay_constant max="0.3e-9" in_port="carry_follower.b" out_port="carry_follower.cout"/>
-              <delay_constant max="0.3e-9" in_port="carry_follower.cin" out_port="carry_follower.cout"/>
+              <delay_constant max="${ADDER_LUT4_CIN2OUT_DELAY}" in_port="adder_lut4.cin" out_port="adder_lut4.lut4_out"/>
+              <delay_constant max="${ADDER_LUT4_CIN2COUT_DELAY}" in_port="adder_lut4.cin" out_port="adder_lut4.cout"/>
+              <delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder_lut4.in" out_port="adder_lut4.lut4_out"/>
+              <delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder_lut4.in" out_port="adder_lut4.cout"/>
             </pb_type>
             <interconnect>
-              <direct name="direct_in0to1" input="soft_adder.in[0:1]" output="adder_lut4.in[0:1]"/>
-              <direct name="direct_in3" input="soft_adder.in[3:3]" output="adder_lut4.in[3:3]"/>
-              <direct name="direct_cin" input="soft_adder.cin" output="carry_follower.b">
+              <direct name="direct_in" input="soft_adder.in[0:3]" output="adder_lut4.in[0:3]"/>
+              <direct name="direct_cin" input="soft_adder.cin" output="adder_lut4.cin">
                 <!-- Pack pattern to build an adder chain connection considered by packer -->
-                <pack_pattern name="chain" in_port="soft_adder.cin" out_port="carry_follower.b"/>
+                <pack_pattern name="chain" in_port="soft_adder.cin" out_port="adder_lut4.cin"/>
               </direct>
-              <direct name="direct_carry" input="adder_lut4.lut2_out[1:1]" output="carry_follower.a">
-                <!-- Pack pattern to pair adder_lut4 and carry_follower into a molecule
-                     considered by packer -->
-                <pack_pattern name="lut_follower" in_port="adder_lut4.lut2_out[1:1]" out_port="carry_follower.a"/>
-              </direct>
-              <direct name="direct_lut2cin" input="adder_lut4.lut2_out[0:0]" output="carry_follower.cin">
-              </direct>
-              <direct name="direct_cout" input="carry_follower.cout" output="soft_adder.cout">
+              <direct name="direct_cout" input="adder_lut4.cout" output="soft_adder.cout">
                 <!-- Pack pattern to build an adder chain connection considered by packer -->
-                <pack_pattern name="chain" in_port="carry_follower.cout" out_port="soft_adder.cout"/>
+                <pack_pattern name="chain" in_port="adder_lut4.cout" out_port="soft_adder.cout"/>
               </direct>
               <direct name="direct_sumout" input="adder_lut4.lut4_out" output="soft_adder.sumout[0:0]">
               </direct>
-              <mux name="mux_out" input="soft_adder.cin soft_adder.in[2:2]" output="adder_lut4.in[2:2]">
-              </mux>
             </interconnect>
           </pb_type>
           <interconnect>