diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga new file mode 100644 index 0000000..2371794 --- /dev/null +++ b/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga @@ -0,0 +1,37 @@ +# This script is designed to generate fabric Verilog netlists +# with a fixed device layout +# It will only output netlists to be used by backend tools, +# i.e., Synopsys ICC2, including +# - Verilog netlists +# - fabric hierarchy description for ICC2's hierarchical flow +# - Timing/Design constraints +# +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR} + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory