diff --git a/DOC/source/arch/fpga_arch.rst b/DOC/source/arch/fpga_arch.rst index 47b3668..c2bf3b2 100644 --- a/DOC/source/arch/fpga_arch.rst +++ b/DOC/source/arch/fpga_arch.rst @@ -3,10 +3,10 @@ FPGA Overview ------------- -.. _fpga_arch_generality: +.. _fpga_arch_overview: -Generality -~~~~~~~~~~ +Architecture Overview +~~~~~~~~~~~~~~~~~~~~~ :numref:`fig_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric. The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric. @@ -30,30 +30,33 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra .. table:: FPGA tile type and functionalities - +------+----------+---------------------------------------------+ - | Type | Capacity | Description | - +======+==========+=============================================+ - | CLB | 144 | Each CLB tile consists of | - | | | - a Configurable Logic Block (CLB) | - | | | - a X-direction Connection Block (CBx) | - | | | - a Y-direction Connection Block (CBy) | - | | | - a Switch Block (SB). | - | | | This is the majority tile across the fabric | - | | | to implement logics and registers. | - +------+----------+---------------------------------------------+ - | IO-A | 36 | The type-A I/O is a low-density I/O tile | - | | | which is designed to mainly interface the | - | | | the GPIOs of the SoC. | - | | | Each I/O-A tile consists of 1 digitial I/O | - | | | cell. | - +------+----------+---------------------------------------------+ - | IO-B | 12 | The type-B I/O is a high-density I/O tile | - | | | which is designed to mainly interface the | - | | | the wishbone interface and logic analyzer | - | | | of the SoC. | - | | | Each I/O-B tile consists of 9 digitial I/O | - | | | cells. | - +------+----------+---------------------------------------------+ + +------+----------+----------------------------------------------+ + | Type | Capacity | Description | + +======+==========+==============================================+ + | CLB | 144 || Each CLB tile consists of | + | | || - a Configurable Logic Block (CLB) | + | | || - a X-direction Connection Block (CBx) | + | | || - a Y-direction Connection Block (CBy) | + | | || - a Switch Block (SB). | + | | | | + | | || This is the majority tile across the fabric | + | | | to implement logics and registers. | + +------+----------+----------------------------------------------+ + | IO-A | 36 || The type-A I/O is a low-density I/O tile | + | | | which is designed to mainly interface | + | | || the GPIOs of the SoC. | + | | | | + | | || Each I/O-A tile consists of 1 digitial I/O | + | | | cell. | + +------+----------+----------------------------------------------+ + | IO-B | 12 || The type-B I/O is a high-density I/O tile | + | | | which is designed to mainly interface | + | | || the wishbone interface and logic analyzer | + | | | of the SoC. | + | | | | + | | || Each I/O-B tile consists of 9 digitial I/O | + | | | cells. | + +------+----------+----------------------------------------------+ .. _fpga_arch_scan_chain: diff --git a/DOC/source/dc_ac_character.rst b/DOC/source/device/dc_ac_character.rst similarity index 73% rename from DOC/source/dc_ac_character.rst rename to DOC/source/device/dc_ac_character.rst index 84ec62e..6b22aee 100644 --- a/DOC/source/dc_ac_character.rst +++ b/DOC/source/device/dc_ac_character.rst @@ -37,19 +37,22 @@ Recommended Operating Conditions .. table:: Recommended Operating Conditions - +----------+------------------------------+------+------+-------+ - | Symbol | Description | Min | Max | Units | - +==========+==============================+======+======+=======+ - | VDD_io | Supply voltage for I/Os | TBD | TBD | V | - +----------+------------------------------+------+------+-------+ - | VDD_core | Supply voltage for FPGA core | TBD | TBD | V | - +----------+------------------------------+------+------+-------+ - | V_in | Input voltage for other I/Os | TBD | TBD | V | - +----------+------------------------------+------+------+-------+ - | I_in | Maximum current through pins | N/A | TBD | mA | - +----------+------------------------------+------+------+-------+ - | f_max | Maximum frequency of I/Os | N/A | TBD | MHz | - +----------+------------------------------+------+------+-------+ + +----------+------------------------------+------+---------+------+-------+ + | Symbol | Description | Min | Typical | Max | Units | + +==========+==============================+======+=========+======+=======+ + | VDD_io | Supply voltage for I/Os | 1.8 | 3.3 | 5.0 | V | + +----------+------------------------------+------+---------+------+-------+ + | VDD_core | Supply voltage for FPGA core | 1.62 | 1.8 | 1.98 | V | + +----------+------------------------------+------+---------+------+-------+ + | V_in | Input voltage for other I/Os | TBD | 3.3 | TBD | V | + +----------+------------------------------+------+---------+------+-------+ + | I_in | Maximum current through pins | N/A | TBD | TBD | mA | + +----------+------------------------------+------+---------+------+-------+ + | f_max | Maximum frequency of I/Os | N/A | TBD | TBD | MHz | + +----------+------------------------------+------+---------+------+-------+ + +.. note:: Threshold voltage of logic `1` for I/O (V_OH) is 0.8 * VDD_io. In other words, V_in should be at least 2.64V in order to be sensed as logic `1` +.. note:: Threshold voltage of logic `0` for I/O (V_OH) is 0.4. In other words, V_in should not exceed 0.4V in order to be sensed as logic `0`. Typical AC Characteristics ^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/DOC/source/device/device_overview.rst b/DOC/source/device/device_overview.rst new file mode 100644 index 0000000..4f7680a --- /dev/null +++ b/DOC/source/device/device_overview.rst @@ -0,0 +1,11 @@ +.. _device_overview: + +General Description +------------------- + +All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII. +All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK. +The devices are embedded FPGA IPs, which are designed to interface the caravel SoC interface. +We aims to empower embedded applications with its low-cost design approach but high-density architecture. +Operating temperature ranging from 0 :math:`^\circ C` to 85 :math:`^\circ C` + diff --git a/DOC/source/device/device_resource.rst b/DOC/source/device/device_resource.rst new file mode 100644 index 0000000..8acbae2 --- /dev/null +++ b/DOC/source/device/device_resource.rst @@ -0,0 +1,38 @@ +.. _device_resource: + +Device Resources +---------------- + +.. _device_resource_hd_fpga: + +High-Density FPGA +~~~~~~~~~~~~~~~~~ + +The High Density (HD) FPGA is an embedded FPGA built with the Skywater 130nm High Density Standard Cell library (`Sky130_fd_SC_HD `_). + +.. table:: Logic capacity of High Density (HD) FPGA IP + + +-------------------------------+------------+ + | Resource Type | Capacity | + +===============================+============+ + | Look-Up Tables [1]_ | 1152 | + +-------------------------------+------------+ + | Flip-flops | 2204 | + +-------------------------------+------------+ + | Max. Configuration Speed [2]_ | 50MHz | + +-------------------------------+------------+ + | Max. Operating Speed [2]_ | 50MHz | + +-------------------------------+------------+ + | User I/O Pins [3]_ | 144 | + +-------------------------------+------------+ + | Max. I/O Speed [2]_ | 33MHz | + +-------------------------------+------------+ + | Core Voltage | 1.8V | + +-------------------------------+------------+ + +.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT. + +.. [2] bounded by the maximum speed of `GPIO cells of Skywater 130nm PDK `_. Higher speed may be expected when a high-speed GPIO cell is available. + +.. [3] I/Os are divided into two groups: GPIO and embedded I/O. See details in :ref:`io_resource`. + diff --git a/DOC/source/device/index.rst b/DOC/source/device/index.rst new file mode 100644 index 0000000..e2f9d8c --- /dev/null +++ b/DOC/source/device/index.rst @@ -0,0 +1,11 @@ +.. _device: + Device Datasheet + +.. toctree:: + :maxdepth: 2 + + device_overview + + device_resource + + dc_ac_character diff --git a/DOC/source/device_family.rst b/DOC/source/device_family.rst deleted file mode 100644 index db351b6..0000000 --- a/DOC/source/device_family.rst +++ /dev/null @@ -1,38 +0,0 @@ -.. _device_family: - -Overview --------- - -All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII. -All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK. -The devices are embedded FPGA IPs, which are designed to interface the caravel SoC interface. -We aims to empower embedded applications with its low-cost design approach but high-density architecture. - - -- Native support on shift registers - -- Operating temperature ranging from 0 :math:`^\circ C` to 85 :math:`^\circ C` - - -.. table:: Logic capacity of High Density (HD) FPGA IP - - +--------------------------+------------+ - | Resource Type | Capacity | - +==========================+============+ - | Look-Up Tables [1]_ | 1152 | - +--------------------------+------------+ - | Flip-flops | 2204 | - +--------------------------+------------+ - | Max. Configuration Speed | TBD | - +--------------------------+------------+ - | Max. Operating Speed | TBD | - +--------------------------+------------+ - | User I/O Pins | 144 | - +--------------------------+------------+ - | Max. I/O Speed | TBD | - +--------------------------+------------+ - | Core Voltage | 1.8V | - +--------------------------+------------+ - -.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT. - diff --git a/DOC/source/index.rst b/DOC/source/index.rst index dad742c..f9fca98 100644 --- a/DOC/source/index.rst +++ b/DOC/source/index.rst @@ -7,15 +7,13 @@ Welcome to SKywater-OpenFPGA documentation! =========================================== .. toctree:: - :caption: Device + :caption: Device Datasheet - device_family - - dc_ac_character + device/index .. toctree:: :maxdepth: 2 - :caption: Architecture + :caption: FPGA Architecture arch/index @@ -23,9 +21,9 @@ Welcome to SKywater-OpenFPGA documentation! :maxdepth: 2 :caption: Appendix - contact + tail/contact - acknowledgment + tail/acknowledgment For more information on the OpenFPGA see openfpga_doc_ or openfpga_github_ diff --git a/DOC/source/acknowledgment.rst b/DOC/source/tail/acknowledgment.rst similarity index 100% rename from DOC/source/acknowledgment.rst rename to DOC/source/tail/acknowledgment.rst diff --git a/DOC/source/contact.rst b/DOC/source/tail/contact.rst similarity index 100% rename from DOC/source/contact.rst rename to DOC/source/tail/contact.rst diff --git a/DOC/source/figures/darpa_logo.png b/DOC/source/tail/figures/darpa_logo.png similarity index 100% rename from DOC/source/figures/darpa_logo.png rename to DOC/source/tail/figures/darpa_logo.png diff --git a/DOC/source/figures/lnis_logo.png b/DOC/source/tail/figures/lnis_logo.png similarity index 100% rename from DOC/source/figures/lnis_logo.png rename to DOC/source/tail/figures/lnis_logo.png diff --git a/DOC/source/figures/uofu_logo.png b/DOC/source/tail/figures/uofu_logo.png similarity index 100% rename from DOC/source/figures/uofu_logo.png rename to DOC/source/tail/figures/uofu_logo.png