[Benchmark] Add benchmark to test fracturable LUTs

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tangxifan 2020-11-22 13:33:09 -07:00
parent fa9a3bd9f3
commit 6c4c23ee72
3 changed files with 37 additions and 0 deletions

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.model and2_or2
.inputs a b
.outputs c d
.names a b c
11 1
.names a b d
00 0
.end

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/////////////////////////////////////////
// Functionality: 2-input AND + 2-input OR
// This benchmark is designed to test fracturable LUTs
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module and2_or2(
a,
b,
c,
d);
input wire a;
input wire b;
output wire c;
output wire d;
assign c = a & b;
assign d = a | b;
endmodule