From 6aefa8077e2e712bfa7d9d1d0897b6a31a630856 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 25 Nov 2020 16:40:54 -0700
Subject: [PATCH] [Arch] Critical patch on LE architecture which enables
 correct shift register connections

---
 ...egister_scan_chain_nonLR_caravel_io_skywater130nm.xml | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 92ea39f..08c4b97 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -396,18 +396,21 @@
               <direct name="direct3" input="ff[0].Q" output="ff[1].DI"/>
               <direct name="direct4" input="ff[1].Q" output="fabric.sc_out"/>
               <direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
-              <direct name="direct6" input="frac_logic.out[1:1]" output="ff[1:1].D"/>
               <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
               <mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
                 <delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
                 <delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
               </mux>
-              <mux name="mux2" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+              <mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
+                <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
+              </mux>
+              <mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
                 <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
-              <mux name="mux3" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+              <mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
                 <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>