From 68c1e17a96edd6d588573a13b9fa2c60898455a9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 14 Dec 2020 13:26:04 -0700 Subject: [PATCH] [Testbench] Add more testbenches for CHD post-pnr verification --- .../bin2bcd_post_pnr_include_netlists.v | 30 +++++++++++++++++++ ...in2bcd_post_pnr_wrapper_include_netlists.v | 30 +++++++++++++++++++ ...ounter_post_pnr_wrapper_include_netlists.v | 30 +++++++++++++++++++ .../top_module_post_pnr_include_netlists.v | 30 +++++++++++++++++++ ...module_post_pnr_wrapper_include_netlists.v | 30 +++++++++++++++++++ 5 files changed, 150 insertions(+) create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_wrapper_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_wrapper_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_wrapper_include_netlists.v diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_include_netlists.v new file mode 100644 index 0000000..0ed7b82 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_include_netlists.v @@ -0,0 +1,30 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "bin2bcd_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..8235967 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,30 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "bin2bcd_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..1ad7f89 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,30 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "counter_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_include_netlists.v new file mode 100644 index 0000000..9ebbef1 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_include_netlists.v @@ -0,0 +1,30 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "top_module_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..a784f07 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,30 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "top_module_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_wrapper_autocheck_top_tb.v" +`endif +