diff --git a/HDL/common/custom_cell_mux_primitive_generator.py b/HDL/common/custom_cell_mux_primitive_generator.py index 45b8c88..50131a2 100644 --- a/HDL/common/custom_cell_mux_primitive_generator.py +++ b/HDL/common/custom_cell_mux_primitive_generator.py @@ -94,6 +94,20 @@ def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index): return lines +####################################################################### +# A function to generate Verilog codes for a MUX2 standard cell +# Given an input index +def generate_verilog_codes_standard_cell_mux2(first_input_index, instance_index): + lines = [] + + lines.append("\tsky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_" + str(instance_index) + "(") + lines.append("\t .A1(in[" + str(first_input_index) + "]),") + lines.append("\t .A0(in[" + str(first_input_index + 1) + "]),") + lines.append("\t .S(mem[" + str(first_input_index) + "]),") + lines.append("\t .X(out[0])") + lines.append("\t );") + + return lines ####################################################################### # A function to output custom cells of multiplexing structure to a file @@ -107,12 +121,8 @@ def write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size): if (1 == mem_size): assert(2 == input_size) # Output a standard cell, currently we support HD cell MUX2 - lines.append("\tsky130_fd_sc_hd_mux2_1 sky130_fd_sc_hd_mux2_1_0(") - lines.append("\t .A1(in[0]),") - lines.append("\t .A0(in[1]),") - lines.append("\t .S(mem[0]),") - lines.append("\t .X(out[0])") - lines.append("\t );") + for line in generate_verilog_codes_standard_cell_mux2(0, 0): + lines.append(line) else: assert(1 < mem_size) assert(mem_size == input_size) diff --git a/HDL/common/digital_io_hd_primitives.v b/HDL/common/digital_io_hd_primitives.v new file mode 100644 index 0000000..5e387e4 --- /dev/null +++ b/HDL/common/digital_io_hd_primitives.v @@ -0,0 +1,6 @@ +`timescale 1ns/1ps + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_4.v" + diff --git a/HDL/common/fd_hd_mux_custom_cells_tt.v b/HDL/common/fd_hd_mux_custom_cells_tt.v new file mode 100644 index 0000000..8bde7c8 --- /dev/null +++ b/HDL/common/fd_hd_mux_custom_cells_tt.v @@ -0,0 +1,71 @@ +// Verilog for library /research/ece/lnis/USERS/brown/Skywater/lib/SCRIPTS/liberate/netlists/Verilog/sclib_SKYWATER130_tt created by Liberate 19.2.1.591 on Wed Dec 2 19:03:48 MST 2020 for SDF version 2.1 + +// type: scs8hd_muxinv8_1 +`timescale 1ns/10ps +`celldefine +module scs8hd_muxinv2_1 (Z, Q1, Q2, S0, S0B, S1, S1B); + output Z; + input Q1, Q2, S0, S0B, S1, S1B; + + wire Q1__bar, Q2__bar; + + not (Q2__bar, Q2); + not (Q1__bar, Q1); + + bufif1 (Z, Q1__bar, S0); + bufif1 (Z, Q2__bar, S1); + +`ifdef ENABLE_SIGNAL_INITIALIZATION + initial begin + $deposit(Q1, 1'b0); + $deposit(Q2, 1'b0); + end +`endif + + specify + (Q1 => Z) = 0.01; + (Q2 => Z) = 0.01; + (S0 => Z) = 0.01; + (S0B => Z) = 0.01; + (S1 => Z) = 0.01; + (S1B => Z) = 0.01; + endspecify +endmodule +`endcelldefine + +// type: scs8hd_muxinv8_1 +`timescale 1ns/10ps +`celldefine +module scs8hd_muxinv3_1 (Z, Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B); + output Z; + input Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B; + + wire Q1__bar, Q2__bar, Q3__bar; + + not (Q3__bar, Q3); + not (Q2__bar, Q2); + not (Q1__bar, Q1); + + bufif1 (Z, Q1__bar, S0); + bufif1 (Z, Q2__bar, S1); + bufif1 (Z, Q3__bar, S2); + +`ifdef ENABLE_SIGNAL_INITIALIZATION + initial begin + $deposit(Q1, 1'b0); + $deposit(Q2, 1'b0); + $deposit(Q3, 1'b0); + end +`endif + + // Timing + specify + (Q1 => Z) = 0.01; + (Q3 => Z) = 0.01; + (S0 => Z) = 0.01; + (S0B => Z) = 0.01; + (S2 => Z) = 0.01; + (S2B => Z) = 0.01; + endspecify +endmodule +`endcelldefine diff --git a/MSIM/common/run_post_pnr_msim_task.py b/MSIM/common/run_post_pnr_msim_task.py index 09b538e..f0ffff2 100644 --- a/MSIM/common/run_post_pnr_msim_task.py +++ b/MSIM/common/run_post_pnr_msim_task.py @@ -30,6 +30,8 @@ parser.add_argument('--testbench_dir_name', required=True, help='Specify the directory path for the Verilog testbenches') parser.add_argument('--task_name', required=True, help='Specify the directory path for the Verilog testbenches') +parser.add_argument('--testbench_type', default="postpnr", + help='Specify the type of verification: postpnr|prepnr') args = parser.parse_args() ##################################################################### @@ -37,7 +39,7 @@ args = parser.parse_args() ##################################################################### logging.info("Finding testbenches..."); -testbench_dir_abspath = abspath(args.testbench_dir_name) + "/postpnr/verilog_testbench"; +testbench_dir_abspath = abspath(args.testbench_dir_name) + "/" + args.testbench_type + "/verilog_testbench"; testbench_files = [] for globbed_file in glob.glob(testbench_dir_abspath + "/*_include_netlists.v"): @@ -49,7 +51,7 @@ logging.info("Found " + str(len(testbench_files)) + " testbenches") # Try to create the directory of Modelsim projects ##################################################################### parent_dir_abspath = dirname(dirname(abspath(__file__))) -msim_task_dir_abspath = abspath(parent_dir_abspath + "/" + args.task_name) + "/postpnr/verilog_testbench"; +msim_task_dir_abspath = abspath(parent_dir_abspath + "/" + args.task_name) + "/" + args.testbench_type + "/verilog_testbench"; os.makedirs(msim_task_dir_abspath, exist_ok=True) #####################################################################