From c34c777409db99f05caa0c02af8f4696f743199d Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Wed, 20 Jan 2021 21:18:38 -0800 Subject: [PATCH] Using custom yosys script for benchmarks run in generate_testbench task --- .../generate_testbench/config/task_template.conf | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf index b68fe46..be53569 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf @@ -60,27 +60,43 @@ bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3. bench1_top = and2_latch bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench2_top = bin2bcd +bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench3_top = counter +bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench4_top = routing_test +bench4_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys # RS decoder needs 1.5k LUT4, exceeding device capacity bench5_top = rs_decoder_top +bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench6_top = top_module +bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench7_top = and2_or2 +bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench8_top = cavlc_top +bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys #bench9_top = cf_fft_256_8 bench10_top = counter120bitx5 +bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench11_top = top +bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench12_top = dct_mac +bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys #bench13_top = des_perf bench14_top = diffeq_f_systemC +bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys #bench15_top = i2c_master_top #bench16_top = iir bench17_top = jpeg_qnr +bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench18_top = multi_enc_decx2x4 +bench18_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys #bench19_top = sdc_controller bench20_top = sha256 +bench20_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench21_top = unsigned_mult_80 +bench21_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys bench22_top = io_tc1 +bench22_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] #end_flow_with_test=