From 64d1113461a41e79847ecd0ba270613e92eba065 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 5 Nov 2020 10:18:52 -0700
Subject: [PATCH] [HDL] Add HDL codes for the FPGA I/O cell tuned for Caravel

---
 HDL/common/digital_io_hd.v | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/HDL/common/digital_io_hd.v b/HDL/common/digital_io_hd.v
index 5267d22..b1431a3 100644
--- a/HDL/common/digital_io_hd.v
+++ b/HDL/common/digital_io_hd.v
@@ -42,3 +42,22 @@ module GPOUT (
         .A	(A),
         .X	(Y) );
 endmodule
+
+//-----------------------------------------------------
+// Function    : A minimum embedded I/O
+//               just an overlay to interface other components
+//-----------------------------------------------------
+module EMBEDDED_IO (
+  input SOC_IN, // Input to drive the inpad signal
+  output SOC_OUT, // Output the outpad signal
+  output SOC_DIR, // Output the directionality
+  output FPGA_IN, // Input data to FPGA
+  input FPGA_OUT, // Output data from FPGA
+  input FPGA_DIR // direction control 
+);
+
+  assign FPGA_IN = SOC_IN;
+  assign SOC_OUT = FPGA_OUT;
+  assign SOC_DIR = FPGA_DIR;
+endmodule
+