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Commented out shift_register mode in k4_N8 VPR architecture. 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2021-02-04 15:08:58 +01:00
parent da52aa67eb
commit 63f210bc3d
1 changed files with 13 additions and 0 deletions
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13
ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -630,6 +630,18 @@ Authors: Xifan Tang
</mode> </mode>
<!-- 4-LUT mode definition end --> <!-- 4-LUT mode definition end -->
<!-- Define shift register begin --> <!-- Define shift register begin -->
<!-- FIXME: Presence of a disabled mode with .latch site inside sometimes triggers
the VPR bug: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1655
FIXME: There is a bug in the following mode which prevents the
first register input from reaching the regular routing network.
Once both issues are fixed then the mode may be uncommented (and
enabled).
-->
<!--
<mode name="shift_register" disable_packing="true"> <mode name="shift_register" disable_packing="true">
<pb_type name="shift_reg" num_pb="1"> <pb_type name="shift_reg" num_pb="1">
<input name="reg_in" num_pins="1"/> <input name="reg_in" num_pins="1"/>
@ -657,6 +669,7 @@ Authors: Xifan Tang
<direct name="direct4" input="fle.clk" output="shift_reg.clk"/> <direct name="direct4" input="fle.clk" output="shift_reg.clk"/>
</interconnect> </interconnect>
</mode> </mode>
-->
<!-- Define shift register end --> <!-- Define shift register end -->
</pb_type> </pb_type>
<interconnect> <interconnect>