From 6344bb420df5d4bc9ba14ffbaf54bedff062d189 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 13 Nov 2020 09:47:32 -0700 Subject: [PATCH] [Script] Remove out-of-data task run --- .../generate_fabric/config/task_template.conf | 0 .../generate_sdc/config/task_template.conf | 0 .../config/task_template.conf | 0 .../generate_fabric/config/task_template.conf | 0 .../generate_sdc/config/task_template.conf | 0 .../config/task_template.conf | 0 .../generate_fabric/config/task_template.conf | 37 ------------------- .../generate_sdc/config/task_template.conf | 36 ------------------ .../config/task_template.conf | 37 ------------------- .../generate_fabric/config/task_template.conf | 37 ------------------- .../generate_sdc/config/task_template.conf | 36 ------------------ .../config/task_template.conf | 37 ------------------- .../generate_fabric/config/task_template.conf | 37 ------------------- .../generate_sdc/config/task_template.conf | 36 ------------------ .../config/task_template.conf | 37 ------------------- .../generate_fabric/config/task_template.conf | 37 ------------------- .../generate_sdc/config/task_template.conf | 36 ------------------ .../config/task_template.conf | 37 ------------------- .../generate_fabric/config/task_template.conf | 37 ------------------- .../generate_sdc/config/task_template.conf | 36 ------------------ .../config/task_template.conf | 37 ------------------- .../generate_fabric/config/task_template.conf | 37 ------------------- .../generate_sdc/config/task_template.conf | 36 ------------------ .../config/task_template.conf | 37 ------------------- .../generate_fabric/config/task_template.conf | 37 ------------------- .../generate_sdc/config/task_template.conf | 36 ------------------ .../config/task_template.conf | 37 ------------------- .../generate_fabric/config/task_template.conf | 37 ------------------- .../generate_sdc/config/task_template.conf | 36 ------------------ .../config/task_template.conf | 37 ------------------- 30 files changed, 880 deletions(-) rename SCRIPT/skywater_openfpga_task/{k4_non_adder_caravel_cc_fdhd_12x12 => k4_N8_caravel_cc_fdhd_12x12}/generate_fabric/config/task_template.conf (100%) rename SCRIPT/skywater_openfpga_task/{k4_non_adder_caravel_cc_fdhd_12x12 => k4_N8_caravel_cc_fdhd_12x12}/generate_sdc/config/task_template.conf (100%) rename SCRIPT/skywater_openfpga_task/{k4_non_adder_caravel_cc_fdhd_12x12 => k4_N8_caravel_cc_fdhd_12x12}/generate_testbench/config/task_template.conf (100%) rename SCRIPT/skywater_openfpga_task/{k4_non_adder_caravel_cc_fdhd_2x2 => k4_N8_caravel_cc_fdhd_2x2}/generate_fabric/config/task_template.conf (100%) rename SCRIPT/skywater_openfpga_task/{k4_non_adder_caravel_cc_fdhd_2x2 => k4_N8_caravel_cc_fdhd_2x2}/generate_sdc/config/task_template.conf (100%) rename SCRIPT/skywater_openfpga_task/{k4_non_adder_caravel_cc_fdhd_2x2 => k4_N8_caravel_cc_fdhd_2x2}/generate_testbench/config/task_template.conf (100%) delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_fabric/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_sdc/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_testbench/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_fabric/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_sdc/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_testbench/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_fabric/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_sdc/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_testbench/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_fabric/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_sdc/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_testbench/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_fabric/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_sdc/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_fabric/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_sdc/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_testbench/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_fabric/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_sdc/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_testbench/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_fabric/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_sdc/config/task_template.conf delete mode 100644 SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_testbench/config/task_template.conf diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf similarity index 100% rename from SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf rename to SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf similarity index 100% rename from SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf rename to SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf similarity index 100% rename from SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf rename to SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf similarity index 100% rename from SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf rename to SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf similarity index 100% rename from SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf rename to SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf similarity index 100% rename from SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf rename to SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_fabric/config/task_template.conf deleted file mode 100644 index 222b4c8..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdhd_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdhd_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_sdc/config/task_template.conf deleted file mode 100644 index 071db85..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,36 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdhd_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_testbench/config/task_template.conf deleted file mode 100644 index 4f61490..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdhd_2x2/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_FPGA_2x2_fdhd_cc -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_fabric/config/task_template.conf deleted file mode 100644 index 489f679..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdhs_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdhs_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_sdc/config/task_template.conf deleted file mode 100644 index 9cee614..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,36 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdhs_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_testbench/config/task_template.conf deleted file mode 100644 index b99b766..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdhs_2x2/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_FPGA_2x2_fdhs_cc -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdhs_cc/SRC/fabric_netlists.v - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_fabric/config/task_template.conf deleted file mode 100644 index fbec199..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdhvl_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdhvl_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_sdc/config/task_template.conf deleted file mode 100644 index 1eb498a..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,36 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdhvl_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_testbench/config/task_template.conf deleted file mode 100644 index 64aeb5f..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdhvl_2x2/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_FPGA_2x2_fdhvl_cc -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdhvl_cc/SRC/fabric_netlists.v - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_fabric/config/task_template.conf deleted file mode 100644 index fec8a5a..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdls_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdls_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_sdc/config/task_template.conf deleted file mode 100644 index 5bded8e..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,36 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdls_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_testbench/config/task_template.conf deleted file mode 100644 index cb4936e..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdls_2x2/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_FPGA_2x2_fdls_cc -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdls_cc/SRC/fabric_netlists.v - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_fabric/config/task_template.conf deleted file mode 100644 index 292f8a2..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdms_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdms_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_sdc/config/task_template.conf deleted file mode 100644 index 72f8188..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,36 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_fdms_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf deleted file mode 100644 index ae0ece2..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_fdms_2x2/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_FPGA_2x2_fdms_cc -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdms_cc/SRC/fabric_netlists.v - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_fabric/config/task_template.conf deleted file mode 100644 index b51e760..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_ndafdms_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_ndafdms_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_sdc/config/task_template.conf deleted file mode 100644 index ead0080..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,36 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_FPGA_2x2_ndafdms_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_testbench/config/task_template.conf deleted file mode 100644 index 0315787..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_cc_ndafdms_2x2/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_FPGA_2x2_ndafdms_cc -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_FPGA_2x2_fdms_cc/SRC/fabric_netlists.v - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_adder_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_fabric/config/task_template.conf deleted file mode 100644 index 21ae463..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_FPGA_2x2_fdhd_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_FPGA_2x2_fdhd_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_sdc/config/task_template.conf deleted file mode 100644 index cd6665a..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,36 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_FPGA_2x2_fdhd_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_testbench/config/task_template.conf deleted file mode 100644 index 1a6a378..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_FPGA_2x2_fdhd_cc -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_fabric/config/task_template.conf deleted file mode 100644 index b02676b..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_fabric/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_sdc/config/task_template.conf deleted file mode 100644 index 9d1bbfa..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_sdc/config/task_template.conf +++ /dev/null @@ -1,36 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_testbench/config/task_template.conf deleted file mode 100644 index ecb57ea..0000000 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_embedded_io_cc_fdhd_2x2/generate_testbench/config/task_template.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga -openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 -openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc -openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_embedded_io_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v - -[ARCHITECTURES] -arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test=