diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index bf49476..8e19984 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -579,6 +579,10 @@
         <!-- We use direct connections to reduce the area to the most
              The global local routing is going to compensate the loss in routability
           -->
+        <!-- FIXME: The implicit port definition results in I0[0] connected to
+                    in[2]. Such twisted connection is not expected.
+                    I[0] should be connected to in[0]
+          -->
         <direct name="direct_fle0" input="clb.I0" output="fle[0:0].in[0:2]">
           <!-- TODO: Timing should be backannotated from post-PnR results -->
         </direct>