diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v index c1b7265..3891371 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -17,8 +17,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `ifdef AUTOCHECKED_SIMULATION `include "and2_latch_output_verilog.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v index 8851916..3486b82 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,31 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:92f909b526ee576979b1a02b23171c242ff03e62d862f06413b6a5236e5377cb -size 1478 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_latch_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v index 694c7f1..5e8fe9c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -17,8 +17,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `ifdef AUTOCHECKED_SIMULATION `include "and2_or2_output_verilog.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v index 7354521..45cf601 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,31 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:825a6a406d866bda71202b39eb897b967484f3dc7c3cf7a62aa18791e54df573 -size 1474 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_or2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 24d1f7b..3bb3a24 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -17,8 +17,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `ifdef AUTOCHECKED_SIMULATION `include "and2_output_verilog.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v index 40df803..3db9134 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,31 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:9f6df360605df5a436036afc2ccf3b950ce42b3c9ea396350cd4ebbb4d705b9d -size 1466 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index 0f03de9..9ae6575 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -1,3 +1,28 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:f3da10525b0dff707611379ed6ae1348c294eae1a8cd31499ce2e35dde3beaab -size 1329 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 67960 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/ccff_test_post_pnr.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v index 838b868..1946f9c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,30 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:06bb3d6a1ee52298d3ac59ad73f16132b268c013b3cb411d0dfe6f033f6aed36 -size 1488 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 67960 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v index 3f49591..3a4654c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -17,8 +17,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `ifdef AUTOCHECKED_SIMULATION `include "routing_test_output_verilog.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v index 7139452..e4a342c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,31 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:3adff4e62fe53b8cef99dc752bab3ebc6890445d6263b3aad5fdec154f53fbcf -size 1482 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "routing_test_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index ae327f8..e2a7f73 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -1,3 +1,28 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:f25455fe75150d87bcfb386c5c953172a1712655ec1e38017d22aeb062314a6d -size 1328 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_SCANCHAIN_SIZE 2304 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v index 5694280..9b12e2c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,30 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:c3b64adf49892e8d7e7263273e76b566cb1f0922d404c224d550136d43b49178 -size 1487 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_SCANCHAIN_SIZE 2304 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v new file mode 100644 index 0000000..9d4b256 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -0,0 +1,29 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_latch_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..540d182 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,31 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_latch_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v new file mode 100644 index 0000000..7b2d42a --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -0,0 +1,29 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Sun Nov 22 13:37:06 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_or2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..cf3bb8f --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,31 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_or2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v new file mode 100644 index 0000000..3d84fa3 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -0,0 +1,29 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..4a7d602 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,31 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..b1183c5 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -0,0 +1,28 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 78765 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/ccff_test_post_pnr.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..0b6a7f4 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,30 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 78765 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..8acf961 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -0,0 +1,29 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Fri Nov 20 15:48:54 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "routing_test_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..74e2be5 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,31 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "routing_test_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..84b99ba --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -0,0 +1,28 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_SCANCHAIN_SIZE 2304 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..4822ff7 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,30 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_SCANCHAIN_SIZE 2304 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v"