mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #24 from LNIS-Projects/xt_dev
Add Post-PnR Testbench for AND2_LATCH Benchmark
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Laboratory for Nano Integrated Systems (LNIS)
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@ -3,10 +3,10 @@
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FPGA Overview
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-------------
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.. _fpga_arch_generality:
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.. _fpga_arch_overview:
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Generality
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~~~~~~~~~~
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Architecture Overview
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~~~~~~~~~~~~~~~~~~~~~
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:numref:`fig_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric.
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The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric.
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@ -30,30 +30,33 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
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.. table:: FPGA tile type and functionalities
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+------+----------+---------------------------------------------+
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+------+----------+----------------------------------------------+
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| Type | Capacity | Description |
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+======+==========+=============================================+
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| CLB | 144 | Each CLB tile consists of |
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| | | - a Configurable Logic Block (CLB) |
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| | | - a X-direction Connection Block (CBx) |
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| | | - a Y-direction Connection Block (CBy) |
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| | | - a Switch Block (SB). |
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| | | This is the majority tile across the fabric |
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+======+==========+==============================================+
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| CLB | 144 || Each CLB tile consists of |
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| | || - a Configurable Logic Block (CLB) |
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| | || - a X-direction Connection Block (CBx) |
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| | || - a Y-direction Connection Block (CBy) |
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| | || - a Switch Block (SB). |
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| | | |
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| | || This is the majority tile across the fabric |
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| | | to implement logics and registers. |
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+------+----------+---------------------------------------------+
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| IO-A | 36 | The type-A I/O is a low-density I/O tile |
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| | | which is designed to mainly interface the |
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| | | the GPIOs of the SoC. |
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| | | Each I/O-A tile consists of 1 digitial I/O |
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+------+----------+----------------------------------------------+
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| IO-A | 36 || The type-A I/O is a low-density I/O tile |
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| | | which is designed to mainly interface |
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| | || the GPIOs of the SoC. |
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| | | |
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| | || Each I/O-A tile consists of 1 digitial I/O |
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| | | cell. |
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+------+----------+---------------------------------------------+
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| IO-B | 12 | The type-B I/O is a high-density I/O tile |
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| | | which is designed to mainly interface the |
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| | | the wishbone interface and logic analyzer |
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+------+----------+----------------------------------------------+
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| IO-B | 12 || The type-B I/O is a high-density I/O tile |
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| | | which is designed to mainly interface |
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| | || the wishbone interface and logic analyzer |
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| | | of the SoC. |
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| | | Each I/O-B tile consists of 9 digitial I/O |
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| | | |
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| | || Each I/O-B tile consists of 9 digitial I/O |
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| | | cells. |
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+------+----------+---------------------------------------------+
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+------+----------+----------------------------------------------+
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.. _fpga_arch_scan_chain:
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@ -37,19 +37,22 @@ Recommended Operating Conditions
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.. table:: Recommended Operating Conditions
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+----------+------------------------------+------+------+-------+
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| Symbol | Description | Min | Max | Units |
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+==========+==============================+======+======+=======+
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| VDD_io | Supply voltage for I/Os | TBD | TBD | V |
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+----------+------------------------------+------+------+-------+
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| VDD_core | Supply voltage for FPGA core | TBD | TBD | V |
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+----------+------------------------------+------+------+-------+
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| V_in | Input voltage for other I/Os | TBD | TBD | V |
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+----------+------------------------------+------+------+-------+
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| I_in | Maximum current through pins | N/A | TBD | mA |
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+----------+------------------------------+------+------+-------+
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| f_max | Maximum frequency of I/Os | N/A | TBD | MHz |
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+----------+------------------------------+------+------+-------+
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+----------+------------------------------+------+---------+------+-------+
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| Symbol | Description | Min | Typical | Max | Units |
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+==========+==============================+======+=========+======+=======+
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| VDD_io | Supply voltage for I/Os | 1.8 | 3.3 | 5.0 | V |
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+----------+------------------------------+------+---------+------+-------+
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| VDD_core | Supply voltage for FPGA core | 1.62 | 1.8 | 1.98 | V |
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+----------+------------------------------+------+---------+------+-------+
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| V_in | Input voltage for other I/Os | TBD | 3.3 | TBD | V |
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+----------+------------------------------+------+---------+------+-------+
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| I_in | Maximum current through pins | N/A | TBD | TBD | mA |
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+----------+------------------------------+------+---------+------+-------+
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| f_max | Maximum frequency of I/Os | N/A | TBD | TBD | MHz |
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+----------+------------------------------+------+---------+------+-------+
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.. note:: Threshold voltage of logic `1` for I/O (V_OH) is 0.8 * VDD_io. In other words, V_in should be at least 2.64V in order to be sensed as logic `1`
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.. note:: Threshold voltage of logic `0` for I/O (V_OH) is 0.4. In other words, V_in should not exceed 0.4V in order to be sensed as logic `0`.
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Typical AC Characteristics
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^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -0,0 +1,11 @@
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.. _device_overview:
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General Description
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-------------------
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All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII.
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All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK.
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The devices are embedded FPGA IPs, which are designed to interface the caravel SoC interface.
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We aims to empower embedded applications with its low-cost design approach but high-density architecture.
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Operating temperature ranging from 0 :math:`^\circ C` to 85 :math:`^\circ C`
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@ -0,0 +1,38 @@
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.. _device_resource:
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Device Resources
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----------------
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.. _device_resource_hd_fpga:
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High-Density FPGA
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~~~~~~~~~~~~~~~~~
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The High Density (HD) FPGA is an embedded FPGA built with the Skywater 130nm High Density Standard Cell library (`Sky130_fd_SC_HD <https://cs.opensource.google/skywater-pdk/skywater-pdk/+/master:libraries/sky130_fd_sc_hd/>`_).
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.. table:: Logic capacity of High Density (HD) FPGA IP
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+-------------------------------+------------+
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| Resource Type | Capacity |
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+===============================+============+
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| Look-Up Tables [1]_ | 1152 |
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+-------------------------------+------------+
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| Flip-flops | 2204 |
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+-------------------------------+------------+
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| Max. Configuration Speed [2]_ | 50MHz |
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+-------------------------------+------------+
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| Max. Operating Speed [2]_ | 50MHz |
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+-------------------------------+------------+
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| User I/O Pins [3]_ | 144 |
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+-------------------------------+------------+
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| Max. I/O Speed [2]_ | 33MHz |
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+-------------------------------+------------+
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| Core Voltage | 1.8V |
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+-------------------------------+------------+
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.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT.
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.. [2] bounded by the maximum speed of `GPIO cells of Skywater 130nm PDK <https://skywater-pdk.readthedocs.io/en/latest/contents/libraries/sky130_fd_io/docs/user_guide.html#design-metrics-1>`_. Higher speed may be expected when a high-speed GPIO cell is available.
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.. [3] I/Os are divided into two groups: GPIO and embedded I/O. See details in :ref:`io_resource`.
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@ -0,0 +1,11 @@
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.. _device:
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Device Datasheet
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.. toctree::
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:maxdepth: 2
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device_overview
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device_resource
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dc_ac_character
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@ -1,38 +0,0 @@
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.. _device_family:
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Overview
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||||
--------
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|
||||
All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII.
|
||||
All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK.
|
||||
The devices are embedded FPGA IPs, which are designed to interface the caravel SoC interface.
|
||||
We aims to empower embedded applications with its low-cost design approach but high-density architecture.
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- Native support on shift registers
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- Operating temperature ranging from 0 :math:`^\circ C` to 85 :math:`^\circ C`
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|
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|
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.. table:: Logic capacity of High Density (HD) FPGA IP
|
||||
|
||||
+--------------------------+------------+
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||||
| Resource Type | Capacity |
|
||||
+==========================+============+
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||||
| Look-Up Tables [1]_ | 1152 |
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+--------------------------+------------+
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| Flip-flops | 2204 |
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||||
+--------------------------+------------+
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||||
| Max. Configuration Speed | TBD |
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||||
+--------------------------+------------+
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||||
| Max. Operating Speed | TBD |
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||||
+--------------------------+------------+
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| User I/O Pins | 144 |
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+--------------------------+------------+
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||||
| Max. I/O Speed | TBD |
|
||||
+--------------------------+------------+
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||||
| Core Voltage | 1.8V |
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||||
+--------------------------+------------+
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||||
|
||||
.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT.
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|
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@ -7,15 +7,13 @@ Welcome to SKywater-OpenFPGA documentation!
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===========================================
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.. toctree::
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:caption: Device
|
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:caption: Device Datasheet
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|
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device_family
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dc_ac_character
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device/index
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.. toctree::
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:maxdepth: 2
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:caption: Architecture
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:caption: FPGA Architecture
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arch/index
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@ -23,9 +21,9 @@ Welcome to SKywater-OpenFPGA documentation!
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:maxdepth: 2
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:caption: Appendix
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contact
|
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tail/contact
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acknowledgment
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tail/acknowledgment
|
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For more information on the OpenFPGA see openfpga_doc_ or openfpga_github_
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@ -0,0 +1,70 @@
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Netlist Summary
|
||||
// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Wed Nov 11 16:01:30 2020
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//-------------------------------------------
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//----- Time scale -----
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||||
`timescale 1ns / 1ps
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// ------ Include simulation defines -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
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|
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// ------ Include Skywater cell netlists -----
|
||||
// Cells already used pre-PnR
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
|
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
|
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|
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// Cells added due to their use in PnR
|
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v"
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "and2_latch_output_verilog.v"
|
||||
`endif
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v"
|
||||
`endif
|
||||
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
// ------ Include simulation defines -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/define_simulation.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
|
||||
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue