diff --git a/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
new file mode 100644
index 0000000..795f4e7
--- /dev/null
+++ b/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -0,0 +1,441 @@
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diff --git a/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
new file mode 100644
index 0000000..8bb01f5
--- /dev/null
+++ b/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -0,0 +1,255 @@
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diff --git a/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
new file mode 100644
index 0000000..dab674f
--- /dev/null
+++ b/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -0,0 +1,258 @@
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diff --git a/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml b/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
new file mode 100644
index 0000000..001f4aa
--- /dev/null
+++ b/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
@@ -0,0 +1,335 @@
+
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diff --git a/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
new file mode 100644
index 0000000..b4c25de
--- /dev/null
+++ b/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -0,0 +1,272 @@
+
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+ 10e-12
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+ 10e-12 5e-12
+
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diff --git a/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
new file mode 100644
index 0000000..3ea3f5e
--- /dev/null
+++ b/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -0,0 +1,268 @@
+
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12 5e-12
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+ 10e-12 5e-12
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diff --git a/ARCH/openfpga_arch/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml
new file mode 100644
index 0000000..868bb0d
--- /dev/null
+++ b/ARCH/openfpga_arch/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml
@@ -0,0 +1,250 @@
+
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+ 10e-12
+
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 4f47d51..fea9a5a 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -55,6 +55,17 @@
+
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@@ -412,7 +423,7 @@
-
+
@@ -469,21 +480,23 @@
${LUT3_DELAY}
-
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-
+
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_bitstream/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_bitstream/config/task.conf
new file mode 100644
index 0000000..6d8bc39
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_bitstream/config/task.conf
@@ -0,0 +1,53 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=40
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+bench1=/home/apond/sofa/BENCHMARK/and2_latch/and2_latch.v
+bench2=/home/apond/sofa/BENCHMARK/bin2bcd/bin2bcd.v
+bench3=/home/apond/sofa/BENCHMARK/counter/counter.v
+bench4=/home/apond/sofa/BENCHMARK/routing_test/routing_test.v
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5=/home/apond/sofa/BENCHMARK/rs_decoder/rtl/rs_decoder.v
+bench6=/home/apond/sofa/BENCHMARK/simon_bit_serial/rtl/*.v
+bench7=/home/apond/sofa/BENCHMARK/and2_or2/and2_or2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench1_top = and2_latch
+bench2_top = bin2bcd
+bench3_top = counter
+bench4_top = routing_test
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5_top = rs_decoder_top
+bench6_top = top_module
+bench7_top = and2_or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task.conf
new file mode 100644
index 0000000..5f26078
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task.conf
@@ -0,0 +1,39 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=40
+openfpga_verilog_output_dir=/home/apond/sofa/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc
+openfpga_sdc_output_dir=/home/apond/sofa/SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task.conf
new file mode 100644
index 0000000..fc73bf0
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=40
+openfpga_sdc_output_dir=/home/apond/sofa/SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task.conf
new file mode 100644
index 0000000..3c2c4fa
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task.conf
@@ -0,0 +1,55 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=40
+openfpga_verilog_output_dir=/home/apond/sofa/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr
+openfpga_fabric_verilog_netlist=/home/apond/sofa/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+bench1=/home/apond/sofa/BENCHMARK/and2_latch/and2_latch.v
+bench2=/home/apond/sofa/BENCHMARK/bin2bcd/bin2bcd.v
+bench3=/home/apond/sofa/BENCHMARK/counter/counter.v
+bench4=/home/apond/sofa/BENCHMARK/routing_test/routing_test.v
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5=/home/apond/sofa/BENCHMARK/rs_decoder/rtl/rs_decoder.v
+bench6=/home/apond/sofa/BENCHMARK/simon_bit_serial/rtl/*.v
+bench7=/home/apond/sofa/BENCHMARK/and2_or2/and2_or2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench1_top = and2_latch
+bench2_top = bin2bcd
+bench3_top = counter
+bench4_top = routing_test
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5_top = rs_decoder_top
+bench6_top = top_module
+bench7_top = and2_or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task.conf
new file mode 100644
index 0000000..5dd66af
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task.conf
@@ -0,0 +1,39 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_verilog_output_dir=/home/apond/sofa/HDL/k4_N8_caravel_io_FPGA_2x2_fdhd_cc
+openfpga_sdc_output_dir=/home/apond/sofa/SDC/k4_N8_caravel_io_FPGA_2x2_fdhd_cc
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_2x2.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task.conf
new file mode 100644
index 0000000..663d6b7
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_sdc_output_dir=/home/apond/sofa/SDC/k4_N8_caravel_io_FPGA_2x2_fdhd_cc
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_2x2.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task.conf
new file mode 100644
index 0000000..300fdcf
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task.conf
@@ -0,0 +1,41 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_verilog_output_dir=/home/apond/sofa/TESTBENCH/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/prepnr
+openfpga_fabric_verilog_netlist=/home/apond/sofa/HDL/k4_N8_caravel_io_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_2x2.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+bench1=/home/apond/sofa/BENCHMARK/and2_latch/and2_latch.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench1_top = and2_latch
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_bitstream/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_bitstream/config/task.conf
new file mode 100644
index 0000000..1f57cdf
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_bitstream/config/task.conf
@@ -0,0 +1,53 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+bench1=/home/apond/sofa/BENCHMARK/and2_latch/and2_latch.v
+bench2=/home/apond/sofa/BENCHMARK/bin2bcd/bin2bcd.v
+bench3=/home/apond/sofa/BENCHMARK/counter/counter.v
+bench4=/home/apond/sofa/BENCHMARK/routing_test/routing_test.v
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5=/home/apond/sofa/BENCHMARK/rs_decoder/rtl/rs_decoder.v
+bench6=/home/apond/sofa/BENCHMARK/simon_bit_serial/rtl/*.v
+bench7=/home/apond/sofa/BENCHMARK/and2_or2/and2_or2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench1_top = and2_latch
+bench2_top = bin2bcd
+bench3_top = counter
+bench4_top = routing_test
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5_top = rs_decoder_top
+bench6_top = top_module
+bench7_top = and2_or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task.conf
new file mode 100644
index 0000000..21cd853
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task.conf
@@ -0,0 +1,39 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60
+openfpga_verilog_output_dir=/home/apond/sofa/HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc
+openfpga_sdc_output_dir=/home/apond/sofa/SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task.conf
new file mode 100644
index 0000000..3b26e0d
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60
+openfpga_sdc_output_dir=/home/apond/sofa/SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task.conf
new file mode 100644
index 0000000..ae30a92
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task.conf
@@ -0,0 +1,55 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60
+openfpga_verilog_output_dir=/home/apond/sofa/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr
+openfpga_fabric_verilog_netlist=/home/apond/sofa/HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/fabric_netlists.v
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+bench1=/home/apond/sofa/BENCHMARK/and2_latch/and2_latch.v
+bench2=/home/apond/sofa/BENCHMARK/bin2bcd/bin2bcd.v
+bench3=/home/apond/sofa/BENCHMARK/counter/counter.v
+bench4=/home/apond/sofa/BENCHMARK/routing_test/routing_test.v
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5=/home/apond/sofa/BENCHMARK/rs_decoder/rtl/rs_decoder.v
+bench6=/home/apond/sofa/BENCHMARK/simon_bit_serial/rtl/*.v
+bench7=/home/apond/sofa/BENCHMARK/and2_or2/and2_or2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench1_top = and2_latch
+bench2_top = bin2bcd
+bench3_top = counter
+bench4_top = routing_test
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5_top = rs_decoder_top
+bench6_top = top_module
+bench7_top = and2_or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_bitstream/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_bitstream/config/task.conf
new file mode 100644
index 0000000..41d21b5
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_bitstream/config/task.conf
@@ -0,0 +1,53 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_bitstream_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+bench1=/home/apond/sofa/BENCHMARK/and2_latch/and2_latch.v
+bench2=/home/apond/sofa/BENCHMARK/bin2bcd/bin2bcd.v
+bench3=/home/apond/sofa/BENCHMARK/counter/counter.v
+bench4=/home/apond/sofa/BENCHMARK/routing_test/routing_test.v
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5=/home/apond/sofa/BENCHMARK/rs_decoder/rtl/rs_decoder.v
+bench6=/home/apond/sofa/BENCHMARK/simon_bit_serial/rtl/*.v
+bench7=/home/apond/sofa/BENCHMARK/and2_or2/and2_or2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench1_top = and2_latch
+bench2_top = bin2bcd
+bench3_top = counter
+bench4_top = routing_test
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5_top = rs_decoder_top
+bench6_top = top_module
+bench7_top = and2_or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task.conf
new file mode 100644
index 0000000..2b0bafd
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task.conf
@@ -0,0 +1,39 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60
+openfpga_verilog_output_dir=/home/apond/sofa/HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc
+openfpga_sdc_output_dir=/home/apond/sofa/SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task.conf
new file mode 100644
index 0000000..7ef4c5a
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60
+openfpga_sdc_output_dir=/home/apond/sofa/SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task.conf
new file mode 100644
index 0000000..142fee7
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task.conf
@@ -0,0 +1,55 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=12x12
+openfpga_vpr_route_chan_width=60
+openfpga_verilog_output_dir=/home/apond/sofa/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr
+openfpga_fabric_verilog_netlist=/home/apond/sofa/HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+bench1=/home/apond/sofa/BENCHMARK/and2_latch/and2_latch.v
+bench2=/home/apond/sofa/BENCHMARK/bin2bcd/bin2bcd.v
+bench3=/home/apond/sofa/BENCHMARK/counter/counter.v
+bench4=/home/apond/sofa/BENCHMARK/routing_test/routing_test.v
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5=/home/apond/sofa/BENCHMARK/rs_decoder/rtl/rs_decoder.v
+bench6=/home/apond/sofa/BENCHMARK/simon_bit_serial/rtl/*.v
+bench7=/home/apond/sofa/BENCHMARK/and2_or2/and2_or2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench1_top = and2_latch
+bench2_top = bin2bcd
+bench3_top = counter
+bench4_top = routing_test
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+#bench5_top = rs_decoder_top
+bench6_top = top_module
+bench7_top = and2_or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task.conf
new file mode 100644
index 0000000..383956a
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=32x32
+openfpga_vpr_route_chan_width=60
+openfpga_verilog_output_dir=/home/apond/sofa/HDL/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc
+openfpga_sdc_output_dir=/home/apond/sofa/SDC/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_32x32.xml
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task.conf
new file mode 100644
index 0000000..6859d2f
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task.conf
@@ -0,0 +1,40 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=32x32
+openfpga_vpr_route_chan_width=60
+openfpga_sdc_output_dir=/home/apond/sofa/SDC/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_32x32.xml
+# Yosys parameters
+yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/io_reg/io_reg.v
+
+[SYNTHESIS_PARAM]
+bench0_top = io_reg
+bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task.conf
new file mode 100644
index 0000000..1cf38d1
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task.conf
@@ -0,0 +1,106 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
+openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+openfpga_vpr_device_layout=32x32
+openfpga_vpr_route_chan_width=60
+openfpga_verilog_output_dir=/home/apond/sofa/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/prepnr
+openfpga_fabric_verilog_netlist=/home/apond/sofa/HDL/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/SRC/fabric_netlists.v
+external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_32x32.xml
+# Yosys parameters
+yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
+
+[ARCHITECTURES]
+arch0=/home/apond/sofa/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=/home/apond/sofa/BENCHMARK/and2/and2.v
+bench1=/home/apond/sofa/BENCHMARK/and2_latch/and2_latch.v
+bench2=/home/apond/sofa/BENCHMARK/bin2bcd/bin2bcd.v
+bench3=/home/apond/sofa/BENCHMARK/counter/counter.v
+bench4=/home/apond/sofa/BENCHMARK/routing_test/routing_test.v
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+bench5=/home/apond/sofa/BENCHMARK/rs_decoder/rtl/rs_decoder.v
+bench6=/home/apond/sofa/BENCHMARK/simon_bit_serial/rtl/*.v
+bench7=/home/apond/sofa/BENCHMARK/and2_or2/and2_or2.v
+# Skip cavlc benchmark because current yosys script failed in DFF mapping; Problem should be solved once the yosys script is updated
+#bench8=/home/apond/sofa/BENCHMARK/cavlc_top/rtl/*.v
+#bench9=/home/apond/sofa/BENCHMARK/cf_fft_256_8/rtl/*.v
+bench10=/home/apond/sofa/BENCHMARK/counter120bitx5/rtl/*.v
+bench11=/home/apond/sofa/BENCHMARK/counter_16bit/rtl/*.v
+bench12=/home/apond/sofa/BENCHMARK/dct_mac/rtl/*.v
+#bench13=/home/apond/sofa/BENCHMARK/des_perf/rtl/*.v
+bench14=/home/apond/sofa/BENCHMARK/diffeq_f_systemC/rtl/*.v
+#bench15=/home/apond/sofa/BENCHMARK/i2c_master_top/rtl/*.v
+#bench16=/home/apond/sofa/BENCHMARK/iir/rtl/*.v
+# Skip jpeg_qnr benchmark because current yosys script failed in DFF mapping; Problem should be solved once the yosys script is updated
+#bench17=/home/apond/sofa/BENCHMARK/jpeg_qnr/rtl/*.v
+bench18=/home/apond/sofa/BENCHMARK/multi_enc_decx2x4/rtl/*.v
+#bench19=/home/apond/sofa/BENCHMARK/sdc_controller/rtl/*.v
+bench20=/home/apond/sofa/BENCHMARK/sha256/rtl/*.v
+bench21=/home/apond/sofa/BENCHMARK/unsigned_mult_80/rtl/*.v
+bench22=/home/apond/sofa/BENCHMARK/io_tc1/rtl/*.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench1_top = and2_latch
+bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench2_top = bin2bcd
+bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench3_top = counter
+bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench4_top = routing_test
+bench4_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+# RS decoder needs 1.5k LUT4, exceeding device capacity
+bench5_top = rs_decoder_top
+bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench6_top = top_module
+bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench7_top = and2_or2
+bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench8_top = cavlc_top
+bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+#bench9_top = cf_fft_256_8
+bench10_top = counter120bitx5
+bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench11_top = top
+bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench12_top = dct_mac
+bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+#bench13_top = des_perf
+bench14_top = diffeq_f_systemC
+bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+#bench15_top = i2c_master_top
+#bench16_top = iir
+bench17_top = jpeg_qnr
+bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench18_top = multi_enc_decx2x4
+#bench18_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+#bench19_top = sdc_controller
+bench20_top = sha256
+bench20_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench21_top = unsigned_mult_80
+bench21_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench22_top = io_tc1
+bench22_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=