diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ConfigFlipFLop.png b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ConfigFlipFLop.png index eeb9b77..87815fb 100644 Binary files a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ConfigFlipFLop.png and b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ConfigFlipFLop.png differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ConfigurationChain.png b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ConfigurationChain.png index b7873a7..11cb6b0 100644 Binary files a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ConfigurationChain.png and b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ConfigurationChain.png differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ProgClockTree.png b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ProgClockTree.png index 081c547..b9157bb 100644 Binary files a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ProgClockTree.png and b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/ProgClockTree.png differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/clockTree.png b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/clockTree.png index 80167b4..a548903 100644 Binary files a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/clockTree.png and b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/clockTree.png differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met1_utilization.png b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met1_utilization.png index 8168de2..e923e58 100644 Binary files a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met1_utilization.png and b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met1_utilization.png differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met2_utilization.png b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met2_utilization.png index 6f034fb..991db89 100644 Binary files a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met2_utilization.png and b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met2_utilization.png differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met3_utilization.png b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met3_utilization.png index 53f0920..7d4c35e 100644 Binary files a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met3_utilization.png and b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met3_utilization.png differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met4_utilization.png b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met4_utilization.png index e66534a..117c902 100644 Binary files a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met4_utilization.png and b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/met4_utilization.png differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/power_contacts.png b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/power_contacts.png index a8d8bda..412b888 100644 Binary files a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/power_contacts.png and b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/power_contacts.png differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/utilization.png b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/utilization.png index 2d99cd7..254e5fe 100644 Binary files a/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/utilization.png and b/FPGA1212_SOFA_HD_PNR/fpga_top/Screenshots/utilization.png differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v index 53318a3..5c47cdb 100644 --- a/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v @@ -11,12 +11,19 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; +wire copt_net_88 ; + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( copt_net_90 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( mem_out[0] ) , - .X ( copt_net_90 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_88 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_89 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_88 ) , + .X ( copt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_86 ) , + .X ( copt_net_87 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_87 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1311 ( .A ( mem_out[0] ) , + .X ( copt_net_89 ) ) ; endmodule @@ -30,17 +37,17 @@ input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , - .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_59 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_60 ) ) ; + .TE_B ( BUF_net_59 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_59 ( .A ( BUF_net_61 ) , .Y ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_61 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -105,11 +112,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -122,11 +129,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -143,7 +150,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -181,11 +188,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -198,13 +205,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -219,11 +226,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -236,13 +243,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -424,6 +431,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_2__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -447,8 +456,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -475,8 +482,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_2__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -500,6 +505,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -665,11 +672,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -682,13 +689,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -720,13 +727,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -741,11 +748,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -764,7 +771,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -777,13 +784,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -796,13 +803,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -815,31 +822,33 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_92 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_86 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ropt_net_94 ) , + .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( ccff_head[0] ) , .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1305 ( .A ( copt_net_85 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1308 ( .A ( ccff_head[0] ) , - .X ( copt_net_86 ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1309 ( .A ( copt_net_82 ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_83 ) , - .X ( copt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1311 ( .A ( copt_net_88 ) , - .X ( copt_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( copt_net_84 ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_82 ) , + .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_93 ) , + .X ( ropt_net_94 ) ) ; endmodule @@ -927,6 +936,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cby_2__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -956,9 +967,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_67 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; endmodule @@ -1016,9 +1024,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_67 ) ) ; endmodule @@ -1135,9 +1143,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_65 ) ) ; endmodule @@ -1195,7 +1203,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1284,8 +1292,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cby_2__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1315,6 +1321,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1469,7 +1477,7 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1478,7 +1486,7 @@ cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1487,7 +1495,7 @@ cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1496,7 +1504,7 @@ cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -1505,7 +1513,7 @@ cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1514,7 +1522,7 @@ cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1523,7 +1531,7 @@ cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1532,7 +1540,7 @@ cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1541,7 +1549,7 @@ cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1593,7 +1601,7 @@ cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1601,7 +1609,7 @@ cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1609,7 +1617,7 @@ cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1617,7 +1625,7 @@ cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1625,7 +1633,7 @@ cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1633,7 +1641,7 @@ cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1641,7 +1649,7 @@ cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1649,7 +1657,7 @@ cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -1697,14 +1705,14 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( { ropt_net_91 } ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) ) ; + .X ( ctsbuf_net_177 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) ) ; + .X ( ctsbuf_net_278 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , @@ -1788,22 +1796,18 @@ sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) , sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( left_width_0_height_0__pin_1_lower[0] ) , .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_73 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3471203 ( .A ( ctsbuf_net_177 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521208 ( .A ( ctsbuf_net_278 ) , .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) ) ; endmodule @@ -1814,13 +1818,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1837,9 +1841,9 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1871,13 +1875,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1890,11 +1894,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -1909,7 +1913,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -1928,7 +1932,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -1951,7 +1955,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -1982,6 +1986,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2005,8 +2011,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -2033,8 +2037,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2058,6 +2060,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -2158,8 +2162,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -2186,8 +2191,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2211,6 +2214,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -2339,8 +2344,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2364,6 +2367,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -2374,15 +2379,29 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +wire copt_net_84 ; + +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_84 ) , + .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1316 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1317 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_81 ) , + .X ( copt_net_82 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_82 ) , + .X ( copt_net_83 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_83 ) , + .X ( mem_out[3] ) ) ; endmodule @@ -2393,7 +2412,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -2414,7 +2433,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -2431,13 +2450,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2450,13 +2469,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2469,11 +2488,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -2488,13 +2507,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2507,35 +2526,25 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_100 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_91 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( ccff_head[0] ) , - .X ( copt_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1314 ( .A ( copt_net_82 ) , - .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_83 ) , - .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1324 ( .A ( copt_net_85 ) , - .X ( copt_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1334 ( .A ( ropt_net_97 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1335 ( .A ( ropt_net_98 ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1336 ( .A ( copt_net_86 ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1339 ( .A ( ropt_net_96 ) , - .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( ropt_net_88 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_92 ) , + .X ( ropt_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_88 ) , + .X ( ropt_net_90 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1362 ( .A ( ropt_net_89 ) , + .X ( ropt_net_91 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1363 ( .A ( ropt_net_90 ) , + .X ( ropt_net_92 ) ) ; endmodule @@ -2564,6 +2573,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cby_1__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -2593,9 +2604,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_75 ) ) ; endmodule @@ -2830,8 +2838,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_59 ) ) ; endmodule @@ -3007,8 +3016,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_57 ) ) ; endmodule @@ -3123,7 +3133,7 @@ cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -3132,7 +3142,7 @@ cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -3141,7 +3151,7 @@ cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -3150,7 +3160,7 @@ cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -3159,7 +3169,7 @@ cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -3223,9 +3233,8 @@ cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { copt_net_87 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -3241,7 +3250,7 @@ cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -3257,7 +3266,7 @@ cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -3265,7 +3274,7 @@ cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -3273,7 +3282,7 @@ cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -3289,7 +3298,7 @@ cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -3332,31 +3341,32 @@ cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , - .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_W_out ) ) ; sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , - .X ( net_net_67 ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( net_net_68 ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) ) ; + .X ( ctsbuf_net_177 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) ) ; + .X ( ctsbuf_net_278 ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ropt_net_93 ) ) ; + .X ( ropt_net_87 ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ZBUF_6_f_1 ) ) ; + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( prog_clk_3_N_out ) ) ; + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( ropt_net_95 ) ) ; + .X ( prog_clk_3_S_out ) ) ; sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , .X ( clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) ) ; -sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , - .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_509_ ) ) ; sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_506_ ) ) ; + .X ( aps_rename_510_ ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , @@ -3437,43 +3447,31 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_66 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( clk_3_S_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_75 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , - .X ( clk_2_N_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , - .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , - .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , - .X ( prog_clk_2_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_509_ ) , .X ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , - .X ( copt_net_92 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_585 ( .A ( aps_rename_508_ ) , + .X ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_586 ( .A ( aps_rename_507_ ) , + .X ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_587 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1358 ( .A ( ropt_net_87 ) , .X ( prog_clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , - .X ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , - .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_177 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_278 ) , + .X ( prog_clk_0_N_out ) ) ; endmodule @@ -3484,23 +3482,23 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_55 ; +wire copt_net_60 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , - .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_60 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_60 ) , + .X ( copt_net_55 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( copt_net_55 ) , .X ( copt_net_56 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_56 ) , .X ( copt_net_57 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , .X ( copt_net_58 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , - .X ( copt_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , - .X ( copt_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_61 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1193 ( .A ( copt_net_58 ) , + .X ( copt_net_61 ) ) ; endmodule @@ -3596,17 +3594,17 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( ccff_head[0] ) , .X ( copt_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_49 ) , .X ( copt_net_50 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_50 ) , .X ( copt_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( copt_net_51 ) , .X ( copt_net_52 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_52 ) , .X ( copt_net_53 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_53 ) , .X ( copt_net_54 ) ) ; endmodule @@ -3693,10 +3691,14 @@ output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; input prog_clk_0_E_in ; -wire ropt_net_73 ; -wire ropt_net_75 ; -wire ropt_net_74 ; -wire ropt_net_72 ; +wire ropt_net_67 ; +wire ropt_net_68 ; +wire ropt_net_66 ; +wire ropt_net_65 ; +wire ropt_net_63 ; +wire ropt_net_69 ; +wire ropt_net_64 ; +wire ropt_net_62 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -3739,12 +3741,12 @@ sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , +sky130_fd_sc_hd__buf_6 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_73 ) ) ; + .X ( ropt_net_67 ) ) ; sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_75 ) ) ; + .X ( ropt_net_68 ) ) ; sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , @@ -3752,18 +3754,18 @@ sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; + .X ( ropt_net_66 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_65 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_63 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__buf_6 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; @@ -3774,7 +3776,7 @@ sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_74 ) ) ; + .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , @@ -3790,10 +3792,10 @@ sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_69 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_64 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[13] ) ) ; sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) ) ; @@ -3804,7 +3806,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_72 ) ) ; + .X ( ropt_net_62 ) ) ; sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_43__42 ( @@ -3812,14 +3814,22 @@ sky130_fd_sc_hd__buf_6 FTB_43__42 ( .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_48 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1194 ( .A ( ropt_net_62 ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1195 ( .A ( ropt_net_63 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1196 ( .A ( ropt_net_64 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1197 ( .A ( ropt_net_65 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1198 ( .A ( ropt_net_66 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1199 ( .A ( ropt_net_67 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1200 ( .A ( ropt_net_68 ) , .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1201 ( .A ( ropt_net_69 ) , + .X ( chany_bottom_out[11] ) ) ; endmodule @@ -3835,14 +3845,14 @@ wire copt_net_86 ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( copt_net_86 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_88 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_84 ) , + .X ( copt_net_83 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , + .X ( copt_net_85 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1310 ( .A ( copt_net_84 ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_86 ) , - .X ( copt_net_88 ) ) ; endmodule @@ -3858,15 +3868,14 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_61 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_64 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_61 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_61 ( .A ( BUF_net_63 ) , .Y ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_63 ) ) ; + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_64 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -3933,7 +3942,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -4250,6 +4259,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -4273,8 +4284,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -4426,7 +4435,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -4477,7 +4486,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -4493,7 +4502,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -4622,9 +4631,9 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -4641,7 +4650,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_93 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_95 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -4650,24 +4659,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( ccff_head[0] ) , + .X ( copt_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_75 ) , + .X ( copt_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_78 ) , .X ( copt_net_79 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_79 ) , .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( copt_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_82 ) , - .X ( ropt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1315 ( .A ( ropt_net_92 ) , - .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_80 ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1314 ( .A ( ropt_net_94 ) , + .X ( ropt_net_95 ) ) ; endmodule @@ -4725,7 +4732,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -4843,7 +4850,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -5050,6 +5057,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -5079,8 +5088,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -5138,8 +5145,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -5306,7 +5314,7 @@ cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -5315,7 +5323,7 @@ cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -5333,7 +5341,7 @@ cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -5342,7 +5350,7 @@ cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -5360,7 +5368,7 @@ cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -5421,7 +5429,7 @@ cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -5437,7 +5445,7 @@ cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , @@ -5453,7 +5461,7 @@ cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -5461,7 +5469,7 @@ cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -5477,7 +5485,7 @@ cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -5529,10 +5537,10 @@ cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_176 ) ) ; + .X ( ctsbuf_net_174 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , +sky130_fd_sc_hd__buf_12 FTB_20__19 ( .A ( chanx_left_in[1] ) , .X ( chanx_right_out[1] ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , .X ( chanx_right_out[2] ) ) ; @@ -5574,7 +5582,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , .X ( chanx_left_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__buf_12 FTB_41__40 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; @@ -5619,11 +5627,7 @@ sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , .HI ( optlc_net_72 ) ) ; sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , .HI ( optlc_net_73 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_74 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521203 ( .A ( ctsbuf_net_174 ) , .X ( prog_clk_0_W_out ) ) ; endmodule @@ -5637,11 +5641,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5656,9 +5660,9 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -5696,7 +5700,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -5751,7 +5755,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -5905,8 +5909,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -5930,6 +5932,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -5979,7 +5983,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -6109,8 +6113,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -6134,6 +6136,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -6183,7 +6187,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -6195,29 +6199,25 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -wire copt_net_81 ; +wire copt_net_84 ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_81 ) ) ; -sky130_fd_sc_hd__buf_4 FTB_8__7 ( .A ( copt_net_83 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_81 ) , - .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( mem_out[3] ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_84 ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_87 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , - .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_85 ) , + .X ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_84 ) , + .X ( copt_net_87 ) ) ; endmodule @@ -6234,7 +6234,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -6342,7 +6342,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_79 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_103 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -6351,18 +6351,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( ccff_head[0] ) , - .X ( copt_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_74 ) , - .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_75 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , .X ( copt_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_76 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( ccff_head[0] ) , .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_78 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1323 ( .A ( copt_net_81 ) , + .X ( ropt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1324 ( .A ( ropt_net_102 ) , + .X ( ropt_net_103 ) ) ; endmodule @@ -6420,7 +6424,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -6450,8 +6454,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -6481,6 +6483,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -6908,7 +6912,6 @@ input clk_3_E_in ; output clk_3_E_out ; output clk_3_W_out ; -wire ropt_net_94 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -6968,7 +6971,7 @@ cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -6977,7 +6980,7 @@ cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -6986,7 +6989,7 @@ cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -7004,7 +7007,7 @@ cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -7022,7 +7025,7 @@ cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -7059,9 +7062,8 @@ cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_100 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -7069,7 +7071,7 @@ cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -7077,7 +7079,7 @@ cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -7085,7 +7087,7 @@ cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -7093,7 +7095,7 @@ cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -7101,7 +7103,7 @@ cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -7117,7 +7119,7 @@ cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -7165,31 +7167,30 @@ cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_173 ) ) ; + .X ( ctsbuf_net_175 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( net_net_69 ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_70 ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_71 ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( clk_3_W_out ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , @@ -7273,34 +7274,29 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) , sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , .X ( REGOUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( prog_clk_1_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , - .Y ( prog_clk_1_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_67 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_69 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_70 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_71 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( net_net_69 ) , + .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( net_net_70 ) , .X ( clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , .HI ( optlc_net_72 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_73 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_79 ( .A ( aps_rename_507_ ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_506_ ) , + .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_175 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , - .X ( SC_OUT_TOP ) ) ; endmodule @@ -7311,23 +7307,21 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_124 ; +wire copt_net_122 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_124 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_122 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_119 ) , - .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_124 ) , - .X ( copt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_118 ) , - .X ( copt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_122 ) , +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1346 ( .A ( copt_net_124 ) , .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , - .X ( copt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_120 ) , - .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( copt_net_125 ) , + .X ( copt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_126 ) , + .X ( copt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_127 ) , + .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_122 ) , + .X ( copt_net_127 ) ) ; endmodule @@ -7342,17 +7336,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_511_ ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_88 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( BUF_net_88 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_112 ( .A ( BUF_net_90 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_90 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -7432,16 +7426,13 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_85 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_85 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( BUF_net_85 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_87 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_87 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; endmodule @@ -7522,15 +7513,16 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_82 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_87 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_86 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_86 ( .A ( BUF_net_88 ) , .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_88 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_88 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -7611,16 +7603,14 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_508_ ) , - .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_84 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_81 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -7700,16 +7690,13 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_76 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( net_net_80 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_76 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_76 ( .A ( BUF_net_78 ) , .Y ( BUF_net_76 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_78 ) ) ; + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( SOC_DIR ) ) ; endmodule @@ -7789,16 +7776,19 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_73 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_507_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_73 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_73 ( .A ( BUF_net_75 ) , .Y ( BUF_net_73 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_75 ) ) ; + .TE_B ( BUF_net_77 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_77 ( .A ( BUF_net_79 ) , .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( BUF_net_78 ) , .Y ( BUF_net_107 ) ) ; endmodule @@ -7868,7 +7858,7 @@ endmodule module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_184_0 ) ; + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_211_0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7876,22 +7866,22 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_211_0 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( ZBUF_184_0 ) , .Z ( SOC_OUT ) ) ; + .TE_B ( ZBUF_211_0 ) , .Z ( SOC_OUT ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , - iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_184_0 ) ; + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -7901,7 +7891,7 @@ input [0:0] iopad_outpad ; input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; wire [0:0] EMBEDDED_IO_HD_0_en ; @@ -7911,7 +7901,7 @@ cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , - .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .ZBUF_211_0 ( ZBUF_211_0 ) ) ; cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; @@ -7921,7 +7911,7 @@ endmodule module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , ZBUF_184_0 ) ; + ccff_tail , ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -7931,7 +7921,7 @@ input [0:0] io_outpad ; input [0:0] ccff_head ; output [0:0] io_inpad ; output [0:0] ccff_tail ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , @@ -7940,7 +7930,7 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .ZBUF_211_0 ( ZBUF_211_0 ) ) ; endmodule @@ -7968,16 +7958,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_70 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_506_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_72 ) ) ; + .TE_B ( BUF_net_74 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_76 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_74 ( .A ( BUF_net_76 ) , .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -8057,13 +8048,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( net_net_69 ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__buf_8 BUFT_RR_69 ( .A ( net_net_69 ) , .X ( SOC_DIR ) ) ; + .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -8278,7 +8273,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_136 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -8287,6 +8282,20 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( ccff_head[0] ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_117 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_118 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_120 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_121 ) , + .X ( ropt_net_136 ) ) ; endmodule @@ -8435,6 +8444,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -8464,8 +8475,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -8523,9 +8532,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -8583,7 +8592,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -8642,9 +8651,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -8702,9 +8711,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_96 ) ) ; endmodule @@ -8762,9 +8771,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -8822,7 +8830,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -8940,7 +8948,7 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -8949,7 +8957,7 @@ cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -8958,7 +8966,7 @@ cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -8967,7 +8975,7 @@ cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -8976,7 +8984,7 @@ cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -8985,7 +8993,7 @@ cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -8994,7 +9002,7 @@ cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -9003,7 +9011,7 @@ cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -9012,7 +9020,7 @@ cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -9078,12 +9086,12 @@ cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_511_ } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_5_lower ) , .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , - .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; + .ZBUF_211_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , @@ -9138,10 +9146,10 @@ cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_17_lower ) , .ccff_tail ( ccff_tail ) ) ; -sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1117 ) ) ; + .X ( ctsbuf_net_1115 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -9251,15 +9259,15 @@ sky130_fd_sc_hd__buf_6 FTB_67__66 ( .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , - .HI ( optlc_net_116 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_211_inst_119 ( .A ( aps_rename_511_ ) , .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3521246 ( .A ( ctsbuf_net_1115 ) , .X ( prog_clk_0_W_out ) ) ; endmodule @@ -9327,6 +9335,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -9335,9 +9345,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_91 ) ) ; endmodule @@ -9367,9 +9374,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -9399,7 +9406,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -9411,19 +9418,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_102 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_102 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_107 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_105 ) , - .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( copt_net_102 ) , - .X ( copt_net_107 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( copt_net_99 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_102 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( mem_out[1] ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; endmodule @@ -9821,9 +9826,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; endmodule @@ -9903,9 +9908,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -9931,8 +9935,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -10007,13 +10012,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -10034,14 +10039,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_81 ) ) ; endmodule @@ -10067,7 +10071,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -10094,9 +10098,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -10122,9 +10125,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -10145,13 +10148,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -10200,13 +10203,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -10227,13 +10230,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -10719,31 +10722,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_109 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1257 ( .A ( copt_net_95 ) , + .X ( copt_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_91 ) , + .X ( copt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_93 ) , .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_96 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_100 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_98 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_99 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( copt_net_101 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( ropt_net_117 ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1275 ( .A ( copt_net_92 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1276 ( .A ( ropt_net_110 ) , + .X ( ropt_net_111 ) ) ; endmodule @@ -11043,7 +11046,7 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -11051,7 +11054,7 @@ sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -11059,7 +11062,7 @@ sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -11067,7 +11070,7 @@ sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -11093,7 +11096,7 @@ sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , @@ -11101,7 +11104,7 @@ sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -11109,7 +11112,7 @@ sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -11117,7 +11120,7 @@ sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -11141,122 +11144,122 @@ sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -11381,19 +11384,19 @@ sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -11422,14 +11425,14 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[18] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) , .X ( chany_bottom_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , - .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_87 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_88 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , + .HI ( optlc_net_90 ) ) ; endmodule @@ -11440,25 +11443,27 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_106 ; +wire copt_net_103 ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_103 ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_103 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_103 ) , .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_106 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_104 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( copt_net_105 ) , .X ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_107 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_104 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_108 ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , + .X ( copt_net_108 ) ) ; endmodule @@ -11559,7 +11564,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -11581,13 +11586,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__1__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -11613,8 +11618,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; endmodule @@ -11635,13 +11641,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__1__const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -11667,9 +11674,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) ) ; endmodule @@ -11695,9 +11702,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -11794,8 +11801,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__1__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -11804,6 +11809,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -11833,8 +11841,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -11856,8 +11865,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -11866,6 +11873,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -11895,8 +11904,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_82 ) ) ; endmodule @@ -12064,8 +12074,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -12099,9 +12110,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -12124,8 +12135,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_2__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -12137,6 +12146,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -12209,9 +12220,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -12287,6 +12298,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_2__1__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12304,9 +12317,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) ) ; endmodule @@ -12374,6 +12384,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_2__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12391,9 +12403,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_69 ) ) ; endmodule @@ -12558,9 +12567,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -12606,7 +12615,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -12633,8 +12642,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_2__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12655,6 +12662,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -12700,7 +12710,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -12747,9 +12757,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_67 ) ) ; endmodule @@ -12795,9 +12805,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_65 ) ) ; endmodule @@ -12990,8 +13000,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_2__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -13033,6 +13041,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_63 ) ) ; endmodule @@ -13116,8 +13127,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; sb_2__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -13141,6 +13150,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_61 ) ) ; endmodule @@ -13272,7 +13284,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_112 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -13281,26 +13293,6 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( ccff_head[0] ) , - .X ( copt_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_97 ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_99 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1271 ( .A ( copt_net_100 ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1272 ( .A ( ropt_net_109 ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1273 ( .A ( ropt_net_110 ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , - .X ( ropt_net_112 ) ) ; endmodule @@ -13550,7 +13542,7 @@ sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , @@ -13560,7 +13552,7 @@ sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -13578,7 +13570,7 @@ sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] , @@ -13586,7 +13578,7 @@ sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , @@ -13595,7 +13587,7 @@ sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -13621,7 +13613,7 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , @@ -13633,7 +13625,7 @@ sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -13651,7 +13643,7 @@ sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] , @@ -13659,7 +13651,7 @@ sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , @@ -13667,7 +13659,7 @@ sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -13675,7 +13667,7 @@ sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -13683,7 +13675,7 @@ sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -13691,7 +13683,7 @@ sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -13699,7 +13691,7 @@ sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , @@ -13741,7 +13733,7 @@ sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , @@ -13749,7 +13741,7 @@ sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , @@ -13757,7 +13749,7 @@ sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -13781,7 +13773,7 @@ sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -13793,28 +13785,28 @@ sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 ( .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] , chanx_left_out[13] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 ( .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , @@ -13840,31 +13832,31 @@ sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_bottom_out[15] , chany_top_out[15] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_bottom_out[17] , chany_top_out[17] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_bottom_out[18] , chany_top_out[18] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_out[19] , chany_top_out[19] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , @@ -13894,32 +13886,32 @@ sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , @@ -13949,7 +13941,7 @@ sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) ) ; @@ -14005,14 +13997,14 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , - .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , + .HI ( optlc_net_101 ) ) ; endmodule @@ -14023,19 +14015,19 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_97 ; +wire copt_net_104 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_97 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_104 ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_98 ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_102 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_104 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) ) ; endmodule @@ -14376,9 +14368,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -14399,14 +14391,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_66 ) ) ; endmodule @@ -14486,9 +14477,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -14514,9 +14505,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -14542,9 +14533,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -14565,13 +14556,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -14592,13 +14584,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -14624,9 +14616,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -14706,9 +14698,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -14756,13 +14748,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -14810,13 +14803,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; endmodule @@ -14842,8 +14836,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -14864,13 +14859,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) ) ; endmodule @@ -14891,13 +14887,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -15072,9 +15068,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_57 ) ) ; endmodule @@ -15096,8 +15092,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__0__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -15106,6 +15100,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -15127,8 +15123,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__0__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -15137,6 +15131,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -15242,9 +15238,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -15282,9 +15277,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_52 ) ) ; endmodule @@ -15308,8 +15303,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_2__0__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -15324,6 +15317,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_50 ) ) ; endmodule @@ -15361,8 +15357,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; endmodule @@ -15424,31 +15421,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_114 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_120 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( ccff_head[0] ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1251 ( .A ( copt_net_89 ) , - .X ( copt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_90 ) , - .X ( copt_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_88 ) , - .X ( copt_net_92 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( ropt_net_116 ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( copt_net_91 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_99 ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_98 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_97 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1282 ( .A ( copt_net_95 ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1283 ( .A ( ropt_net_121 ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1284 ( .A ( ropt_net_119 ) , + .X ( ropt_net_121 ) ) ; endmodule @@ -15490,9 +15487,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; endmodule @@ -15534,9 +15531,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -15561,8 +15557,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_2__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -15580,6 +15574,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_43 ) ) ; endmodule @@ -15663,7 +15660,7 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input prog_clk_0_N_in ; -wire ropt_net_104 ; +wire ropt_net_110 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -15743,7 +15740,7 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -15751,7 +15748,7 @@ sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -15759,7 +15756,7 @@ sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -15767,7 +15764,7 @@ sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -15793,7 +15790,7 @@ sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -15801,7 +15798,7 @@ sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -15809,7 +15806,7 @@ sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -15817,7 +15814,7 @@ sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -15842,25 +15839,25 @@ sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 ( chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -15885,112 +15882,112 @@ sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -16102,28 +16099,30 @@ sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[3] ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) ) ; sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[5] ) , +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_left_in[5] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , - .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , - .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_85 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_86 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[17] ) ) ; endmodule @@ -16134,27 +16133,20 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -wire copt_net_105 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_105 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_104 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_105 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_103 ) , - .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_101 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_100 ) , - .X ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_109 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( mem_out[2] ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1295 ( .A ( copt_net_108 ) , + .X ( copt_net_109 ) ) ; endmodule @@ -16179,8 +16171,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_1__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -16198,6 +16188,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -16359,7 +16351,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -16382,6 +16374,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__2__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -16390,9 +16384,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_80 ) ) ; endmodule @@ -16422,9 +16413,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -16446,8 +16437,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -16456,6 +16445,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -16626,8 +16618,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_1__2__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -16639,6 +16629,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -16728,9 +16720,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -16912,9 +16903,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -16940,8 +16931,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -16962,6 +16951,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) ) ; endmodule @@ -17007,7 +16999,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -17101,9 +17093,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -17129,8 +17120,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -17151,6 +17140,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -17196,8 +17188,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -17332,9 +17325,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_71 ) ) ; endmodule @@ -17497,9 +17490,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -17532,8 +17525,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -17575,6 +17566,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -17685,9 +17678,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -17741,9 +17734,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -17771,8 +17764,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; sb_1__2__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -17799,6 +17790,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -17809,7 +17803,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_99 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_130 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -17818,18 +17812,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_96 ) , - .X ( copt_net_94 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_97 ) , - .X ( copt_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_94 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( ccff_head[0] ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_100 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_104 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_105 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_131 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1317 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) ) ; endmodule @@ -17946,7 +17946,8 @@ input SC_IN_BOT ; output SC_OUT_BOT ; input prog_clk_0_S_in ; -wire ropt_net_115 ; +wire ropt_net_118 ; +wire ropt_net_119 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -18016,7 +18017,7 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -18029,7 +18030,7 @@ sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , @@ -18038,7 +18039,7 @@ sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -18047,7 +18048,7 @@ sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -18073,7 +18074,7 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -18084,7 +18085,7 @@ sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , @@ -18103,7 +18104,7 @@ sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , @@ -18111,7 +18112,7 @@ sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -18128,7 +18129,7 @@ sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -18136,7 +18137,7 @@ sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -18144,7 +18145,7 @@ sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -18152,7 +18153,7 @@ sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -18160,7 +18161,7 @@ sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -18168,7 +18169,7 @@ sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , @@ -18176,7 +18177,7 @@ sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , @@ -18184,7 +18185,7 @@ sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -18231,7 +18232,7 @@ sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -18243,21 +18244,21 @@ sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 ( .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] , chanx_right_out[10] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_99 ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 ( .in ( { chanx_left_out[19] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , @@ -18278,37 +18279,37 @@ sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( chanx_right_out[11] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -18343,7 +18344,7 @@ sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , @@ -18356,18 +18357,17 @@ sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_118 ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) , @@ -18378,7 +18378,7 @@ sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[7] ) , +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) , .X ( chanx_left_out[9] ) ) ; @@ -18428,22 +18428,22 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_88 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_89 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1314 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_115 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_118 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_119 ) , .X ( SC_OUT_BOT ) ) ; endmodule @@ -18455,16 +18455,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; +wire copt_net_120 ; + sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_119 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( mem_out[2] ) , - .X ( copt_net_119 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_120 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_120 ) , + .X ( mem_out[2] ) ) ; endmodule @@ -18635,8 +18636,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__1__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -18657,6 +18656,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -18702,8 +18704,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -18960,8 +18963,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -18991,6 +18992,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -19048,7 +19051,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -19107,9 +19110,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_94 ) ) ; endmodule @@ -19344,9 +19347,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_92 ) ) ; endmodule @@ -19404,9 +19407,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_90 ) ) ; endmodule @@ -19435,6 +19438,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -19464,9 +19469,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) ) ; endmodule @@ -19495,6 +19497,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -19524,8 +19528,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -19554,6 +19556,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -19583,8 +19587,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -19642,9 +19644,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) ) ; endmodule @@ -20059,9 +20061,9 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , - .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -20205,7 +20207,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_124 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_125 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -20214,26 +20216,26 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_113 ) , - .X ( copt_net_108 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_108 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_114 ) , .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_109 ) , .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_110 ) , .X ( copt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_111 ) , .X ( copt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_112 ) , .X ( copt_net_113 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_122 ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1302 ( .A ( copt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( copt_net_113 ) , .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1303 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_122 ) , .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1304 ( .A ( ropt_net_123 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1311 ( .A ( ropt_net_123 ) , .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1312 ( .A ( ropt_net_124 ) , + .X ( ropt_net_125 ) ) ; endmodule @@ -20366,9 +20368,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -20399,8 +20400,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -20436,6 +20435,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -20501,7 +20502,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -20600,6 +20601,74 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_81 ) ) ; +endmodule + + +module sb_1__1__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -20640,74 +20709,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_82 ) ) ; -endmodule - - module sb_1__1__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule @@ -20735,6 +20736,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -20770,8 +20773,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -20991,7 +20992,7 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -21011,7 +21012,7 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -21021,7 +21022,7 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] , chanx_left_out[13] , chanx_right_in[15] , @@ -21031,7 +21032,7 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] , chanx_right_in[11] , chanx_left_out[14] , @@ -21051,7 +21052,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] , chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , @@ -21061,7 +21062,7 @@ sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -21126,7 +21127,7 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] , @@ -21152,7 +21153,7 @@ sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , @@ -21190,7 +21191,7 @@ sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] , @@ -21199,7 +21200,7 @@ sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , @@ -21217,7 +21218,7 @@ sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , @@ -21226,7 +21227,7 @@ sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_107 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] , chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] , @@ -21253,7 +21254,7 @@ sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 ( .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] , chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] , @@ -21271,7 +21272,7 @@ sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] , chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] , @@ -21280,7 +21281,7 @@ sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -21348,7 +21349,7 @@ sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , @@ -21356,7 +21357,7 @@ sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , @@ -21372,7 +21373,7 @@ sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , @@ -21392,8 +21393,8 @@ sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , - .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , + .HI ( optlc_net_102 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) , @@ -21500,18 +21501,20 @@ sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , .HI ( optlc_net_103 ) ) ; sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) , .HI ( optlc_net_104 ) ) ; sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) , .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_108 ) ) ; endmodule @@ -21600,20 +21603,20 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -wire copt_net_107 ; +wire copt_net_106 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_107 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) ) ; sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_106 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_107 ) , - .X ( copt_net_106 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1288 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_106 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_109 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1290 ( .A ( copt_net_110 ) , .X ( mem_out[2] ) ) ; endmodule @@ -21656,8 +21659,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_1__0__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21675,6 +21676,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -21716,9 +21719,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -21905,9 +21908,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -21999,8 +22001,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -22096,8 +22099,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; endmodule @@ -22232,9 +22236,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -22288,6 +22292,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -22296,9 +22302,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_76 ) ) ; endmodule @@ -22328,9 +22331,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -22360,9 +22363,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -22392,9 +22395,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -22424,8 +22427,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -22517,6 +22521,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_1__0__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -22528,8 +22534,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -22788,9 +22792,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -22816,8 +22820,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__0__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -22838,6 +22840,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -22863,8 +22868,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -22885,6 +22888,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -23055,24 +23060,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_99 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_102 ) , .X ( copt_net_100 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_100 ) , .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_105 ) , .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( ccff_head[0] ) , .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_101 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( copt_net_104 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_131 ) , .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_132 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_132 ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( copt_net_103 ) , - .X ( ropt_net_134 ) ) ; endmodule @@ -23224,9 +23229,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -23342,6 +23346,7 @@ output prog_clk_3_N_out ; input clk_3_S_in ; output clk_3_N_out ; +wire ropt_net_119 ; wire ropt_net_118 ; wire [0:0] prog_clk ; wire prog_clk_0 ; @@ -23411,7 +23416,7 @@ sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , @@ -23420,7 +23425,7 @@ sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ; sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] , chanx_left_out[14] , left_bottom_grid_pin_3_[0] , @@ -23429,7 +23434,7 @@ sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] , @@ -23437,7 +23442,7 @@ sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -23463,7 +23468,7 @@ sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -23471,7 +23476,7 @@ sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -23479,7 +23484,7 @@ sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , SYNOPSYS_UNCONNECTED_25 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , @@ -23487,7 +23492,7 @@ sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] , @@ -23503,7 +23508,7 @@ sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] , @@ -23511,7 +23516,7 @@ sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -23553,14 +23558,14 @@ sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 ( .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] , chanx_right_out[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , @@ -23575,43 +23580,43 @@ sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( chanx_right_out[11] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -23650,7 +23655,7 @@ sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[19] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -23672,7 +23677,7 @@ sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -23705,7 +23710,7 @@ sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , @@ -23723,7 +23728,7 @@ sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_left_out[11] , left_bottom_grid_pin_7_[0] , @@ -23731,7 +23736,7 @@ sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , @@ -23749,14 +23754,14 @@ sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_95 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , @@ -23801,8 +23806,8 @@ sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[7] ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_119 ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) , @@ -23817,8 +23822,8 @@ sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) , .X ( chanx_right_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) , @@ -23827,26 +23832,28 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( Test_en_S_in ) , .Y ( BUF_net_86 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( Test_en_S_in ) , .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( prog_clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_88 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_118 ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[17] ) ) ; endmodule @@ -23857,23 +23864,21 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_79 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_79 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_79 ) , - .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_75 ) , - .X ( copt_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1240 ( .A ( copt_net_76 ) , - .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1241 ( .A ( copt_net_77 ) , - .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1242 ( .A ( copt_net_78 ) , - .X ( mem_out[1] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( copt_net_71 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( mem_out[1] ) , + .X ( copt_net_70 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_74 ) , + .X ( copt_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1237 ( .A ( copt_net_70 ) , + .X ( copt_net_72 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_72 ) , + .X ( copt_net_73 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_73 ) , + .X ( copt_net_74 ) ) ; endmodule @@ -24154,7 +24159,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -24208,7 +24213,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -24235,7 +24240,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -24289,7 +24294,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -24343,9 +24348,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_51 ) ) ; endmodule @@ -24371,9 +24376,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_58 ( .A ( BUF_net_49 ) , .Y ( out[0] ) ) ; endmodule @@ -24394,13 +24399,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -24421,13 +24426,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -24475,14 +24480,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) ) ; endmodule @@ -24562,9 +24566,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -24585,13 +24588,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -24678,9 +24681,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_45 ) ) ; endmodule @@ -24702,6 +24705,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_0__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -24710,9 +24715,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_46 ) ) ; endmodule @@ -24784,9 +24786,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_43 ) ) ; endmodule @@ -24810,6 +24812,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_0__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -24824,8 +24828,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -24853,29 +24855,29 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_131 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_118 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_69 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( ccff_head[0] ) , + .X ( copt_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_63 ) , + .X ( copt_net_64 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1230 ( .A ( copt_net_64 ) , + .X ( copt_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_68 ) , + .X ( copt_net_66 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_65 ) , + .X ( copt_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_67 ) , .X ( copt_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_71 ) , - .X ( copt_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_73 ) , - .X ( copt_net_70 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_70 ) , - .X ( copt_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( ccff_head[0] ) , - .X ( copt_net_72 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_72 ) , - .X ( copt_net_73 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1292 ( .A ( ropt_net_132 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1293 ( .A ( copt_net_68 ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1281 ( .A ( copt_net_66 ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1282 ( .A ( ropt_net_117 ) , + .X ( ropt_net_118 ) ) ; endmodule @@ -24992,8 +24994,8 @@ input SC_IN_TOP ; output SC_OUT_BOT ; input prog_clk_0_E_in ; -wire ropt_net_95 ; -wire ropt_net_96 ; +wire ropt_net_88 ; +wire ropt_net_87 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -25053,7 +25055,7 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , @@ -25061,7 +25063,7 @@ sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -25078,7 +25080,7 @@ sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -25086,7 +25088,7 @@ sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -25102,13 +25104,13 @@ sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 ( chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -25123,92 +25125,92 @@ sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -25308,20 +25310,20 @@ sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chanx_right_in[4] ) , .X ( chany_bottom_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) , .X ( chany_bottom_out[13] ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[8] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) ) ; sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_96 ) ) ; + .X ( ropt_net_88 ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) , @@ -25330,18 +25332,18 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) , .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_87 ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_65 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , - .HI ( optlc_net_66 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , - .HI ( optlc_net_67 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1257 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_96 ) , +sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , + .HI ( optlc_net_60 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , + .HI ( optlc_net_61 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , + .HI ( optlc_net_62 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1252 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1253 ( .A ( ropt_net_88 ) , .X ( chany_bottom_out[7] ) ) ; endmodule @@ -25485,9 +25487,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; endmodule @@ -25508,13 +25510,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__1__const1_30 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -25540,9 +25542,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_107 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -25568,9 +25570,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -25596,9 +25598,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_91 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -25609,25 +25611,24 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_125 ; - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_125 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_125 ) , - .X ( copt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_120 ) , - .X ( copt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_121 ) , - .X ( copt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_122 ) , - .X ( copt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_123 ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( copt_net_129 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( mem_out[1] ) , .X ( copt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_124 ) , - .X ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( copt_net_124 ) , + .X ( copt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_125 ) , + .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_126 ) , + .X ( copt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_127 ) , + .X ( copt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_128 ) , + .X ( copt_net_129 ) ) ; endmodule @@ -25717,9 +25718,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -25749,8 +25750,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -25772,6 +25774,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_0__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -25780,8 +25784,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -25811,9 +25813,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -25941,9 +25943,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_81 ) ) ; endmodule @@ -25989,9 +25991,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) ) ; endmodule @@ -26017,6 +26019,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_0__1__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -26037,8 +26041,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -26191,9 +26193,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_77 ) ) ; endmodule @@ -26227,9 +26229,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_106 ) ) ; endmodule @@ -26298,9 +26300,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -26334,9 +26336,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_71 ) ) ; endmodule @@ -26359,8 +26361,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -26372,6 +26372,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -26405,7 +26408,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -26529,9 +26532,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -26633,6 +26636,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_0__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -26647,9 +26652,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_67 ) ) ; endmodule @@ -26687,9 +26689,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -26802,31 +26803,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_129 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_133 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_115 ) , - .X ( copt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_114 ) , - .X ( copt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_119 ) , - .X ( copt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_116 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_120 ) , .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_118 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_121 ) , .X ( copt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1289 ( .A ( copt_net_117 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1290 ( .A ( ropt_net_127 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1291 ( .A ( ropt_net_128 ) , - .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_123 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( ccff_head[0] ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1299 ( .A ( copt_net_118 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( ropt_net_131 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) ) ; endmodule @@ -26980,8 +26981,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -26999,6 +26998,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -27040,8 +27041,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -27083,9 +27085,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -27110,6 +27111,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -27127,8 +27130,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -27235,21 +27236,21 @@ sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , @@ -27257,28 +27258,28 @@ sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -27319,35 +27320,35 @@ sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_top_out[9] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -27379,49 +27380,49 @@ sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_top_out[11] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_bottom_out[9] , right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 ( .in ( { chany_bottom_out[13] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 ( .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] , chany_top_out[19] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -27465,7 +27466,7 @@ sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[6] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -27474,7 +27475,7 @@ sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -27483,7 +27484,7 @@ sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , @@ -27504,29 +27505,29 @@ sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 ( chany_top_out[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 ( .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 ( .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 ( .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -27555,32 +27556,32 @@ sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , @@ -27667,14 +27668,16 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_93 ) , + .HI ( optlc_net_117 ) ) ; endmodule @@ -27734,9 +27737,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -27864,8 +27867,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_0__0__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -27880,6 +27881,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -27998,9 +28002,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -28011,14 +28015,14 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; +wire copt_net_92 ; + sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_91 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1251 ( .A ( mem_out[1] ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_87 ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_92 ) , .X ( copt_net_88 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_88 ) , .X ( copt_net_89 ) ) ; @@ -28026,6 +28030,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_89 ) , .X ( copt_net_90 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_90 ) , .X ( copt_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1256 ( .A ( copt_net_91 ) , + .X ( mem_out[1] ) ) ; endmodule @@ -28276,27 +28282,27 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_137 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1244 ( .A ( ccff_head[0] ) , - .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( copt_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( ccff_head[0] ) , .X ( copt_net_81 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1246 ( .A ( copt_net_85 ) , .X ( copt_net_82 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1247 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1249 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( copt_net_84 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1280 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( copt_net_82 ) , + .X ( copt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( copt_net_84 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1301 ( .A ( ropt_net_136 ) , + .X ( ropt_net_137 ) ) ; endmodule @@ -28317,14 +28323,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_69 ) ) ; endmodule @@ -28350,9 +28355,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -28378,9 +28383,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -28406,9 +28411,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -28434,9 +28439,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -28462,9 +28467,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) ) ; endmodule @@ -28517,9 +28522,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_58 ) ) ; endmodule @@ -28545,9 +28550,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_55 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_56 ) ) ; endmodule @@ -28573,9 +28578,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_53 ( .A ( BUF_net_54 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_54 ) ) ; endmodule @@ -28601,9 +28606,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_52 ) ) ; endmodule @@ -28629,9 +28634,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_48 ( .A ( BUF_net_49 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_50 ) ) ; endmodule @@ -28657,9 +28662,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_47 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_48 ) ) ; endmodule @@ -28685,9 +28690,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_45 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_46 ) ) ; endmodule @@ -28740,7 +28745,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -28767,8 +28772,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; endmodule @@ -28825,6 +28831,7 @@ output [0:19] chanx_right_out ; output [0:0] ccff_tail ; input prog_clk_0_E_in ; +wire ropt_net_107 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -28881,92 +28888,92 @@ sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -29062,7 +29069,7 @@ sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , @@ -29070,7 +29077,7 @@ sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , @@ -29088,7 +29095,7 @@ sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , @@ -29096,7 +29103,7 @@ sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -29112,13 +29119,13 @@ sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 ( right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -29145,8 +29152,8 @@ sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) , .X ( chany_top_out[7] ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) , .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_107 ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) , @@ -29163,14 +29170,16 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , +sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , .HI ( optlc_net_79 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , + .HI ( optlc_net_80 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[9] ) ) ; endmodule @@ -29183,21 +29192,21 @@ output [0:1] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( copt_net_165 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1947 ( .A ( copt_net_162 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1943 ( .A ( mem_out[1] ) , .X ( copt_net_160 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1948 ( .A ( copt_net_160 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1944 ( .A ( copt_net_160 ) , .X ( copt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1949 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1945 ( .A ( copt_net_161 ) , .X ( copt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1950 ( .A ( copt_net_161 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1946 ( .A ( copt_net_162 ) , .X ( copt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1951 ( .A ( copt_net_163 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1947 ( .A ( copt_net_163 ) , .X ( copt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1952 ( .A ( copt_net_164 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1948 ( .A ( copt_net_164 ) , .X ( copt_net_165 ) ) ; endmodule @@ -29209,7 +29218,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -29226,7 +29235,7 @@ output [0:1] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29315,8 +29324,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( p_abuf0 ) , .Y ( BUF_net_121 ) ) ; +sky130_fd_sc_hd__buf_1 BUFT_RR_119 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; endmodule @@ -29342,8 +29350,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( p_abuf0 ) , .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( p_abuf0 ) , .Y ( BUF_net_118 ) ) ; endmodule @@ -29359,10 +29367,10 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , .Q ( net_net_73 ) ) ; sky130_fd_sc_hd__buf_8 BUFT_RR_73 ( .A ( copt_net_168 ) , .X ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1955 ( .A ( copt_net_169 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1950 ( .A ( net_net_73 ) , + .X ( copt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1951 ( .A ( copt_net_167 ) , .X ( copt_net_168 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1956 ( .A ( net_net_73 ) , - .X ( copt_net_169 ) ) ; endmodule @@ -29730,10 +29738,10 @@ grid_clb_mux_tree_size2_mem_31 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , grid_clb_mux_tree_size2_mem mem_ff_1_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; -sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( ropt_net_170 ) , .X ( fabric_reg_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1959 ( .A ( fabric_sc_out[0] ) , - .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1954 ( .A ( fabric_sc_out[0] ) , + .X ( ropt_net_170 ) ) ; endmodule @@ -29830,12 +29838,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -29843,7 +29851,7 @@ grid_clb_const1_38 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -29853,12 +29861,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -29866,7 +29874,7 @@ grid_clb_const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -29894,10 +29902,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_117 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_116 ) ) ; endmodule @@ -29924,10 +29932,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_113 ) ) ; endmodule @@ -29979,12 +29987,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -29992,7 +30000,7 @@ grid_clb_const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -30181,13 +30189,13 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -30210,7 +30218,7 @@ grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; @@ -30220,7 +30228,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -30235,7 +30243,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -30255,7 +30262,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -30286,7 +30293,7 @@ grid_clb_mux_tree_size2_27 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_38 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -30294,7 +30301,7 @@ grid_clb_mux_tree_size2_38 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_25 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -30317,7 +30324,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; + fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -30332,7 +30339,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , @@ -30340,7 +30346,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; endmodule @@ -30409,12 +30415,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -30422,7 +30428,7 @@ grid_clb_const1_37 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -30432,12 +30438,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -30445,7 +30451,7 @@ grid_clb_const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -30456,13 +30462,13 @@ endmodule module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -30470,13 +30476,13 @@ grid_clb_const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_515_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -30486,13 +30492,13 @@ endmodule module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -30500,13 +30506,13 @@ grid_clb_const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_514_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -30558,12 +30564,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -30571,7 +30577,7 @@ grid_clb_const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -30760,13 +30766,13 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -30789,7 +30795,7 @@ grid_clb_mux_tree_size2_20 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_20 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; @@ -30799,7 +30805,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -30813,7 +30819,7 @@ output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -30833,7 +30839,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -30850,21 +30856,21 @@ grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_37 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -30872,7 +30878,7 @@ grid_clb_mux_tree_size2_37 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -30895,7 +30901,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p3 ) ; + fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -30909,7 +30915,7 @@ output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p3 ; +input p0 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , @@ -30917,7 +30923,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; endmodule @@ -31033,13 +31039,13 @@ endmodule module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -31047,13 +31053,13 @@ grid_clb_const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_513_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_105 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_104 ) ) ; endmodule @@ -31063,13 +31069,13 @@ endmodule module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -31077,13 +31083,13 @@ grid_clb_const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_512_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -31376,7 +31382,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p2 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -31391,7 +31397,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p2 ; -input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -31428,14 +31433,14 @@ grid_clb_mux_tree_size2_17 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_18 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_19 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -31473,7 +31478,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p2 , p3 ) ; + fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -31488,7 +31493,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p2 ; -input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , @@ -31496,7 +31500,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; endmodule @@ -31588,12 +31592,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -31601,7 +31605,7 @@ grid_clb_const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -31629,10 +31633,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_511_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -31642,13 +31646,13 @@ endmodule module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , p_abuf0 , - p2 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -31656,13 +31660,13 @@ grid_clb_const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_95 ) ) ; endmodule @@ -31714,12 +31718,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -31727,7 +31731,7 @@ grid_clb_const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -31916,13 +31920,13 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -31945,7 +31949,7 @@ grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_12 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; @@ -31955,7 +31959,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -31969,6 +31973,7 @@ output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -31989,7 +31994,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -32006,7 +32011,7 @@ grid_clb_mux_tree_size2_13 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_14 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -32020,7 +32025,7 @@ grid_clb_mux_tree_size2_15 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -32051,7 +32056,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; + fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -32065,6 +32070,7 @@ output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -32073,7 +32079,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; endmodule @@ -32142,12 +32148,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -32155,7 +32161,7 @@ grid_clb_const1_34 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -32206,10 +32212,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_509_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_92 ) ) ; endmodule @@ -32235,10 +32241,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -32290,12 +32296,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -32303,7 +32309,7 @@ grid_clb_const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -32492,13 +32498,13 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -32521,7 +32527,7 @@ grid_clb_mux_tree_size2_8 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_8 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; @@ -32531,7 +32537,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -32546,7 +32552,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -32566,7 +32571,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -32605,7 +32610,7 @@ grid_clb_mux_tree_size2_34 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ; + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -32628,7 +32633,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ; + fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -32643,7 +32648,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , @@ -32651,7 +32655,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; endmodule @@ -32720,12 +32724,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_33 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_33 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -32733,7 +32737,7 @@ grid_clb_const1_33 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -32781,9 +32785,12 @@ grid_clb_const1_6 const1_0_ ( sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( p_abuf0 ) , .Y ( BUF_net_87 ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -32807,9 +32814,9 @@ grid_clb_const1_5 const1_0_ ( sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( out[0] ) , .Y ( BUF_net_85 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( p_abuf0 ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf0 ) , .Y ( BUF_net_83 ) ) ; endmodule @@ -33176,7 +33183,7 @@ grid_clb_mux_tree_size2_33 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_3_out ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_5 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -33352,12 +33359,9 @@ grid_clb_const1_2 const1_0_ ( sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_82 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_82 ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( out[0] ) , .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( p_abuf0 ) ) ; endmodule @@ -33381,9 +33385,12 @@ grid_clb_const1_1 const1_0_ ( sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( p_abuf0 ) , .Y ( BUF_net_77 ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_78 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -33460,7 +33467,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_167 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_159 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -33495,18 +33502,18 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1942 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1937 ( .A ( copt_net_156 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1938 ( .A ( copt_net_158 ) , .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1943 ( .A ( copt_net_155 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1939 ( .A ( copt_net_157 ) , .X ( copt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1944 ( .A ( copt_net_159 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1940 ( .A ( copt_net_155 ) , .X ( copt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1945 ( .A ( copt_net_157 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1941 ( .A ( ccff_head[0] ) , .X ( copt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1946 ( .A ( copt_net_156 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1942 ( .A ( copt_net_154 ) , .X ( copt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1954 ( .A ( copt_net_158 ) , - .X ( copt_net_167 ) ) ; endmodule @@ -33817,7 +33824,7 @@ module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clb_I0 , clb_reg_out , clb_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p0 , - p1 , p2 , p3 , p4 ) ; + p1 , p2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:2] clb_I0 ; @@ -33864,7 +33871,6 @@ input p0 ; input p1 ; input p2 ; input p3 ; -input p4 ; wire [0:0] direct_interc_29_out ; wire [0:0] direct_interc_36_out ; @@ -33921,7 +33927,7 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_reg_out ( direct_interc_43_out ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p_abuf0 ( p_abuf4 ) , .p_abuf1 ( p_abuf5 ) , .p0 ( p0 ) , .p2 ( p3 ) ) ; + .p_abuf0 ( p_abuf4 ) , .p_abuf1 ( p_abuf5 ) , .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3[2] , clb_I3i[0] } ) , @@ -33933,7 +33939,7 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .fle_reg_out ( direct_interc_50_out ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p_abuf0 ( p_abuf6 ) , .p_abuf1 ( p_abuf7 ) , .p2 ( p3 ) ) ; + .p_abuf0 ( p_abuf6 ) , .p_abuf1 ( p_abuf7 ) , .p0 ( p0 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4[2] , clb_I4i[0] } ) , @@ -33945,7 +33951,7 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_reg_out ( direct_interc_57_out ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf8 ) , .p_abuf1 ( p_abuf9 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf8 ) , .p_abuf1 ( p_abuf9 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5[2] , clb_I5i[0] } ) , @@ -33957,7 +33963,7 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_reg_out ( direct_interc_64_out ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p_abuf0 ( p_abuf10 ) , .p_abuf1 ( p_abuf11 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf10 ) , .p_abuf1 ( p_abuf11 ) , .p0 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6[2] , clb_I6i[0] } ) , @@ -33969,7 +33975,7 @@ grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle .fle_reg_out ( direct_interc_71_out ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p_abuf0 ( p_abuf12 ) , .p_abuf1 ( p_abuf13 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf12 ) , .p_abuf1 ( p_abuf13 ) , .p0 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7[2] , clb_I7i[0] } ) , @@ -34118,8 +34124,9 @@ output prog_clk_0_N_out ; input clk_0_N_in ; input clk_0_S_in ; -wire p_abuf0 ; -wire p_abuf3 ; +wire p_abuf2 ; +wire p_abuf8 ; +wire p_abuf12 ; wire prog_clk_0 ; wire [0:0] prog_clk ; wire [0:0] clk ; @@ -34167,56 +34174,58 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_reg_in ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_520_ , top_width_0_height_0__pin_35_lower[0] , - top_width_0_height_0__pin_36_lower[0] , aps_rename_523_ , - aps_rename_524_ , aps_rename_525_ , aps_rename_526_ , - aps_rename_527_ , aps_rename_528_ , aps_rename_529_ , + .clb_O ( { aps_rename_520_ , aps_rename_521_ , aps_rename_522_ , + top_width_0_height_0__pin_37_lower[0] , aps_rename_524_ , + aps_rename_525_ , aps_rename_526_ , aps_rename_527_ , + aps_rename_528_ , right_width_0_height_0__pin_43_lower[0] , aps_rename_530_ , aps_rename_531_ , aps_rename_532_ , - aps_rename_533_ , aps_rename_534_ , aps_rename_535_ } ) , + right_width_0_height_0__pin_47_lower[0] , aps_rename_534_ , + aps_rename_535_ } ) , .clb_reg_out ( bottom_width_0_height_0__pin_50_ ) , .clb_sc_out ( { SC_OUT_BOT } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , + .ccff_tail ( ccff_tail ) , + .p_abuf0 ( top_width_0_height_0__pin_35_lower[0] ) , .p_abuf1 ( top_width_0_height_0__pin_34_lower[0] ) , - .p_abuf2 ( top_width_0_height_0__pin_37_lower[0] ) , - .p_abuf3 ( p_abuf3 ) , + .p_abuf2 ( p_abuf2 ) , + .p_abuf3 ( top_width_0_height_0__pin_36_lower[0] ) , .p_abuf4 ( top_width_0_height_0__pin_39_lower[0] ) , .p_abuf5 ( top_width_0_height_0__pin_38_lower[0] ) , .p_abuf6 ( top_width_0_height_0__pin_41_lower[0] ) , .p_abuf7 ( top_width_0_height_0__pin_40_lower[0] ) , - .p_abuf8 ( right_width_0_height_0__pin_43_lower[0] ) , + .p_abuf8 ( p_abuf8 ) , .p_abuf9 ( right_width_0_height_0__pin_42_lower[0] ) , .p_abuf10 ( right_width_0_height_0__pin_45_lower[0] ) , .p_abuf11 ( right_width_0_height_0__pin_44_lower[0] ) , - .p_abuf12 ( right_width_0_height_0__pin_47_lower[0] ) , + .p_abuf12 ( p_abuf12 ) , .p_abuf13 ( right_width_0_height_0__pin_46_lower[0] ) , .p_abuf14 ( right_width_0_height_0__pin_49_lower[0] ) , .p_abuf15 ( right_width_0_height_0__pin_48_lower[0] ) , .p0 ( optlc_net_146 ) , .p1 ( optlc_net_147 ) , .p2 ( optlc_net_148 ) , - .p3 ( optlc_net_149 ) , .p4 ( optlc_net_150 ) ) ; + .p3 ( optlc_net_149 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) ) ; -sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , - .X ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , .X ( aps_rename_536_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( Test_en_E_out ) ) ; sky130_fd_sc_hd__buf_12 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1151 ) ) ; + .X ( ctsbuf_net_1150 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2152 ) ) ; + .X ( ctsbuf_net_2151 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3153 ) ) ; + .X ( ctsbuf_net_3152 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4154 ) ) ; + .X ( ctsbuf_net_4153 ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( aps_rename_520_ ) , .X ( top_width_0_height_0__pin_34_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( p_abuf0 ) , +sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( aps_rename_521_ ) , .X ( top_width_0_height_0__pin_35_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( p_abuf3 ) , +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( aps_rename_522_ ) , .X ( top_width_0_height_0__pin_36_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( aps_rename_523_ ) , +sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( p_abuf2 ) , .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( aps_rename_524_ ) , .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; @@ -34228,7 +34237,7 @@ sky130_fd_sc_hd__buf_6 FTB_64__63 ( .A ( aps_rename_527_ ) , .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_528_ ) , .X ( right_width_0_height_0__pin_42_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_529_ ) , +sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( p_abuf8 ) , .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_530_ ) , .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; @@ -34236,13 +34245,17 @@ sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_531_ ) , .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_532_ ) , .X ( right_width_0_height_0__pin_46_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_533_ ) , +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( p_abuf12 ) , .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_534_ ) , .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_535_ ) , .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( SC_OUT_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , + .Y ( Test_en_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( aps_rename_536_ ) , + .Y ( BUF_net_121 ) ) ; sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_146 ) ) ; sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , @@ -34251,17 +34264,13 @@ sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_148 ) ) ; sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_150 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_133 ( .A ( aps_rename_536_ ) , - .X ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3901298 ( .A ( ctsbuf_net_1151 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3901295 ( .A ( ctsbuf_net_1150 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3951303 ( .A ( ctsbuf_net_2152 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3951300 ( .A ( ctsbuf_net_2151 ) , .X ( prog_clk_0_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4001308 ( .A ( ctsbuf_net_3153 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4001305 ( .A ( ctsbuf_net_3152 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4051313 ( .A ( ctsbuf_net_4154 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4051310 ( .A ( ctsbuf_net_4153 ) , .X ( prog_clk_0_N_out ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz b/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz index 4c4b5a2..c5fa910 100644 Binary files a/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz and b/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v index b92523d..56f837d 100644 --- a/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v @@ -13,15 +13,23 @@ output [0:0] mem_out ; input VDD ; input VSS ; +wire copt_net_88 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( copt_net_90 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( mem_out[0] ) , - .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_88 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_89 ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_88 ) , + .X ( copt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_86 ) , + .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_87 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1311 ( .A ( mem_out[0] ) , + .X ( copt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40,19 +48,21 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , - .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_59 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( SOC_DIR ) , + .TE_B ( BUF_net_59 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_59 ( .A ( BUF_net_61 ) , .Y ( BUF_net_59 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_61 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -134,11 +144,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -157,11 +167,11 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -184,7 +194,7 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -234,11 +244,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -257,13 +267,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -284,11 +294,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -307,13 +317,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -503,59 +513,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -589,6 +546,59 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; @@ -764,11 +774,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -787,13 +797,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -837,13 +847,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -864,11 +874,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -893,7 +903,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -912,13 +922,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -937,13 +947,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -962,32 +972,34 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_92 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_86 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ropt_net_94 ) , + .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( ccff_head[0] ) , .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1305 ( .A ( copt_net_85 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1308 ( .A ( ccff_head[0] ) , - .X ( copt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1309 ( .A ( copt_net_82 ) , - .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_83 ) , - .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1311 ( .A ( copt_net_88 ) , - .X ( copt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( copt_net_84 ) , + .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_82 ) , + .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_93 ) , + .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1076,6 +1088,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1110,10 +1125,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1174,10 +1185,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1301,10 +1312,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1365,7 +1376,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1456,9 +1467,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1493,6 +1501,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1656,7 +1666,7 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1666,7 +1676,7 @@ cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1676,7 +1686,7 @@ cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1686,7 +1696,7 @@ cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -1696,7 +1706,7 @@ cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1706,7 +1716,7 @@ cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1716,7 +1726,7 @@ cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1726,7 +1736,7 @@ cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1736,7 +1746,7 @@ cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1789,7 +1799,7 @@ cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1798,7 +1808,7 @@ cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1807,7 +1817,7 @@ cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1816,7 +1826,7 @@ cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1825,7 +1835,7 @@ cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1834,7 +1844,7 @@ cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1843,7 +1853,7 @@ cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1852,7 +1862,7 @@ cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -1900,15 +1910,14 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( { ropt_net_91 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_278 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , @@ -1993,22 +2002,18 @@ sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( left_width_0_height_0__pin_1_lower[0] ) , .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3471203 ( .A ( ctsbuf_net_177 ) , .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521208 ( .A ( ctsbuf_net_278 ) , .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2024,13 +2029,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2053,9 +2058,9 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2099,13 +2104,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2124,11 +2129,11 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2149,7 +2154,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2174,7 +2179,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2203,7 +2208,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2233,59 +2238,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2319,6 +2271,59 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; @@ -2421,8 +2426,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2447,9 +2454,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2477,6 +2481,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2609,9 +2615,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2639,6 +2642,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2651,19 +2656,33 @@ output [0:3] mem_out ; input VDD ; input VSS ; +wire copt_net_84 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_84 ) , + .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1316 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1317 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_81 ) , + .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_82 ) , + .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_83 ) , + .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2679,7 +2698,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2706,7 +2725,7 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2729,13 +2748,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2754,13 +2773,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2779,11 +2798,11 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2804,13 +2823,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2829,36 +2848,26 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_100 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_91 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( ccff_head[0] ) , - .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1314 ( .A ( copt_net_82 ) , - .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_83 ) , - .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1324 ( .A ( copt_net_85 ) , - .X ( copt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1334 ( .A ( ropt_net_97 ) , - .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1335 ( .A ( ropt_net_98 ) , - .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1336 ( .A ( copt_net_86 ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1339 ( .A ( ropt_net_96 ) , - .X ( ropt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( ropt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_92 ) , + .X ( ropt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_88 ) , + .X ( ropt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1362 ( .A ( ropt_net_89 ) , + .X ( ropt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1363 ( .A ( ropt_net_90 ) , + .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2885,6 +2894,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2919,10 +2931,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3171,8 +3179,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3359,8 +3369,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3480,7 +3492,7 @@ cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -3490,7 +3502,7 @@ cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -3500,7 +3512,7 @@ cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -3510,7 +3522,7 @@ cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -3520,7 +3532,7 @@ cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -3587,9 +3599,9 @@ cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { copt_net_87 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -3607,7 +3619,7 @@ cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -3625,7 +3637,7 @@ cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -3634,7 +3646,7 @@ cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -3643,7 +3655,7 @@ cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -3661,7 +3673,7 @@ cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -3704,32 +3716,32 @@ cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , - .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , - .X ( net_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( net_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_278 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ZBUF_6_f_1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( prog_clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , .X ( clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , - .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , @@ -3810,46 +3822,34 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) , +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) , +sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , - .X ( clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , - .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , - .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , - .X ( prog_clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_509_ ) , .X ( clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , - .X ( copt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_585 ( .A ( aps_rename_508_ ) , + .X ( clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_586 ( .A ( aps_rename_507_ ) , + .X ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_587 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1358 ( .A ( ropt_net_87 ) , .X ( prog_clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , - .X ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , - .X ( prog_clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_177 ) , + .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_278 ) , + .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3862,27 +3862,27 @@ output [0:0] mem_out ; input VDD ; input VSS ; -wire copt_net_55 ; +wire copt_net_60 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) , +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , - .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_60 ) , + .X ( copt_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( copt_net_55 ) , .X ( copt_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_56 ) , .X ( copt_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , .X ( copt_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , - .X ( copt_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , - .X ( copt_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_61 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1193 ( .A ( copt_net_58 ) , + .X ( copt_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4005,17 +4005,17 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( ccff_head[0] ) , .X ( copt_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_49 ) , .X ( copt_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_50 ) , .X ( copt_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( copt_net_51 ) , .X ( copt_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_52 ) , .X ( copt_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_53 ) , .X ( copt_net_54 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4108,10 +4108,14 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; -wire ropt_net_73 ; -wire ropt_net_75 ; -wire ropt_net_74 ; -wire ropt_net_72 ; +wire ropt_net_67 ; +wire ropt_net_68 ; +wire ropt_net_66 ; +wire ropt_net_65 ; +wire ropt_net_63 ; +wire ropt_net_69 ; +wire ropt_net_64 ; +wire ropt_net_62 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -4157,12 +4161,12 @@ sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , +sky130_fd_sc_hd__buf_6 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , @@ -4170,18 +4174,18 @@ sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__buf_6 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -4192,7 +4196,7 @@ sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , @@ -4208,10 +4212,10 @@ sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -4222,7 +4226,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_43__42 ( @@ -4231,14 +4235,22 @@ sky130_fd_sc_hd__buf_6 FTB_43__42 ( .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1194 ( .A ( ropt_net_62 ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1195 ( .A ( ropt_net_63 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1196 ( .A ( ropt_net_64 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1197 ( .A ( ropt_net_65 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1198 ( .A ( ropt_net_66 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1199 ( .A ( ropt_net_67 ) , .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1200 ( .A ( ropt_net_68 ) , .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1201 ( .A ( ropt_net_69 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4260,14 +4272,14 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_88 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_84 ) , + .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , + .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1310 ( .A ( copt_net_84 ) , - .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_86 ) , - .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4289,18 +4301,16 @@ supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_61 ) , .Y ( SOC_DIR_N ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .TE_B ( BUF_net_64 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_61 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_61 ( .A ( BUF_net_63 ) , .Y ( BUF_net_61 ) , + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_64 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4384,7 +4394,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -4750,6 +4760,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -4777,8 +4790,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4938,7 +4949,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4991,7 +5002,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5012,7 +5023,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -5183,9 +5194,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -5208,7 +5219,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_93 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_95 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -5218,24 +5229,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( ccff_head[0] ) , + .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_75 ) , + .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_78 ) , .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_79 ) , .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_82 ) , - .X ( ropt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1315 ( .A ( ropt_net_92 ) , - .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_80 ) , + .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1314 ( .A ( ropt_net_94 ) , + .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5296,7 +5305,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5421,7 +5430,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5638,6 +5647,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -5672,8 +5684,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5734,8 +5744,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5912,7 +5924,7 @@ cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -5922,7 +5934,7 @@ cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -5942,7 +5954,7 @@ cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -5952,7 +5964,7 @@ cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -5972,7 +5984,7 @@ cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -6035,7 +6047,7 @@ cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -6053,7 +6065,7 @@ cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , @@ -6071,7 +6083,7 @@ cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -6080,7 +6092,7 @@ cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -6098,7 +6110,7 @@ cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -6150,10 +6162,10 @@ cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , +sky130_fd_sc_hd__buf_12 FTB_20__19 ( .A ( chanx_left_in[1] ) , .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -6195,7 +6207,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__buf_12 FTB_41__40 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -6243,11 +6255,7 @@ sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , .HI ( optlc_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , .HI ( optlc_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521203 ( .A ( ctsbuf_net_174 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6266,11 +6274,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -6291,9 +6299,9 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -6343,7 +6351,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -6416,7 +6424,7 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -6581,9 +6589,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -6611,6 +6616,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6662,7 +6669,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6796,9 +6803,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -6826,6 +6830,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6877,7 +6883,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6891,33 +6897,29 @@ output [0:3] mem_out ; input VDD ; input VSS ; -wire copt_net_81 ; +wire copt_net_84 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_81 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 FTB_8__7 ( .A ( copt_net_83 ) , .X ( ccff_tail[0] ) , +sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_81 ) , - .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( mem_out[3] ) , - .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_84 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_87 ) , .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , - .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_85 ) , + .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_84 ) , + .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6939,7 +6941,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -7083,7 +7085,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_79 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_103 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -7093,18 +7095,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( ccff_head[0] ) , - .X ( copt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_74 ) , - .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_75 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_76 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( ccff_head[0] ) , .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_78 ) , + .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1323 ( .A ( copt_net_81 ) , + .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1324 ( .A ( ropt_net_102 ) , + .X ( ropt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7165,7 +7171,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7193,9 +7199,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -7230,6 +7233,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7681,7 +7686,6 @@ output clk_3_W_out ; input VDD ; input VSS ; -wire ropt_net_94 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -7745,7 +7749,7 @@ cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_71 ) ) ; + .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -7755,7 +7759,7 @@ cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_69 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -7765,7 +7769,7 @@ cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_71 ) ) ; + .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -7785,7 +7789,7 @@ cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_70 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -7805,7 +7809,7 @@ cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_70 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -7842,9 +7846,9 @@ cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_100 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -7853,7 +7857,7 @@ cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_71 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -7862,7 +7866,7 @@ cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_69 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -7871,7 +7875,7 @@ cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_71 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -7880,7 +7884,7 @@ cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_69 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -7889,7 +7893,7 @@ cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_70 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -7907,7 +7911,7 @@ cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_70 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -7956,32 +7960,32 @@ cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( prog_clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( net_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_70 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) , +sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , @@ -8066,36 +8070,32 @@ sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) , +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , .X ( REGOUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( prog_clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , - .Y ( prog_clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( net_net_69 ) , + .X ( prog_clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( net_net_70 ) , .X ( clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( clk_2_E_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , .HI ( optlc_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_79 ( .A ( aps_rename_507_ ) , + .X ( clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_506_ ) , + .X ( clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_175 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , - .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8108,27 +8108,25 @@ output [0:0] mem_out ; input VDD ; input VSS ; -wire copt_net_124 ; +wire copt_net_122 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_124 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_119 ) , - .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_124 ) , - .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_118 ) , - .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_122 ) , +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1346 ( .A ( copt_net_124 ) , .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , - .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_120 ) , - .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( copt_net_125 ) , + .X ( copt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_126 ) , + .X ( copt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_127 ) , + .X ( copt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_122 ) , + .X ( copt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8148,19 +8146,19 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) , .VPWR ( VDD ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_511_ ) , +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_88 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( BUF_net_88 ) , + .TE_B ( BUF_net_90 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_112 ( .A ( BUF_net_90 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8264,19 +8262,14 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_85 ) , .Y ( SOC_DIR_N ) , + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_85 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( BUF_net_85 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_87 ) , .Y ( SOC_DIR ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8382,17 +8375,19 @@ supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_82 ) , .Y ( SOC_DIR_N ) , +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_87 ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) , + .TE_B ( BUF_net_86 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_86 ( .A ( BUF_net_88 ) , .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( BUF_net_87 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_88 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8498,18 +8493,16 @@ supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_508_ ) , - .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .TE_B ( BUF_net_84 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) , + .TE_B ( BUF_net_81 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8612,20 +8605,15 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_76 ) , .Y ( SOC_DIR_N ) , + .B ( IO_ISOL_N ) , .Y ( net_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_76 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_76 ( .A ( BUF_net_78 ) , .Y ( BUF_net_76 ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8728,20 +8716,24 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) , .VPWR ( VDD ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_73 ) , .Y ( SOC_DIR_N ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_507_ ) , + .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_73 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_73 ( .A ( BUF_net_75 ) , .Y ( BUF_net_73 ) , + .TE_B ( BUF_net_77 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_77 ( .A ( BUF_net_79 ) , .Y ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( BUF_net_78 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( BUF_net_78 ) , .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8829,7 +8821,7 @@ endmodule module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_184_0 ) ; + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_211_0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -8839,19 +8831,19 @@ input FPGA_DIR ; input IO_ISOL_N ; input VDD ; input VSS ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_211_0 ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( ZBUF_184_0 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .TE_B ( ZBUF_211_0 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8859,7 +8851,7 @@ module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , - ZBUF_184_0 ) ; + ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -8871,7 +8863,7 @@ output [0:0] iopad_inpad ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; wire [0:0] EMBEDDED_IO_HD_0_en ; supply1 VDD ; @@ -8883,7 +8875,7 @@ cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_211_0 ( ZBUF_211_0 ) ) ; cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , @@ -8894,7 +8886,7 @@ endmodule module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , ZBUF_184_0 ) ; + ccff_tail , VDD , VSS , ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -8906,7 +8898,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; supply1 VDD ; supply0 VSS ; @@ -8918,7 +8910,7 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .VSS ( VSS ) , .ZBUF_211_0 ( ZBUF_211_0 ) ) ; endmodule @@ -8957,20 +8949,20 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_70 ) , .Y ( SOC_DIR_N ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_506_ ) , + .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) , + .TE_B ( BUF_net_74 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_76 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_4 BINV_R_74 ( .A ( BUF_net_76 ) , .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9073,15 +9065,20 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( net_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 BUFT_RR_69 ( .A ( net_net_69 ) , .X ( SOC_DIR ) , + .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9361,7 +9358,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_136 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -9371,6 +9368,20 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( ccff_head[0] ) , + .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_117 ) , + .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_118 ) , + .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_120 ) , + .X ( copt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_121 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9525,6 +9536,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -9559,8 +9573,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9621,10 +9633,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9685,7 +9697,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9747,10 +9759,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9811,10 +9823,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9875,10 +9887,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9939,7 +9949,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10062,7 +10072,7 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -10072,7 +10082,7 @@ cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -10082,7 +10092,7 @@ cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; + .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -10092,7 +10102,7 @@ cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; + .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -10102,7 +10112,7 @@ cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; + .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -10112,7 +10122,7 @@ cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; + .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -10122,7 +10132,7 @@ cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -10132,7 +10142,7 @@ cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -10142,7 +10152,7 @@ cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( bottom_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; + .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -10210,12 +10220,12 @@ cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_511_ } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_5_lower ) , .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; + .VSS ( VSS ) , .ZBUF_211_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , @@ -10275,10 +10285,10 @@ cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_17_lower ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_1115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -10399,16 +10409,16 @@ sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , - .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , - .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_211_inst_119 ( .A ( aps_rename_511_ ) , .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3521246 ( .A ( ctsbuf_net_1115 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10492,6 +10502,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -10502,10 +10515,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10535,10 +10544,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10568,7 +10577,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10582,23 +10591,21 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_102 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_102 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( copt_net_99 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_107 ) , - .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_105 ) , - .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( copt_net_102 ) , - .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_102 ) , + .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( mem_out[1] ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11133,10 +11140,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11215,10 +11222,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11243,8 +11248,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11317,15 +11324,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11344,16 +11350,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11378,7 +11383,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11404,10 +11409,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11432,10 +11435,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11454,14 +11457,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11508,15 +11512,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11535,14 +11538,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12083,7 +12087,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_109 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -12091,24 +12095,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1257 ( .A ( copt_net_95 ) , + .X ( copt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_91 ) , + .X ( copt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_93 ) , .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_96 ) , - .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_100 ) , - .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_98 ) , - .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_99 ) , - .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( copt_net_101 ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( ropt_net_117 ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , + .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1275 ( .A ( copt_net_92 ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1276 ( .A ( ropt_net_110 ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12421,7 +12425,7 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -12430,7 +12434,7 @@ sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -12439,7 +12443,7 @@ sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -12448,7 +12452,7 @@ sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -12475,7 +12479,7 @@ sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , @@ -12484,7 +12488,7 @@ sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -12493,7 +12497,7 @@ sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -12502,7 +12506,7 @@ sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -12527,145 +12531,145 @@ sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -12792,21 +12796,21 @@ sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -12836,14 +12840,14 @@ sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , - .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , - .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , + .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12856,29 +12860,31 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_106 ; +wire copt_net_103 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_103 ) , - .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_103 ) , .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_106 ) , - .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_104 ) , - .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( copt_net_105 ) , .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_107 ) , + .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_104 ) , + .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_108 ) , + .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , + .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13008,7 +13014,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13028,15 +13034,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13061,8 +13066,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13081,15 +13088,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13114,10 +13122,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13142,10 +13150,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13270,9 +13278,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -13283,6 +13288,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13312,8 +13321,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13333,9 +13344,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -13346,6 +13354,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13375,8 +13385,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13570,8 +13582,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13605,10 +13619,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13629,9 +13643,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -13645,6 +13656,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13726,10 +13739,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13821,6 +13834,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -13841,10 +13857,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13912,6 +13924,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -13932,10 +13947,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14144,10 +14155,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14195,7 +14206,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14220,9 +14231,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -14247,6 +14255,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14294,7 +14306,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14343,10 +14355,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14394,10 +14406,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14609,9 +14621,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -14660,6 +14669,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14759,9 +14772,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -14789,6 +14799,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14937,7 +14951,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_112 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -14947,26 +14961,6 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( ccff_head[0] ) , - .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_97 ) , - .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_99 ) , - .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , - .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1271 ( .A ( copt_net_100 ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1272 ( .A ( ropt_net_109 ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1273 ( .A ( ropt_net_110 ) , - .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15229,7 +15223,7 @@ sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , @@ -15240,7 +15234,7 @@ sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -15259,7 +15253,7 @@ sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] , @@ -15268,7 +15262,7 @@ sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , @@ -15278,7 +15272,7 @@ sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -15305,7 +15299,7 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , @@ -15318,7 +15312,7 @@ sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -15337,7 +15331,7 @@ sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] , @@ -15346,7 +15340,7 @@ sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , @@ -15355,7 +15349,7 @@ sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -15364,7 +15358,7 @@ sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -15373,7 +15367,7 @@ sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -15382,7 +15376,7 @@ sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -15391,7 +15385,7 @@ sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , @@ -15434,7 +15428,7 @@ sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , @@ -15443,7 +15437,7 @@ sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , @@ -15452,7 +15446,7 @@ sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -15477,7 +15471,7 @@ sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -15490,7 +15484,7 @@ sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 ( .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] , chanx_left_out[13] } ) , @@ -15498,7 +15492,7 @@ sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , @@ -15506,7 +15500,7 @@ sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 ( .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , @@ -15514,7 +15508,7 @@ sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , @@ -15541,35 +15535,35 @@ sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_bottom_out[15] , chany_top_out[15] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_bottom_out[17] , chany_top_out[17] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_bottom_out[18] , chany_top_out[18] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_out[19] , chany_top_out[19] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , @@ -15600,37 +15594,37 @@ sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , @@ -15661,7 +15655,7 @@ sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -15717,14 +15711,14 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) , .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , - .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , - .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , - .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15737,23 +15731,23 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_97 ; +wire copt_net_104 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_97 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_98 ) , - .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_102 ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_104 ) , + .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16219,10 +16213,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16241,16 +16235,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16329,10 +16322,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16357,10 +16350,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16385,10 +16378,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16407,6 +16400,34 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -16419,32 +16440,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -16466,10 +16461,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16548,10 +16543,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16597,15 +16592,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16651,15 +16647,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16684,8 +16681,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16704,15 +16703,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16731,15 +16731,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16939,10 +16938,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16962,9 +16961,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -16975,6 +16971,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16994,9 +16992,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -17007,6 +17002,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17137,10 +17134,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17179,10 +17174,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17204,9 +17199,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -17224,6 +17216,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17262,8 +17258,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_48 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17348,7 +17346,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_114 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_120 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -17356,24 +17354,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( ccff_head[0] ) , - .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1251 ( .A ( copt_net_89 ) , - .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_90 ) , - .X ( copt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_88 ) , - .X ( copt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( ropt_net_116 ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( copt_net_91 ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_99 ) , + .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_98 ) , + .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , + .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_97 ) , + .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1282 ( .A ( copt_net_95 ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1283 ( .A ( ropt_net_121 ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1284 ( .A ( ropt_net_119 ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17416,10 +17414,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_46 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17462,10 +17460,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_43 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17488,9 +17484,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -17511,6 +17504,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_43 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17598,7 +17595,7 @@ input prog_clk_0_N_in ; input VDD ; input VSS ; -wire ropt_net_104 ; +wire ropt_net_110 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -17681,7 +17678,7 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -17690,7 +17687,7 @@ sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -17699,7 +17696,7 @@ sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -17708,7 +17705,7 @@ sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -17735,7 +17732,7 @@ sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -17744,7 +17741,7 @@ sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -17753,7 +17750,7 @@ sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -17762,7 +17759,7 @@ sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -17788,28 +17785,28 @@ sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -17835,133 +17832,133 @@ sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -18074,28 +18071,30 @@ sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[3] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[5] ) , +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_left_in[5] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) , .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , - .HI ( optlc_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , - .HI ( optlc_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18108,7 +18107,6 @@ output [0:2] mem_out ; input VDD ; input VSS ; -wire copt_net_105 ; supply1 VDD ; supply0 VSS ; @@ -18116,23 +18114,16 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_105 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_104 ) , - .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_105 ) , - .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_103 ) , - .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_101 ) , - .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_100 ) , - .X ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_109 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( mem_out[2] ) , + .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1295 ( .A ( copt_net_108 ) , + .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18155,9 +18146,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -18178,6 +18166,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18381,7 +18371,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18402,6 +18392,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -18412,10 +18405,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18445,10 +18434,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18468,9 +18457,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -18481,6 +18467,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18670,9 +18660,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -18686,6 +18673,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18783,10 +18772,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19018,10 +19005,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19045,9 +19032,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -19072,6 +19056,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19119,7 +19107,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19218,10 +19206,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19245,9 +19231,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -19272,6 +19255,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19319,8 +19306,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19472,10 +19461,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19658,10 +19647,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19692,9 +19681,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -19743,6 +19729,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19843,6 +19831,66 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -19881,7 +19929,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , endmodule -module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:8] in ; input [0:3] sram ; @@ -19941,65 +19989,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , endmodule -module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; @@ -20012,7 +20001,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_99 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_130 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -20022,18 +20011,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_96 ) , - .X ( copt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_97 ) , - .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_94 ) , - .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( ccff_head[0] ) , + .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_100 ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_104 ) , + .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_105 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_131 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1317 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20156,7 +20151,8 @@ input prog_clk_0_S_in ; input VDD ; input VSS ; -wire ropt_net_115 ; +wire ropt_net_118 ; +wire ropt_net_119 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -20229,7 +20225,7 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -20243,7 +20239,7 @@ sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , @@ -20253,7 +20249,7 @@ sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -20263,7 +20259,7 @@ sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -20290,7 +20286,7 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -20302,7 +20298,7 @@ sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , @@ -20322,7 +20318,7 @@ sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , @@ -20331,7 +20327,7 @@ sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -20349,7 +20345,7 @@ sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -20358,7 +20354,7 @@ sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -20367,7 +20363,7 @@ sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -20376,7 +20372,7 @@ sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -20385,7 +20381,7 @@ sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -20394,7 +20390,7 @@ sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , @@ -20403,7 +20399,7 @@ sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , @@ -20412,7 +20408,7 @@ sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -20460,7 +20456,7 @@ sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -20473,7 +20469,7 @@ sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 ( .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] , chanx_right_out[10] , chanx_left_in[19] } ) , @@ -20481,7 +20477,7 @@ sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 ( .in ( { chanx_left_out[19] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) , @@ -20489,7 +20485,7 @@ sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , @@ -20511,42 +20507,42 @@ sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -20582,7 +20578,7 @@ sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , @@ -20596,18 +20592,18 @@ sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) , @@ -20618,7 +20614,7 @@ sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[7] ) , +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) , .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -20668,23 +20664,23 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_115 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1314 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_115 ) , +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , + .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , + .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_118 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_119 ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20698,6 +20694,7 @@ output [0:2] mem_out ; input VDD ; input VSS ; +wire copt_net_120 ; supply1 VDD ; supply0 VSS ; @@ -20706,11 +20703,12 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_119 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( mem_out[2] ) , - .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_120 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_120 ) , + .X ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20903,9 +20901,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -20930,6 +20925,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20977,8 +20976,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21305,9 +21306,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -21342,6 +21340,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21402,7 +21402,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21464,10 +21464,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21717,10 +21717,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21781,10 +21781,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21811,6 +21811,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -21845,10 +21848,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21875,6 +21874,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -21909,8 +21911,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21937,6 +21937,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -21971,8 +21974,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22033,10 +22034,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22502,10 +22503,10 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , - .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22696,7 +22697,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_124 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_125 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -22706,26 +22707,26 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_113 ) , - .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_108 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_114 ) , .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_109 ) , .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_110 ) , .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_111 ) , .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_112 ) , .X ( copt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_122 ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1302 ( .A ( copt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( copt_net_113 ) , .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1303 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_122 ) , .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1304 ( .A ( ropt_net_123 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1311 ( .A ( ropt_net_123 ) , .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1312 ( .A ( ropt_net_124 ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22867,10 +22868,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22899,9 +22898,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -22943,6 +22939,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -23012,7 +23010,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -23114,6 +23112,79 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -23161,79 +23232,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:11] in ; @@ -23259,6 +23257,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -23300,8 +23301,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -23526,7 +23525,7 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -23548,7 +23547,7 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -23559,7 +23558,7 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] , chanx_left_out[13] , chanx_right_in[15] , @@ -23570,7 +23569,7 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] , chanx_right_in[11] , chanx_left_out[14] , @@ -23592,7 +23591,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] , chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , @@ -23603,7 +23602,7 @@ sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -23670,7 +23669,7 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 ( SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] , @@ -23698,7 +23697,7 @@ sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 ( SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , @@ -23738,7 +23737,7 @@ sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] , @@ -23748,7 +23747,7 @@ sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , @@ -23768,7 +23767,7 @@ sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , @@ -23778,7 +23777,7 @@ sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; + .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] , chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] , @@ -23808,7 +23807,7 @@ sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 ( .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] , chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] , @@ -23828,7 +23827,7 @@ sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] , chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] , @@ -23838,7 +23837,7 @@ sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -23909,7 +23908,7 @@ sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , @@ -23918,7 +23917,7 @@ sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , @@ -23936,7 +23935,7 @@ sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , @@ -23957,8 +23956,8 @@ sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 ( .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , - .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) , @@ -24065,18 +24064,20 @@ sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) , .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) , .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24177,7 +24178,7 @@ output [0:2] mem_out ; input VDD ; input VSS ; -wire copt_net_107 ; +wire copt_net_106 ; supply1 VDD ; supply0 VSS ; @@ -24186,15 +24187,15 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_107 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_106 ) , - .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_107 ) , - .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1288 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_106 ) , + .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_109 ) , + .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1290 ( .A ( copt_net_110 ) , .X ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24241,9 +24242,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -24264,6 +24262,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24306,10 +24306,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24519,10 +24519,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24629,8 +24627,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24735,8 +24735,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24913,10 +24915,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24969,6 +24971,38 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -24986,7 +25020,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -25019,7 +25053,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -25052,7 +25086,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -25085,37 +25119,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; @@ -25215,6 +25218,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -25228,8 +25234,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25538,10 +25542,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25565,9 +25569,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -25592,6 +25593,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25615,9 +25620,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -25642,6 +25644,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25842,24 +25846,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_99 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_102 ) , .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_100 ) , .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_105 ) , .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( ccff_head[0] ) , .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_101 ) , + .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( copt_net_104 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_131 ) , .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_132 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_132 ) , .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( copt_net_103 ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26019,10 +26023,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26143,6 +26145,7 @@ output clk_3_N_out ; input VDD ; input VSS ; +wire ropt_net_119 ; wire ropt_net_118 ; wire [0:0] prog_clk ; wire prog_clk_0 ; @@ -26215,7 +26218,7 @@ sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , @@ -26225,7 +26228,7 @@ sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] , chanx_left_out[14] , left_bottom_grid_pin_3_[0] , @@ -26235,7 +26238,7 @@ sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] , @@ -26244,7 +26247,7 @@ sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -26271,7 +26274,7 @@ sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -26280,7 +26283,7 @@ sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -26289,7 +26292,7 @@ sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , SYNOPSYS_UNCONNECTED_25 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , @@ -26298,7 +26301,7 @@ sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] , @@ -26316,7 +26319,7 @@ sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] , @@ -26325,7 +26328,7 @@ sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -26368,7 +26371,7 @@ sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 ( .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] , chanx_right_out[10] } ) , @@ -26376,7 +26379,7 @@ sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , @@ -26392,49 +26395,49 @@ sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -26474,7 +26477,7 @@ sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -26498,7 +26501,7 @@ sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -26533,7 +26536,7 @@ sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , @@ -26552,7 +26555,7 @@ sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_left_out[11] , left_bottom_grid_pin_7_[0] , @@ -26561,7 +26564,7 @@ sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , @@ -26581,14 +26584,14 @@ sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , @@ -26633,8 +26636,8 @@ sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[7] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) , @@ -26649,8 +26652,8 @@ sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) , .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) , @@ -26659,30 +26662,32 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) , .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( Test_en_N_out ) , +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( Test_en_S_in ) , .Y ( BUF_net_86 ) , +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( Test_en_S_in ) , .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( clk_3_N_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_118 ) , + .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26695,27 +26700,25 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_79 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_79 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( copt_net_71 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_79 ) , - .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_75 ) , - .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1240 ( .A ( copt_net_76 ) , - .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1241 ( .A ( copt_net_77 ) , - .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1242 ( .A ( copt_net_78 ) , - .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( mem_out[1] ) , + .X ( copt_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_74 ) , + .X ( copt_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1237 ( .A ( copt_net_70 ) , + .X ( copt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_72 ) , + .X ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_73 ) , + .X ( copt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27097,7 +27100,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27150,7 +27153,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27176,7 +27179,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27229,7 +27232,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27282,10 +27285,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27310,9 +27313,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_56 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_58 ( .A ( BUF_net_49 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27332,32 +27335,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -27370,6 +27347,32 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -27412,16 +27415,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27500,10 +27502,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27522,14 +27522,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27628,10 +27629,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_45 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27651,6 +27652,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -27661,10 +27665,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27749,10 +27749,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_44 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_43 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27774,6 +27774,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -27791,8 +27794,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27831,7 +27832,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_131 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_118 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -27839,22 +27840,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_69 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( ccff_head[0] ) , + .X ( copt_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_63 ) , + .X ( copt_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1230 ( .A ( copt_net_64 ) , + .X ( copt_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_68 ) , + .X ( copt_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_65 ) , + .X ( copt_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_67 ) , .X ( copt_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_71 ) , - .X ( copt_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_73 ) , - .X ( copt_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_70 ) , - .X ( copt_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( ccff_head[0] ) , - .X ( copt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_72 ) , - .X ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1292 ( .A ( ropt_net_132 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1293 ( .A ( copt_net_68 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1281 ( .A ( copt_net_66 ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1282 ( .A ( ropt_net_117 ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27976,8 +27977,8 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; -wire ropt_net_95 ; -wire ropt_net_96 ; +wire ropt_net_88 ; +wire ropt_net_87 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -28040,7 +28041,7 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , @@ -28049,7 +28050,7 @@ sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -28067,7 +28068,7 @@ sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -28076,7 +28077,7 @@ sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -28093,14 +28094,14 @@ sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -28116,109 +28117,109 @@ sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -28319,20 +28320,20 @@ sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chanx_right_in[4] ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) , .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[8] ) , .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) , @@ -28341,19 +28342,19 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , - .HI ( optlc_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , - .HI ( optlc_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1257 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_96 ) , +sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , + .HI ( optlc_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , + .HI ( optlc_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , + .HI ( optlc_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1252 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1253 ( .A ( ropt_net_88 ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28532,10 +28533,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28554,15 +28555,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28587,10 +28587,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28615,10 +28615,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28643,10 +28643,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28659,29 +28659,27 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_125 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_125 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_125 ) , - .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_120 ) , - .X ( copt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_121 ) , - .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_122 ) , - .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_123 ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( copt_net_129 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( mem_out[1] ) , .X ( copt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_124 ) , - .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( copt_net_124 ) , + .X ( copt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_125 ) , + .X ( copt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_126 ) , + .X ( copt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_127 ) , + .X ( copt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_128 ) , + .X ( copt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28795,10 +28793,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28828,8 +28826,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28849,6 +28849,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -28859,8 +28862,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28890,10 +28891,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29042,10 +29043,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29093,10 +29094,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29120,6 +29121,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -29144,8 +29148,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29340,10 +29342,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29377,10 +29379,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29450,10 +29452,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29487,10 +29489,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29511,9 +29513,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -29527,6 +29526,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29560,7 +29563,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29715,10 +29718,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29822,6 +29825,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -29839,10 +29845,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29881,10 +29883,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30038,7 +30038,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_129 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_133 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -30046,24 +30046,24 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_115 ) , - .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_114 ) , - .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_119 ) , - .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_116 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_120 ) , .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_118 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_121 ) , .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1289 ( .A ( copt_net_117 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1290 ( .A ( ropt_net_127 ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1291 ( .A ( ropt_net_128 ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_123 ) , + .X ( copt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( ccff_head[0] ) , + .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1299 ( .A ( copt_net_118 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( ropt_net_131 ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30221,9 +30221,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -30244,6 +30241,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30286,8 +30285,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30330,10 +30331,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30356,6 +30355,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -30376,8 +30378,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30489,7 +30489,7 @@ sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) , @@ -30497,7 +30497,7 @@ sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) , @@ -30505,7 +30505,7 @@ sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , @@ -30514,7 +30514,7 @@ sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , @@ -30522,7 +30522,7 @@ sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , @@ -30530,7 +30530,7 @@ sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , @@ -30538,7 +30538,7 @@ sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -30580,7 +30580,7 @@ sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_top_out[9] , chany_top_out[18] } ) , @@ -30588,7 +30588,7 @@ sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , @@ -30596,7 +30596,7 @@ sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , @@ -30604,7 +30604,7 @@ sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , @@ -30612,7 +30612,7 @@ sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -30645,7 +30645,7 @@ sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_top_out[11] } ) , @@ -30653,7 +30653,7 @@ sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_bottom_out[9] , right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) , @@ -30661,7 +30661,7 @@ sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) , @@ -30669,7 +30669,7 @@ sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) , @@ -30677,7 +30677,7 @@ sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 ( .in ( { chany_bottom_out[13] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) , @@ -30685,7 +30685,7 @@ sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 ( .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] , chany_top_out[19] , chany_bottom_in[19] } ) , @@ -30693,7 +30693,7 @@ sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -30738,7 +30738,7 @@ sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[6] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -30748,7 +30748,7 @@ sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -30758,7 +30758,7 @@ sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , @@ -30780,33 +30780,33 @@ sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 ( .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 ( .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 ( .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -30837,37 +30837,37 @@ sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , @@ -30954,14 +30954,16 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , + .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_93 ) , + .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31033,10 +31035,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31177,9 +31179,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -31197,6 +31196,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31330,10 +31333,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31346,18 +31349,18 @@ output [0:1] mem_out ; input VDD ; input VSS ; +wire copt_net_92 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_91 ) , .X ( ccff_tail[0] ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_92 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1251 ( .A ( mem_out[1] ) , - .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_92 ) , .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_88 ) , .X ( copt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -31365,6 +31368,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_89 ) , .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_90 ) , .X ( copt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1256 ( .A ( copt_net_91 ) , + .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31716,28 +31721,28 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_137 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1244 ( .A ( ccff_head[0] ) , - .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( copt_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( ccff_head[0] ) , .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1246 ( .A ( copt_net_85 ) , .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1247 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1249 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( copt_net_84 ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1280 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( copt_net_82 ) , + .X ( copt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( copt_net_84 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1301 ( .A ( ropt_net_136 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31756,16 +31761,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31790,10 +31794,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31818,10 +31822,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31846,10 +31850,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31874,10 +31878,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31902,10 +31906,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31957,10 +31961,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31985,10 +31989,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_55 ( .A ( BUF_net_56 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32013,10 +32017,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_53 ( .A ( BUF_net_54 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_54 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32041,10 +32045,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32069,10 +32073,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_48 ( .A ( BUF_net_49 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32097,10 +32101,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_47 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32125,10 +32129,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_45 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32180,7 +32184,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32206,8 +32210,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_43 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_43 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32266,6 +32272,7 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; +wire ropt_net_107 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -32325,109 +32332,109 @@ sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -32525,7 +32532,7 @@ sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , @@ -32534,7 +32541,7 @@ sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , @@ -32553,7 +32560,7 @@ sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , @@ -32562,7 +32569,7 @@ sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -32579,14 +32586,14 @@ sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -32613,8 +32620,8 @@ sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) , .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) , .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) , @@ -32631,14 +32638,16 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , +sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , .HI ( optlc_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , + .HI ( optlc_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32656,21 +32665,21 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( copt_net_165 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1947 ( .A ( copt_net_162 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1943 ( .A ( mem_out[1] ) , .X ( copt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1948 ( .A ( copt_net_160 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1944 ( .A ( copt_net_160 ) , .X ( copt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1949 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1945 ( .A ( copt_net_161 ) , .X ( copt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1950 ( .A ( copt_net_161 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1946 ( .A ( copt_net_162 ) , .X ( copt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1951 ( .A ( copt_net_163 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1947 ( .A ( copt_net_163 ) , .X ( copt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1952 ( .A ( copt_net_164 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1948 ( .A ( copt_net_164 ) , .X ( copt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32687,7 +32696,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -32710,7 +32719,7 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -32804,9 +32813,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( p_abuf0 ) , .Y ( BUF_net_121 ) , +sky130_fd_sc_hd__buf_1 BUFT_RR_119 ( .A ( p_abuf0 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32832,9 +32839,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( p_abuf0 ) , .Y ( BUF_net_119 ) , +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( p_abuf0 ) , .Y ( BUF_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32857,10 +32864,10 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .Q ( net_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 BUFT_RR_73 ( .A ( copt_net_168 ) , .X ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1955 ( .A ( copt_net_169 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1950 ( .A ( net_net_73 ) , + .X ( copt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1951 ( .A ( copt_net_167 ) , .X ( copt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1956 ( .A ( net_net_73 ) , - .X ( copt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33292,10 +33299,10 @@ grid_clb_mux_tree_size2_mem_31 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , grid_clb_mux_tree_size2_mem mem_ff_1_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( ropt_net_170 ) , .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1959 ( .A ( fabric_sc_out[0] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1954 ( .A ( fabric_sc_out[0] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33418,14 +33425,14 @@ endmodule module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -33434,21 +33441,21 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -33457,7 +33464,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33484,12 +33491,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_517_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33514,12 +33521,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_516_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33583,14 +33590,14 @@ endmodule module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -33599,7 +33606,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33829,7 +33836,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p3 ) ; + VSS , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -33837,7 +33844,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -33863,7 +33870,7 @@ grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -33874,7 +33881,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p3 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -33891,7 +33898,6 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -33913,7 +33919,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -33947,7 +33953,7 @@ grid_clb_mux_tree_size2_27 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_38 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -33955,7 +33961,7 @@ grid_clb_mux_tree_size2_38 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_25 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -33979,7 +33985,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p0 , p3 ) ; + p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -33996,7 +34002,6 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p3 ; supply1 VDD ; supply0 VSS ; @@ -34007,8 +34012,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , - .p3 ( p3 ) ) ; + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; endmodule @@ -34097,14 +34101,14 @@ endmodule module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -34113,21 +34117,21 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -34136,14 +34140,14 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p3 ) ; + p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -34151,7 +34155,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -34160,20 +34164,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p3 ) ; + p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -34181,7 +34185,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -34190,15 +34194,15 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34262,14 +34266,14 @@ endmodule module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -34278,7 +34282,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34508,7 +34512,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p3 ) ; + VSS , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -34516,7 +34520,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -34542,7 +34546,7 @@ grid_clb_mux_tree_size2_20 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_20 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -34553,7 +34557,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p3 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -34569,7 +34573,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -34591,7 +34595,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -34610,7 +34614,7 @@ grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -34618,14 +34622,14 @@ grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_37 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -34633,7 +34637,7 @@ grid_clb_mux_tree_size2_37 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -34657,7 +34661,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p3 ) ; + p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -34673,7 +34677,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p3 ; +input p0 ; supply1 VDD ; supply0 VSS ; @@ -34684,7 +34688,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) ) ; + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; endmodule @@ -34819,7 +34823,7 @@ endmodule module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p3 ) ; + p_abuf0 , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -34827,7 +34831,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -34836,20 +34840,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_513_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p3 ) ; + p_abuf0 , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -34857,7 +34861,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -34866,15 +34870,15 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35229,7 +35233,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p2 , p3 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -35246,7 +35250,6 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p2 ; -input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -35287,7 +35290,7 @@ grid_clb_mux_tree_size2_17 mux_fabric_out_0 ( .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_18 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -35295,7 +35298,7 @@ grid_clb_mux_tree_size2_18 mux_fabric_out_1 ( .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_19 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -35334,7 +35337,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p2 , p3 ) ; + p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -35351,7 +35354,6 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p2 ; -input p3 ; supply1 VDD ; supply0 VSS ; @@ -35362,8 +35364,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) , - .p3 ( p3 ) ) ; + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; endmodule @@ -35475,14 +35476,14 @@ endmodule module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -35491,7 +35492,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35518,17 +35519,17 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p2 ) ; + p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -35536,7 +35537,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -35545,15 +35546,15 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35617,14 +35618,14 @@ endmodule module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -35633,7 +35634,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35863,7 +35864,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p2 ) ; + VSS , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -35871,7 +35872,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -35897,7 +35898,7 @@ grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_12 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -35908,7 +35909,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p2 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -35924,6 +35925,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -35946,7 +35948,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -35965,7 +35967,7 @@ grid_clb_mux_tree_size2_13 mux_fabric_out_0 ( .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_14 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -35980,7 +35982,7 @@ grid_clb_mux_tree_size2_15 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -36012,7 +36014,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p2 ) ; + p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -36028,6 +36030,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; supply1 VDD ; @@ -36039,7 +36042,8 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , + .p2 ( p2 ) ) ; endmodule @@ -36128,14 +36132,14 @@ endmodule module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -36144,7 +36148,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36194,12 +36198,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36224,12 +36228,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36293,14 +36297,14 @@ endmodule module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -36309,7 +36313,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36539,7 +36543,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p2 ) ; + VSS , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -36547,7 +36551,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -36573,7 +36577,7 @@ grid_clb_mux_tree_size2_8 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_8 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -36584,7 +36588,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p2 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -36601,7 +36605,6 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -36623,7 +36626,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -36665,7 +36668,7 @@ grid_clb_mux_tree_size2_34 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -36689,7 +36692,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p0 , p2 ) ; + p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -36706,7 +36709,6 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; supply1 VDD ; supply0 VSS ; @@ -36717,8 +36719,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , - .p2 ( p2 ) ) ; + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; endmodule @@ -36807,14 +36808,14 @@ endmodule module grid_clb_mux_tree_size2_33 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -36823,7 +36824,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36871,12 +36872,14 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( p_abuf0 ) , .Y ( BUF_net_87 ) , +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36899,11 +36902,11 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( out[0] ) , .Y ( BUF_net_85 ) , +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf0 ) , .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37340,7 +37343,7 @@ grid_clb_mux_tree_size2_33 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_5 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -37546,14 +37549,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_82 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( out[0] ) , .Y ( BUF_net_81 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37576,12 +37577,14 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( p_abuf0 ) , .Y ( BUF_net_77 ) , +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_78 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37679,7 +37682,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_167 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_159 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -37722,18 +37725,18 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1942 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1937 ( .A ( copt_net_156 ) , + .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1938 ( .A ( copt_net_158 ) , .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1943 ( .A ( copt_net_155 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1939 ( .A ( copt_net_157 ) , .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1944 ( .A ( copt_net_159 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1940 ( .A ( copt_net_155 ) , .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1945 ( .A ( copt_net_157 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1941 ( .A ( ccff_head[0] ) , .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1946 ( .A ( copt_net_156 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1942 ( .A ( copt_net_154 ) , .X ( copt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1954 ( .A ( copt_net_158 ) , - .X ( copt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38090,7 +38093,7 @@ module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clb_I0 , clb_reg_out , clb_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 , p_abuf13 , p_abuf14 , - p_abuf15 , p0 , p1 , p2 , p3 , p4 ) ; + p_abuf15 , p0 , p1 , p2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:2] clb_I0 ; @@ -38139,7 +38142,6 @@ input p0 ; input p1 ; input p2 ; input p3 ; -input p4 ; wire [0:0] direct_interc_29_out ; wire [0:0] direct_interc_36_out ; @@ -38201,7 +38203,7 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf4 ) , - .p_abuf1 ( p_abuf5 ) , .p0 ( p0 ) , .p2 ( p3 ) ) ; + .p_abuf1 ( p_abuf5 ) , .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3[2] , clb_I3i[0] } ) , @@ -38214,7 +38216,7 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf6 ) , - .p_abuf1 ( p_abuf7 ) , .p2 ( p3 ) ) ; + .p_abuf1 ( p_abuf7 ) , .p0 ( p0 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4[2] , clb_I4i[0] } ) , @@ -38227,7 +38229,7 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf8 ) , - .p_abuf1 ( p_abuf9 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; + .p_abuf1 ( p_abuf9 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5[2] , clb_I5i[0] } ) , @@ -38240,7 +38242,7 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf10 ) , - .p_abuf1 ( p_abuf11 ) , .p3 ( p4 ) ) ; + .p_abuf1 ( p_abuf11 ) , .p0 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6[2] , clb_I6i[0] } ) , @@ -38253,7 +38255,7 @@ grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf12 ) , - .p_abuf1 ( p_abuf13 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; + .p_abuf1 ( p_abuf13 ) , .p0 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7[2] , clb_I7i[0] } ) , @@ -38404,8 +38406,9 @@ input clk_0_S_in ; input VDD ; input VSS ; -wire p_abuf0 ; -wire p_abuf3 ; +wire p_abuf2 ; +wire p_abuf8 ; +wire p_abuf12 ; wire prog_clk_0 ; wire [0:0] prog_clk ; wire [0:0] clk ; @@ -38455,61 +38458,62 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_reg_in ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_520_ , top_width_0_height_0__pin_35_lower[0] , - top_width_0_height_0__pin_36_lower[0] , aps_rename_523_ , - aps_rename_524_ , aps_rename_525_ , aps_rename_526_ , - aps_rename_527_ , aps_rename_528_ , aps_rename_529_ , + .clb_O ( { aps_rename_520_ , aps_rename_521_ , aps_rename_522_ , + top_width_0_height_0__pin_37_lower[0] , aps_rename_524_ , + aps_rename_525_ , aps_rename_526_ , aps_rename_527_ , + aps_rename_528_ , right_width_0_height_0__pin_43_lower[0] , aps_rename_530_ , aps_rename_531_ , aps_rename_532_ , - aps_rename_533_ , aps_rename_534_ , aps_rename_535_ } ) , + right_width_0_height_0__pin_47_lower[0] , aps_rename_534_ , + aps_rename_535_ } ) , .clb_reg_out ( bottom_width_0_height_0__pin_50_ ) , .clb_sc_out ( { SC_OUT_BOT } ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , + .p_abuf0 ( top_width_0_height_0__pin_35_lower[0] ) , .p_abuf1 ( top_width_0_height_0__pin_34_lower[0] ) , - .p_abuf2 ( top_width_0_height_0__pin_37_lower[0] ) , - .p_abuf3 ( p_abuf3 ) , + .p_abuf2 ( p_abuf2 ) , + .p_abuf3 ( top_width_0_height_0__pin_36_lower[0] ) , .p_abuf4 ( top_width_0_height_0__pin_39_lower[0] ) , .p_abuf5 ( top_width_0_height_0__pin_38_lower[0] ) , .p_abuf6 ( top_width_0_height_0__pin_41_lower[0] ) , .p_abuf7 ( top_width_0_height_0__pin_40_lower[0] ) , - .p_abuf8 ( right_width_0_height_0__pin_43_lower[0] ) , + .p_abuf8 ( p_abuf8 ) , .p_abuf9 ( right_width_0_height_0__pin_42_lower[0] ) , .p_abuf10 ( right_width_0_height_0__pin_45_lower[0] ) , .p_abuf11 ( right_width_0_height_0__pin_44_lower[0] ) , - .p_abuf12 ( right_width_0_height_0__pin_47_lower[0] ) , + .p_abuf12 ( p_abuf12 ) , .p_abuf13 ( right_width_0_height_0__pin_46_lower[0] ) , .p_abuf14 ( right_width_0_height_0__pin_49_lower[0] ) , .p_abuf15 ( right_width_0_height_0__pin_48_lower[0] ) , .p0 ( optlc_net_146 ) , .p1 ( optlc_net_147 ) , .p2 ( optlc_net_148 ) , - .p3 ( optlc_net_149 ) , .p4 ( optlc_net_150 ) ) ; + .p3 ( optlc_net_149 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , - .X ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , .X ( aps_rename_536_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_12 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_1150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_2151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_3152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_4153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( aps_rename_520_ ) , .X ( top_width_0_height_0__pin_34_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( p_abuf0 ) , +sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( aps_rename_521_ ) , .X ( top_width_0_height_0__pin_35_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( p_abuf3 ) , +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( aps_rename_522_ ) , .X ( top_width_0_height_0__pin_36_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( aps_rename_523_ ) , +sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( p_abuf2 ) , .X ( top_width_0_height_0__pin_37_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( aps_rename_524_ ) , @@ -38527,7 +38531,7 @@ sky130_fd_sc_hd__buf_6 FTB_64__63 ( .A ( aps_rename_527_ ) , sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_528_ ) , .X ( right_width_0_height_0__pin_42_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_529_ ) , +sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( p_abuf8 ) , .X ( right_width_0_height_0__pin_43_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_530_ ) , @@ -38539,7 +38543,7 @@ sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_531_ ) , sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_532_ ) , .X ( right_width_0_height_0__pin_46_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_533_ ) , +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( p_abuf12 ) , .X ( right_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_534_ ) , @@ -38550,6 +38554,10 @@ sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_535_ ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( SC_OUT_BOT ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , + .Y ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( aps_rename_536_ ) , + .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , @@ -38558,17 +38566,13 @@ sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_133 ( .A ( aps_rename_536_ ) , - .X ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3901298 ( .A ( ctsbuf_net_1151 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3901295 ( .A ( ctsbuf_net_1150 ) , .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3951303 ( .A ( ctsbuf_net_2152 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3951300 ( .A ( ctsbuf_net_2151 ) , .X ( prog_clk_0_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4001308 ( .A ( ctsbuf_net_3153 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4001305 ( .A ( ctsbuf_net_3152 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4051313 ( .A ( ctsbuf_net_4154 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4051310 ( .A ( ctsbuf_net_4153 ) , .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90428,15 +90432,15 @@ endmodule module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 , vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i , wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in , - la_data_out , la_oen , io_in , io_out , io_oeb , VDD , VSS , - analog_io_0_ , analog_io_10_ , analog_io_11_ , analog_io_12_ , - analog_io_13_ , analog_io_14_ , analog_io_15_ , analog_io_16_ , - analog_io_17_ , analog_io_18_ , analog_io_19_ , analog_io_1_ , - analog_io_20_ , analog_io_21_ , analog_io_22_ , analog_io_23_ , - analog_io_24_ , analog_io_25_ , analog_io_26_ , analog_io_27_ , - analog_io_28_ , analog_io_29_ , analog_io_2_ , analog_io_30_ , - analog_io_3_ , analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , - analog_io_8_ , analog_io_9_ , user_clock2 ) ; + la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ , + analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ , + analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ , + analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ , + analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ , + analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ , + analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ , + analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ , + analog_io_9_ , user_clock2 , VDD , VSS ) ; inout vdda1 ; inout vdda2 ; inout vssa1 ; @@ -90461,8 +90465,6 @@ input [127:0] la_oen ; input [37:0] io_in ; output [37:0] io_out ; output [37:0] io_oeb ; -input VDD ; -input VSS ; inout analog_io_0_ ; inout analog_io_10_ ; inout analog_io_11_ ; @@ -90495,6 +90497,8 @@ inout analog_io_7_ ; inout analog_io_8_ ; inout analog_io_9_ ; input user_clock2 ; +input VDD ; +input VSS ; wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef b/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef deleted file mode 100644 index 4819793..0000000 --- a/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:3090ec753012c0eb7b9add66be2d98ddf2a367909aad8ab02c16961d71c8102f -size 28278825 diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz b/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz new file mode 100644 index 0000000..2f86865 Binary files /dev/null and b/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz differ diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v index 9d9a066..bd9b5ec 100644 --- a/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v @@ -11,12 +11,19 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; +wire copt_net_88 ; + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( copt_net_90 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( mem_out[0] ) , - .X ( copt_net_90 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_88 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_89 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_88 ) , + .X ( copt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_86 ) , + .X ( copt_net_87 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_87 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1311 ( .A ( mem_out[0] ) , + .X ( copt_net_89 ) ) ; endmodule @@ -30,17 +37,17 @@ input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , - .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_59 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_60 ) ) ; + .TE_B ( BUF_net_59 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_59 ( .A ( BUF_net_61 ) , .Y ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_61 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -105,11 +112,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -122,11 +129,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -143,7 +150,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -181,11 +188,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -198,13 +205,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -219,11 +226,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -236,13 +243,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -396,50 +403,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -468,6 +431,50 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -609,11 +616,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -626,13 +633,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -664,13 +671,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -685,11 +692,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -708,7 +715,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -721,13 +728,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -740,13 +747,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -759,31 +766,33 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_92 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_86 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ropt_net_94 ) , + .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( ccff_head[0] ) , .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1305 ( .A ( copt_net_85 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1308 ( .A ( ccff_head[0] ) , - .X ( copt_net_86 ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1309 ( .A ( copt_net_82 ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_83 ) , - .X ( copt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1311 ( .A ( copt_net_88 ) , - .X ( copt_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( copt_net_84 ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_82 ) , + .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_93 ) , + .X ( ropt_net_94 ) ) ; endmodule @@ -857,6 +866,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -886,9 +897,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_67 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; endmodule @@ -939,9 +947,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_67 ) ) ; endmodule @@ -1044,9 +1052,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_65 ) ) ; endmodule @@ -1097,7 +1105,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1172,8 +1180,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1203,6 +1209,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1350,7 +1358,7 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1359,7 +1367,7 @@ cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1368,7 +1376,7 @@ cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1377,7 +1385,7 @@ cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -1386,7 +1394,7 @@ cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1395,7 +1403,7 @@ cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1404,7 +1412,7 @@ cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1413,7 +1421,7 @@ cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1422,7 +1430,7 @@ cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1474,7 +1482,7 @@ cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1482,7 +1490,7 @@ cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1490,7 +1498,7 @@ cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1498,7 +1506,7 @@ cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1506,7 +1514,7 @@ cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1514,7 +1522,7 @@ cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1522,7 +1530,7 @@ cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1530,7 +1538,7 @@ cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -1578,14 +1586,14 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( { ropt_net_91 } ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) ) ; + .X ( ctsbuf_net_177 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) ) ; + .X ( ctsbuf_net_278 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , @@ -1669,22 +1677,18 @@ sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) , sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( left_width_0_height_0__pin_1_lower[0] ) , .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_73 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3471203 ( .A ( ctsbuf_net_177 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521208 ( .A ( ctsbuf_net_278 ) , .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) ) ; endmodule @@ -1695,13 +1699,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1718,9 +1722,9 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1752,13 +1756,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1771,11 +1775,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -1790,7 +1794,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -1809,7 +1813,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -1832,7 +1836,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -1856,50 +1860,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1928,6 +1888,50 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -2011,8 +2015,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -2032,8 +2037,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2057,6 +2060,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -2164,8 +2169,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2189,6 +2192,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -2199,15 +2204,29 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +wire copt_net_84 ; + +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_84 ) , + .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1316 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1317 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_81 ) , + .X ( copt_net_82 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_82 ) , + .X ( copt_net_83 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_83 ) , + .X ( mem_out[3] ) ) ; endmodule @@ -2218,7 +2237,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -2239,7 +2258,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -2256,13 +2275,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2275,13 +2294,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2294,11 +2313,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -2313,13 +2332,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2332,35 +2351,25 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_100 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_91 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( ccff_head[0] ) , - .X ( copt_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1314 ( .A ( copt_net_82 ) , - .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_83 ) , - .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1324 ( .A ( copt_net_85 ) , - .X ( copt_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1334 ( .A ( ropt_net_97 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1335 ( .A ( ropt_net_98 ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1336 ( .A ( copt_net_86 ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1339 ( .A ( ropt_net_96 ) , - .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( ropt_net_88 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_92 ) , + .X ( ropt_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_88 ) , + .X ( ropt_net_90 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1362 ( .A ( ropt_net_89 ) , + .X ( ropt_net_91 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1363 ( .A ( ropt_net_90 ) , + .X ( ropt_net_92 ) ) ; endmodule @@ -2382,6 +2391,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -2411,9 +2422,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_75 ) ) ; endmodule @@ -2620,8 +2628,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_59 ) ) ; endmodule @@ -2776,8 +2785,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_57 ) ) ; endmodule @@ -2892,7 +2902,7 @@ cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -2901,7 +2911,7 @@ cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -2910,7 +2920,7 @@ cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -2919,7 +2929,7 @@ cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -2928,7 +2938,7 @@ cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -2992,9 +3002,8 @@ cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { copt_net_87 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -3010,7 +3019,7 @@ cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -3026,7 +3035,7 @@ cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -3034,7 +3043,7 @@ cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -3042,7 +3051,7 @@ cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -3058,7 +3067,7 @@ cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -3101,31 +3110,32 @@ cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , - .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_W_out ) ) ; sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , - .X ( net_net_67 ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( net_net_68 ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) ) ; + .X ( ctsbuf_net_177 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) ) ; + .X ( ctsbuf_net_278 ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ropt_net_93 ) ) ; + .X ( ropt_net_87 ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ZBUF_6_f_1 ) ) ; + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( prog_clk_3_N_out ) ) ; + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( ropt_net_95 ) ) ; + .X ( prog_clk_3_S_out ) ) ; sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , .X ( clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) ) ; -sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , - .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_509_ ) ) ; sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_506_ ) ) ; + .X ( aps_rename_510_ ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , @@ -3206,43 +3216,31 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_66 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( clk_3_S_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_75 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , - .X ( clk_2_N_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , - .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , - .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , - .X ( prog_clk_2_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_509_ ) , .X ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , - .X ( copt_net_92 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_585 ( .A ( aps_rename_508_ ) , + .X ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_586 ( .A ( aps_rename_507_ ) , + .X ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_587 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1358 ( .A ( ropt_net_87 ) , .X ( prog_clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , - .X ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , - .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_177 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_278 ) , + .X ( prog_clk_0_N_out ) ) ; endmodule @@ -3253,23 +3251,23 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_55 ; +wire copt_net_60 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , - .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_60 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_60 ) , + .X ( copt_net_55 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( copt_net_55 ) , .X ( copt_net_56 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_56 ) , .X ( copt_net_57 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , .X ( copt_net_58 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , - .X ( copt_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , - .X ( copt_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_61 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1193 ( .A ( copt_net_58 ) , + .X ( copt_net_61 ) ) ; endmodule @@ -3365,17 +3363,17 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( ccff_head[0] ) , .X ( copt_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_49 ) , .X ( copt_net_50 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_50 ) , .X ( copt_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( copt_net_51 ) , .X ( copt_net_52 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_52 ) , .X ( copt_net_53 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_53 ) , .X ( copt_net_54 ) ) ; endmodule @@ -3455,10 +3453,14 @@ output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; input prog_clk_0_E_in ; -wire ropt_net_73 ; -wire ropt_net_75 ; -wire ropt_net_74 ; -wire ropt_net_72 ; +wire ropt_net_67 ; +wire ropt_net_68 ; +wire ropt_net_66 ; +wire ropt_net_65 ; +wire ropt_net_63 ; +wire ropt_net_69 ; +wire ropt_net_64 ; +wire ropt_net_62 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -3501,12 +3503,12 @@ sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , +sky130_fd_sc_hd__buf_6 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_73 ) ) ; + .X ( ropt_net_67 ) ) ; sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_75 ) ) ; + .X ( ropt_net_68 ) ) ; sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , @@ -3514,18 +3516,18 @@ sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; + .X ( ropt_net_66 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_65 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_63 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__buf_6 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; @@ -3536,7 +3538,7 @@ sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_74 ) ) ; + .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , @@ -3552,10 +3554,10 @@ sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_69 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_64 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[13] ) ) ; sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) ) ; @@ -3566,7 +3568,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_72 ) ) ; + .X ( ropt_net_62 ) ) ; sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_43__42 ( @@ -3574,14 +3576,22 @@ sky130_fd_sc_hd__buf_6 FTB_43__42 ( .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_48 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1194 ( .A ( ropt_net_62 ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1195 ( .A ( ropt_net_63 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1196 ( .A ( ropt_net_64 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1197 ( .A ( ropt_net_65 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1198 ( .A ( ropt_net_66 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1199 ( .A ( ropt_net_67 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1200 ( .A ( ropt_net_68 ) , .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1201 ( .A ( ropt_net_69 ) , + .X ( chany_bottom_out[11] ) ) ; endmodule @@ -3597,14 +3607,14 @@ wire copt_net_86 ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( copt_net_86 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_88 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_84 ) , + .X ( copt_net_83 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , + .X ( copt_net_85 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1310 ( .A ( copt_net_84 ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_86 ) , - .X ( copt_net_88 ) ) ; endmodule @@ -3620,15 +3630,14 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_61 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_64 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_61 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_61 ( .A ( BUF_net_63 ) , .Y ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_63 ) ) ; + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_64 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -3695,7 +3704,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -3984,6 +3993,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -4007,8 +4018,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -4139,7 +4148,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -4183,7 +4192,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -4199,7 +4208,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -4328,9 +4337,9 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -4347,7 +4356,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_93 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_95 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -4356,24 +4365,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( ccff_head[0] ) , + .X ( copt_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_75 ) , + .X ( copt_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_78 ) , .X ( copt_net_79 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_79 ) , .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( copt_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_82 ) , - .X ( ropt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1315 ( .A ( ropt_net_92 ) , - .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_80 ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1314 ( .A ( ropt_net_94 ) , + .X ( ropt_net_95 ) ) ; endmodule @@ -4424,7 +4431,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -4528,7 +4535,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -4707,6 +4714,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -4736,8 +4745,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -4788,8 +4795,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -4949,7 +4957,7 @@ cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -4958,7 +4966,7 @@ cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -4976,7 +4984,7 @@ cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -4985,7 +4993,7 @@ cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -5003,7 +5011,7 @@ cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -5064,7 +5072,7 @@ cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -5080,7 +5088,7 @@ cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , @@ -5096,7 +5104,7 @@ cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -5104,7 +5112,7 @@ cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -5120,7 +5128,7 @@ cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -5172,10 +5180,10 @@ cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_176 ) ) ; + .X ( ctsbuf_net_174 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , +sky130_fd_sc_hd__buf_12 FTB_20__19 ( .A ( chanx_left_in[1] ) , .X ( chanx_right_out[1] ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , .X ( chanx_right_out[2] ) ) ; @@ -5217,7 +5225,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , .X ( chanx_left_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__buf_12 FTB_41__40 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; @@ -5262,11 +5270,7 @@ sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , .HI ( optlc_net_72 ) ) ; sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , .HI ( optlc_net_73 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_74 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521203 ( .A ( ctsbuf_net_174 ) , .X ( prog_clk_0_W_out ) ) ; endmodule @@ -5280,11 +5284,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5299,9 +5303,9 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -5339,7 +5343,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -5394,7 +5398,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -5527,8 +5531,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -5552,6 +5554,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -5594,7 +5598,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -5703,8 +5707,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -5728,6 +5730,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -5770,7 +5774,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -5782,29 +5786,25 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -wire copt_net_81 ; +wire copt_net_84 ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_81 ) ) ; -sky130_fd_sc_hd__buf_4 FTB_8__7 ( .A ( copt_net_83 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_81 ) , - .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( mem_out[3] ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_84 ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_87 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , - .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_85 ) , + .X ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_84 ) , + .X ( copt_net_87 ) ) ; endmodule @@ -5821,7 +5821,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5929,7 +5929,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_79 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_103 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -5938,18 +5938,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( ccff_head[0] ) , - .X ( copt_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_74 ) , - .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_75 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , .X ( copt_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_76 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( ccff_head[0] ) , .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_78 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1323 ( .A ( copt_net_81 ) , + .X ( ropt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1324 ( .A ( ropt_net_102 ) , + .X ( ropt_net_103 ) ) ; endmodule @@ -6000,7 +6004,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -6023,8 +6027,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -6054,6 +6056,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -6439,7 +6443,6 @@ input clk_3_E_in ; output clk_3_E_out ; output clk_3_W_out ; -wire ropt_net_94 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -6499,7 +6502,7 @@ cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -6508,7 +6511,7 @@ cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -6517,7 +6520,7 @@ cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -6535,7 +6538,7 @@ cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -6553,7 +6556,7 @@ cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -6590,9 +6593,8 @@ cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_100 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -6600,7 +6602,7 @@ cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -6608,7 +6610,7 @@ cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -6616,7 +6618,7 @@ cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -6624,7 +6626,7 @@ cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -6632,7 +6634,7 @@ cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -6648,7 +6650,7 @@ cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -6696,31 +6698,30 @@ cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_173 ) ) ; + .X ( ctsbuf_net_175 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( net_net_69 ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_70 ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_71 ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( clk_3_W_out ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , @@ -6804,34 +6805,29 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) , sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , .X ( REGOUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( prog_clk_1_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , - .Y ( prog_clk_1_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_67 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_69 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_70 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_71 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( net_net_69 ) , + .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( net_net_70 ) , .X ( clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , .HI ( optlc_net_72 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_73 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_79 ( .A ( aps_rename_507_ ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_506_ ) , + .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_175 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , - .X ( SC_OUT_TOP ) ) ; endmodule @@ -6842,23 +6838,21 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_124 ; +wire copt_net_122 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_124 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_122 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_119 ) , - .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_124 ) , - .X ( copt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_118 ) , - .X ( copt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_122 ) , +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1346 ( .A ( copt_net_124 ) , .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , - .X ( copt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_120 ) , - .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( copt_net_125 ) , + .X ( copt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_126 ) , + .X ( copt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_127 ) , + .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_122 ) , + .X ( copt_net_127 ) ) ; endmodule @@ -6873,17 +6867,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_511_ ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_88 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( BUF_net_88 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_112 ( .A ( BUF_net_90 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_90 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -6963,16 +6957,13 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_85 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_85 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( BUF_net_85 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_87 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_87 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; endmodule @@ -7053,15 +7044,16 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_82 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_87 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_86 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_86 ( .A ( BUF_net_88 ) , .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_88 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_88 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -7142,16 +7134,14 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_508_ ) , - .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_84 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_81 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -7231,16 +7221,13 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_76 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( net_net_80 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_76 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_76 ( .A ( BUF_net_78 ) , .Y ( BUF_net_76 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_78 ) ) ; + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( SOC_DIR ) ) ; endmodule @@ -7320,16 +7307,19 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_73 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_507_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_73 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_73 ( .A ( BUF_net_75 ) , .Y ( BUF_net_73 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_75 ) ) ; + .TE_B ( BUF_net_77 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_77 ( .A ( BUF_net_79 ) , .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( BUF_net_78 ) , .Y ( BUF_net_107 ) ) ; endmodule @@ -7399,7 +7389,7 @@ endmodule module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_184_0 ) ; + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_211_0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7407,22 +7397,22 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_211_0 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( ZBUF_184_0 ) , .Z ( SOC_OUT ) ) ; + .TE_B ( ZBUF_211_0 ) , .Z ( SOC_OUT ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , - iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_184_0 ) ; + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -7432,7 +7422,7 @@ input [0:0] iopad_outpad ; input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; wire [0:0] EMBEDDED_IO_HD_0_en ; @@ -7442,7 +7432,7 @@ cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , - .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .ZBUF_211_0 ( ZBUF_211_0 ) ) ; cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; @@ -7452,7 +7442,7 @@ endmodule module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , ZBUF_184_0 ) ; + ccff_tail , ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -7462,7 +7452,7 @@ input [0:0] io_outpad ; input [0:0] ccff_head ; output [0:0] io_inpad ; output [0:0] ccff_tail ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , @@ -7471,7 +7461,7 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .ZBUF_211_0 ( ZBUF_211_0 ) ) ; endmodule @@ -7499,16 +7489,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_70 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_506_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_72 ) ) ; + .TE_B ( BUF_net_74 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_76 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_74 ( .A ( BUF_net_76 ) , .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -7588,13 +7579,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( net_net_69 ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__buf_8 BUFT_RR_69 ( .A ( net_net_69 ) , .X ( SOC_DIR ) ) ; + .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -7809,7 +7804,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_136 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -7818,6 +7813,20 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( ccff_head[0] ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_117 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_118 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_120 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_121 ) , + .X ( ropt_net_136 ) ) ; endmodule @@ -7945,6 +7954,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -7974,8 +7985,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -8026,9 +8035,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -8079,7 +8088,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -8131,9 +8140,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -8184,9 +8193,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_96 ) ) ; endmodule @@ -8237,9 +8246,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -8290,7 +8298,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -8408,7 +8416,7 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -8417,7 +8425,7 @@ cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -8426,7 +8434,7 @@ cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -8435,7 +8443,7 @@ cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -8444,7 +8452,7 @@ cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -8453,7 +8461,7 @@ cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -8462,7 +8470,7 @@ cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -8471,7 +8479,7 @@ cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -8480,7 +8488,7 @@ cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -8546,12 +8554,12 @@ cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_511_ } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_5_lower ) , .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , - .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; + .ZBUF_211_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , @@ -8606,10 +8614,10 @@ cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_17_lower ) , .ccff_tail ( ccff_tail ) ) ; -sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1117 ) ) ; + .X ( ctsbuf_net_1115 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -8719,15 +8727,15 @@ sky130_fd_sc_hd__buf_6 FTB_67__66 ( .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , - .HI ( optlc_net_116 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_211_inst_119 ( .A ( aps_rename_511_ ) , .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3521246 ( .A ( ctsbuf_net_1115 ) , .X ( prog_clk_0_W_out ) ) ; endmodule @@ -8788,6 +8796,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -8796,9 +8806,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_91 ) ) ; endmodule @@ -8821,9 +8828,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -8846,7 +8853,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -8858,19 +8865,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_102 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_102 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_107 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_105 ) , - .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( copt_net_102 ) , - .X ( copt_net_107 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( copt_net_99 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_102 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( mem_out[1] ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; endmodule @@ -9254,9 +9259,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; endmodule @@ -9315,9 +9320,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -9336,8 +9340,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -9391,13 +9396,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -9411,14 +9416,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_81 ) ) ; endmodule @@ -9437,7 +9441,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -9457,9 +9461,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -9478,9 +9481,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -9494,13 +9497,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -9535,13 +9538,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -9555,13 +9558,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -9970,31 +9973,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_109 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1257 ( .A ( copt_net_95 ) , + .X ( copt_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_91 ) , + .X ( copt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_93 ) , .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_96 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_100 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_98 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_99 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( copt_net_101 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( ropt_net_117 ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1275 ( .A ( copt_net_92 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1276 ( .A ( ropt_net_110 ) , + .X ( ropt_net_111 ) ) ; endmodule @@ -10266,7 +10269,7 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -10274,7 +10277,7 @@ sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -10282,7 +10285,7 @@ sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -10290,7 +10293,7 @@ sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -10316,7 +10319,7 @@ sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , @@ -10324,7 +10327,7 @@ sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -10332,7 +10335,7 @@ sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -10340,7 +10343,7 @@ sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -10364,122 +10367,122 @@ sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -10604,19 +10607,19 @@ sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -10645,14 +10648,14 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[18] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) , .X ( chany_bottom_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , - .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_87 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_88 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , + .HI ( optlc_net_90 ) ) ; endmodule @@ -10663,25 +10666,27 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_106 ; +wire copt_net_103 ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_103 ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_103 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_103 ) , .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_106 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_104 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( copt_net_105 ) , .X ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_107 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_104 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_108 ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , + .X ( copt_net_108 ) ) ; endmodule @@ -10775,7 +10780,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -10790,13 +10795,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -10815,8 +10820,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; endmodule @@ -10830,13 +10836,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -10855,9 +10862,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) ) ; endmodule @@ -10876,9 +10883,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -10968,8 +10975,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -10978,6 +10983,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -11000,8 +11008,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -11016,8 +11025,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -11026,6 +11033,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -11048,8 +11057,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_82 ) ) ; endmodule @@ -11196,8 +11206,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -11224,9 +11235,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -11242,8 +11253,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -11255,6 +11264,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -11320,9 +11331,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -11391,6 +11402,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -11408,9 +11421,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) ) ; endmodule @@ -11464,6 +11474,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -11481,9 +11493,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_69 ) ) ; endmodule @@ -11641,9 +11650,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -11682,7 +11691,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -11702,8 +11711,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -11724,6 +11731,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -11762,7 +11772,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -11802,9 +11812,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_67 ) ) ; endmodule @@ -11843,9 +11853,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_65 ) ) ; endmodule @@ -12017,8 +12027,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12060,6 +12068,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_63 ) ) ; endmodule @@ -12136,8 +12147,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -12161,6 +12170,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_61 ) ) ; endmodule @@ -12278,7 +12290,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_112 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -12287,26 +12299,6 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( ccff_head[0] ) , - .X ( copt_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_97 ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_99 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1271 ( .A ( copt_net_100 ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1272 ( .A ( ropt_net_109 ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1273 ( .A ( ropt_net_110 ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , - .X ( ropt_net_112 ) ) ; endmodule @@ -12542,7 +12534,7 @@ sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , @@ -12552,7 +12544,7 @@ sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -12570,7 +12562,7 @@ sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] , @@ -12578,7 +12570,7 @@ sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , @@ -12587,7 +12579,7 @@ sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -12613,7 +12605,7 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , @@ -12625,7 +12617,7 @@ sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -12643,7 +12635,7 @@ sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] , @@ -12651,7 +12643,7 @@ sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , @@ -12659,7 +12651,7 @@ sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -12667,7 +12659,7 @@ sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -12675,7 +12667,7 @@ sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -12683,7 +12675,7 @@ sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -12691,7 +12683,7 @@ sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , @@ -12733,7 +12725,7 @@ sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , @@ -12741,7 +12733,7 @@ sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , @@ -12749,7 +12741,7 @@ sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -12773,7 +12765,7 @@ sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -12785,28 +12777,28 @@ sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 ( .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] , chanx_left_out[13] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 ( .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , @@ -12832,31 +12824,31 @@ sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_bottom_out[15] , chany_top_out[15] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_bottom_out[17] , chany_top_out[17] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_bottom_out[18] , chany_top_out[18] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_out[19] , chany_top_out[19] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , @@ -12886,32 +12878,32 @@ sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , @@ -12941,7 +12933,7 @@ sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) ) ; @@ -12997,14 +12989,14 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , - .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , + .HI ( optlc_net_101 ) ) ; endmodule @@ -13015,19 +13007,19 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_97 ; +wire copt_net_104 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_97 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_104 ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_98 ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_102 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_104 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) ) ; endmodule @@ -13361,9 +13353,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -13377,14 +13369,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_66 ) ) ; endmodule @@ -13443,9 +13434,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -13464,9 +13455,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -13485,9 +13476,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -13501,6 +13492,27 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -13511,26 +13523,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -13546,9 +13538,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -13607,9 +13599,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -13643,13 +13635,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -13683,13 +13676,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; endmodule @@ -13708,8 +13702,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -13723,13 +13718,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) ) ; endmodule @@ -13743,13 +13739,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -13896,9 +13892,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_57 ) ) ; endmodule @@ -13913,8 +13909,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -13923,6 +13917,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -13937,8 +13933,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -13947,6 +13941,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -14045,9 +14041,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -14078,9 +14073,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_52 ) ) ; endmodule @@ -14097,8 +14092,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -14113,6 +14106,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_50 ) ) ; endmodule @@ -14143,8 +14139,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; endmodule @@ -14206,31 +14203,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_114 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_120 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( ccff_head[0] ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1251 ( .A ( copt_net_89 ) , - .X ( copt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_90 ) , - .X ( copt_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_88 ) , - .X ( copt_net_92 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( ropt_net_116 ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( copt_net_91 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_99 ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_98 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_97 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1282 ( .A ( copt_net_95 ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1283 ( .A ( ropt_net_121 ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1284 ( .A ( ropt_net_119 ) , + .X ( ropt_net_121 ) ) ; endmodule @@ -14265,9 +14262,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; endmodule @@ -14302,9 +14299,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -14322,8 +14318,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -14341,6 +14335,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_43 ) ) ; endmodule @@ -14417,7 +14414,7 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input prog_clk_0_N_in ; -wire ropt_net_104 ; +wire ropt_net_110 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -14497,7 +14494,7 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -14505,7 +14502,7 @@ sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -14513,7 +14510,7 @@ sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -14521,7 +14518,7 @@ sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -14547,7 +14544,7 @@ sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -14555,7 +14552,7 @@ sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -14563,7 +14560,7 @@ sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -14571,7 +14568,7 @@ sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -14596,25 +14593,25 @@ sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 ( chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -14639,112 +14636,112 @@ sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -14856,28 +14853,30 @@ sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[3] ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) ) ; sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[5] ) , +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_left_in[5] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , - .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , - .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_85 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_86 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[17] ) ) ; endmodule @@ -14888,27 +14887,20 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -wire copt_net_105 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_105 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_104 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_105 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_103 ) , - .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_101 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_100 ) , - .X ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_109 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( mem_out[2] ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1295 ( .A ( copt_net_108 ) , + .X ( copt_net_109 ) ) ; endmodule @@ -14926,8 +14918,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -14945,6 +14935,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -15092,7 +15084,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -15108,6 +15100,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -15116,9 +15110,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_80 ) ) ; endmodule @@ -15141,9 +15132,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -15158,8 +15149,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -15168,6 +15157,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -15310,8 +15302,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -15323,6 +15313,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -15398,9 +15390,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -15575,9 +15566,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -15596,8 +15587,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -15618,6 +15607,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) ) ; endmodule @@ -15656,7 +15648,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -15736,9 +15728,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -15757,8 +15748,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -15779,6 +15768,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -15817,8 +15809,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -15939,9 +15932,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_71 ) ) ; endmodule @@ -16090,9 +16083,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -16118,8 +16111,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -16161,6 +16152,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -16238,6 +16231,55 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -16270,7 +16312,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , endmodule -module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -16319,54 +16361,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , endmodule -module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; @@ -16374,7 +16368,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_99 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_130 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -16383,18 +16377,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_96 ) , - .X ( copt_net_94 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_97 ) , - .X ( copt_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_94 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( ccff_head[0] ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_100 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_104 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_105 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_131 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1317 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) ) ; endmodule @@ -16504,7 +16504,8 @@ input SC_IN_BOT ; output SC_OUT_BOT ; input prog_clk_0_S_in ; -wire ropt_net_115 ; +wire ropt_net_118 ; +wire ropt_net_119 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -16574,7 +16575,7 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -16587,7 +16588,7 @@ sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , @@ -16596,7 +16597,7 @@ sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -16605,7 +16606,7 @@ sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -16631,7 +16632,7 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -16642,7 +16643,7 @@ sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , @@ -16661,7 +16662,7 @@ sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , @@ -16669,7 +16670,7 @@ sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -16686,7 +16687,7 @@ sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -16694,7 +16695,7 @@ sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -16702,7 +16703,7 @@ sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -16710,7 +16711,7 @@ sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -16718,7 +16719,7 @@ sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -16726,7 +16727,7 @@ sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , @@ -16734,7 +16735,7 @@ sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , @@ -16742,7 +16743,7 @@ sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -16789,7 +16790,7 @@ sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -16801,21 +16802,21 @@ sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 ( .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] , chanx_right_out[10] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_99 ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 ( .in ( { chanx_left_out[19] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , @@ -16836,37 +16837,37 @@ sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( chanx_right_out[11] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -16901,7 +16902,7 @@ sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , @@ -16914,18 +16915,17 @@ sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_118 ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) , @@ -16936,7 +16936,7 @@ sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[7] ) , +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) , .X ( chanx_left_out[9] ) ) ; @@ -16986,22 +16986,22 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_88 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_89 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1314 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_115 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_118 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_119 ) , .X ( SC_OUT_BOT ) ) ; endmodule @@ -17013,16 +17013,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; +wire copt_net_120 ; + sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_119 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( mem_out[2] ) , - .X ( copt_net_119 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_120 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_120 ) , + .X ( mem_out[2] ) ) ; endmodule @@ -17172,8 +17173,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -17194,6 +17193,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -17232,8 +17234,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -17483,8 +17486,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -17514,6 +17515,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -17564,7 +17567,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -17616,9 +17619,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_94 ) ) ; endmodule @@ -17825,9 +17828,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_92 ) ) ; endmodule @@ -17878,9 +17881,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_90 ) ) ; endmodule @@ -17902,6 +17905,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -17931,9 +17936,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) ) ; endmodule @@ -17955,6 +17957,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -17984,8 +17988,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -18007,6 +18009,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -18036,8 +18040,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -18088,9 +18090,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) ) ; endmodule @@ -18477,9 +18479,9 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , - .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -18623,7 +18625,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_124 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_125 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -18632,26 +18634,26 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_113 ) , - .X ( copt_net_108 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_108 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_114 ) , .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_109 ) , .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_110 ) , .X ( copt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_111 ) , .X ( copt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_112 ) , .X ( copt_net_113 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_122 ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1302 ( .A ( copt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( copt_net_113 ) , .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1303 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_122 ) , .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1304 ( .A ( ropt_net_123 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1311 ( .A ( ropt_net_123 ) , .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1312 ( .A ( ropt_net_124 ) , + .X ( ropt_net_125 ) ) ; endmodule @@ -18770,9 +18772,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -18796,8 +18797,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -18833,6 +18832,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -18891,7 +18892,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -18976,6 +18977,67 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_81 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -19016,67 +19078,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_82 ) ) ; -endmodule - - module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; @@ -19097,6 +19098,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -19132,8 +19135,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -19353,7 +19354,7 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -19373,7 +19374,7 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -19383,7 +19384,7 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] , chanx_left_out[13] , chanx_right_in[15] , @@ -19393,7 +19394,7 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] , chanx_right_in[11] , chanx_left_out[14] , @@ -19413,7 +19414,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] , chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , @@ -19423,7 +19424,7 @@ sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -19488,7 +19489,7 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] , @@ -19514,7 +19515,7 @@ sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , @@ -19552,7 +19553,7 @@ sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] , @@ -19561,7 +19562,7 @@ sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , @@ -19579,7 +19580,7 @@ sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , @@ -19588,7 +19589,7 @@ sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_107 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] , chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] , @@ -19615,7 +19616,7 @@ sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 ( .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] , chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] , @@ -19633,7 +19634,7 @@ sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] , chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] , @@ -19642,7 +19643,7 @@ sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -19710,7 +19711,7 @@ sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , @@ -19718,7 +19719,7 @@ sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , @@ -19734,7 +19735,7 @@ sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , @@ -19754,8 +19755,8 @@ sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , - .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , + .HI ( optlc_net_102 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) , @@ -19862,18 +19863,20 @@ sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , .HI ( optlc_net_103 ) ) ; sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) , .HI ( optlc_net_104 ) ) ; sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) , .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_108 ) ) ; endmodule @@ -19955,20 +19958,20 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -wire copt_net_107 ; +wire copt_net_106 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_107 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) ) ; sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_106 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_107 ) , - .X ( copt_net_106 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1288 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_106 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_109 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1290 ( .A ( copt_net_110 ) , .X ( mem_out[2] ) ) ; endmodule @@ -20004,8 +20007,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -20023,6 +20024,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -20057,9 +20060,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -20232,9 +20235,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -20319,8 +20321,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -20402,8 +20405,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; endmodule @@ -20531,9 +20535,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -20573,6 +20577,30 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -20587,7 +20615,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20612,7 +20640,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20637,7 +20665,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20662,30 +20690,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; @@ -20760,6 +20764,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -20771,8 +20777,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -21010,9 +21014,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -21031,8 +21035,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21053,6 +21055,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -21071,8 +21076,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21093,6 +21096,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -21249,24 +21254,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_99 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_102 ) , .X ( copt_net_100 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_100 ) , .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_105 ) , .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( ccff_head[0] ) , .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_101 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( copt_net_104 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_131 ) , .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_132 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_132 ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( copt_net_103 ) , - .X ( ropt_net_134 ) ) ; endmodule @@ -21397,9 +21402,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -21508,6 +21512,7 @@ output prog_clk_3_N_out ; input clk_3_S_in ; output clk_3_N_out ; +wire ropt_net_119 ; wire ropt_net_118 ; wire [0:0] prog_clk ; wire prog_clk_0 ; @@ -21577,7 +21582,7 @@ sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , @@ -21586,7 +21591,7 @@ sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ; sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] , chanx_left_out[14] , left_bottom_grid_pin_3_[0] , @@ -21595,7 +21600,7 @@ sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] , @@ -21603,7 +21608,7 @@ sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -21629,7 +21634,7 @@ sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -21637,7 +21642,7 @@ sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -21645,7 +21650,7 @@ sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , SYNOPSYS_UNCONNECTED_25 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , @@ -21653,7 +21658,7 @@ sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] , @@ -21669,7 +21674,7 @@ sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] , @@ -21677,7 +21682,7 @@ sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -21719,14 +21724,14 @@ sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 ( .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] , chanx_right_out[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , @@ -21741,43 +21746,43 @@ sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( chanx_right_out[11] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -21816,7 +21821,7 @@ sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[19] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -21838,7 +21843,7 @@ sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -21871,7 +21876,7 @@ sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , @@ -21889,7 +21894,7 @@ sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_left_out[11] , left_bottom_grid_pin_7_[0] , @@ -21897,7 +21902,7 @@ sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , @@ -21915,14 +21920,14 @@ sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_95 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , @@ -21967,8 +21972,8 @@ sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[7] ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_119 ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) , @@ -21983,8 +21988,8 @@ sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) , .X ( chanx_right_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) , @@ -21993,26 +21998,28 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( Test_en_S_in ) , .Y ( BUF_net_86 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( Test_en_S_in ) , .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( prog_clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_88 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_118 ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[17] ) ) ; endmodule @@ -22023,23 +22030,21 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_79 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_79 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_79 ) , - .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_75 ) , - .X ( copt_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1240 ( .A ( copt_net_76 ) , - .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1241 ( .A ( copt_net_77 ) , - .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1242 ( .A ( copt_net_78 ) , - .X ( mem_out[1] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( copt_net_71 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( mem_out[1] ) , + .X ( copt_net_70 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_74 ) , + .X ( copt_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1237 ( .A ( copt_net_70 ) , + .X ( copt_net_72 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_72 ) , + .X ( copt_net_73 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_73 ) , + .X ( copt_net_74 ) ) ; endmodule @@ -22313,7 +22318,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -22353,7 +22358,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -22373,7 +22378,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -22413,7 +22418,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -22453,9 +22458,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_51 ) ) ; endmodule @@ -22474,9 +22479,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_58 ( .A ( BUF_net_49 ) , .Y ( out[0] ) ) ; endmodule @@ -22490,26 +22495,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -22520,6 +22505,26 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -22550,14 +22555,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) ) ; endmodule @@ -22616,9 +22620,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -22632,13 +22635,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -22711,9 +22714,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_45 ) ) ; endmodule @@ -22728,6 +22731,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -22736,9 +22741,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_46 ) ) ; endmodule @@ -22803,9 +22805,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_43 ) ) ; endmodule @@ -22822,6 +22824,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -22836,8 +22840,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -22865,29 +22867,29 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_131 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_118 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_69 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( ccff_head[0] ) , + .X ( copt_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_63 ) , + .X ( copt_net_64 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1230 ( .A ( copt_net_64 ) , + .X ( copt_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_68 ) , + .X ( copt_net_66 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_65 ) , + .X ( copt_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_67 ) , .X ( copt_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_71 ) , - .X ( copt_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_73 ) , - .X ( copt_net_70 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_70 ) , - .X ( copt_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( ccff_head[0] ) , - .X ( copt_net_72 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_72 ) , - .X ( copt_net_73 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1292 ( .A ( ropt_net_132 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1293 ( .A ( copt_net_68 ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1281 ( .A ( copt_net_66 ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1282 ( .A ( ropt_net_117 ) , + .X ( ropt_net_118 ) ) ; endmodule @@ -22990,8 +22992,8 @@ input SC_IN_TOP ; output SC_OUT_BOT ; input prog_clk_0_E_in ; -wire ropt_net_95 ; -wire ropt_net_96 ; +wire ropt_net_88 ; +wire ropt_net_87 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -23051,7 +23053,7 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , @@ -23059,7 +23061,7 @@ sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -23076,7 +23078,7 @@ sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -23084,7 +23086,7 @@ sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -23100,13 +23102,13 @@ sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 ( chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -23121,92 +23123,92 @@ sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -23306,20 +23308,20 @@ sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chanx_right_in[4] ) , .X ( chany_bottom_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) , .X ( chany_bottom_out[13] ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[8] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) ) ; sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_96 ) ) ; + .X ( ropt_net_88 ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) , @@ -23328,18 +23330,18 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) , .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_87 ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_65 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , - .HI ( optlc_net_66 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , - .HI ( optlc_net_67 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1257 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_96 ) , +sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , + .HI ( optlc_net_60 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , + .HI ( optlc_net_61 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , + .HI ( optlc_net_62 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1252 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1253 ( .A ( ropt_net_88 ) , .X ( chany_bottom_out[7] ) ) ; endmodule @@ -23469,9 +23471,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; endmodule @@ -23485,13 +23487,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -23510,9 +23512,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_107 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -23531,9 +23533,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -23552,9 +23554,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_91 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -23565,25 +23567,24 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_125 ; - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_125 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_125 ) , - .X ( copt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_120 ) , - .X ( copt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_121 ) , - .X ( copt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_122 ) , - .X ( copt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_123 ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( copt_net_129 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( mem_out[1] ) , .X ( copt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_124 ) , - .X ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( copt_net_124 ) , + .X ( copt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_125 ) , + .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_126 ) , + .X ( copt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_127 ) , + .X ( copt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_128 ) , + .X ( copt_net_129 ) ) ; endmodule @@ -23666,9 +23667,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -23691,8 +23692,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -23707,6 +23709,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -23715,8 +23719,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -23739,9 +23741,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -23855,9 +23857,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_81 ) ) ; endmodule @@ -23896,9 +23898,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) ) ; endmodule @@ -23917,6 +23919,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -23937,8 +23941,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -24084,9 +24086,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_77 ) ) ; endmodule @@ -24113,9 +24115,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_106 ) ) ; endmodule @@ -24170,9 +24172,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -24199,9 +24201,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_71 ) ) ; endmodule @@ -24217,8 +24219,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -24230,6 +24230,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -24256,7 +24259,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -24373,9 +24376,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -24456,6 +24459,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -24470,9 +24475,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_67 ) ) ; endmodule @@ -24503,9 +24505,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -24618,31 +24619,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_129 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_133 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_115 ) , - .X ( copt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_114 ) , - .X ( copt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_119 ) , - .X ( copt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_116 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_120 ) , .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_118 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_121 ) , .X ( copt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1289 ( .A ( copt_net_117 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1290 ( .A ( ropt_net_127 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1291 ( .A ( ropt_net_128 ) , - .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_123 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( ccff_head[0] ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1299 ( .A ( copt_net_118 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( ropt_net_131 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) ) ; endmodule @@ -24768,8 +24769,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -24787,6 +24786,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -24821,8 +24822,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -24857,9 +24859,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -24877,6 +24878,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -24894,8 +24897,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -25002,21 +25003,21 @@ sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , @@ -25024,28 +25025,28 @@ sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -25086,35 +25087,35 @@ sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_top_out[9] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -25146,49 +25147,49 @@ sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_top_out[11] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_bottom_out[9] , right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 ( .in ( { chany_bottom_out[13] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 ( .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] , chany_top_out[19] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -25232,7 +25233,7 @@ sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[6] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -25241,7 +25242,7 @@ sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -25250,7 +25251,7 @@ sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , @@ -25271,29 +25272,29 @@ sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 ( chany_top_out[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 ( .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 ( .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 ( .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -25322,32 +25323,32 @@ sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , @@ -25434,14 +25435,16 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_93 ) , + .HI ( optlc_net_117 ) ) ; endmodule @@ -25494,9 +25497,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -25603,8 +25606,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -25619,6 +25620,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -25723,9 +25727,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -25736,14 +25740,14 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; +wire copt_net_92 ; + sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_91 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1251 ( .A ( mem_out[1] ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_87 ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_92 ) , .X ( copt_net_88 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_88 ) , .X ( copt_net_89 ) ) ; @@ -25751,6 +25755,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_89 ) , .X ( copt_net_90 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_90 ) , .X ( copt_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1256 ( .A ( copt_net_91 ) , + .X ( mem_out[1] ) ) ; endmodule @@ -26001,27 +26007,27 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_137 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1244 ( .A ( ccff_head[0] ) , - .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( copt_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( ccff_head[0] ) , .X ( copt_net_81 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1246 ( .A ( copt_net_85 ) , .X ( copt_net_82 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1247 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1249 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( copt_net_84 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1280 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( copt_net_82 ) , + .X ( copt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( copt_net_84 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1301 ( .A ( ropt_net_136 ) , + .X ( ropt_net_137 ) ) ; endmodule @@ -26035,14 +26041,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_69 ) ) ; endmodule @@ -26061,9 +26066,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -26082,9 +26087,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -26103,9 +26108,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -26124,9 +26129,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -26145,9 +26150,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) ) ; endmodule @@ -26186,9 +26191,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_58 ) ) ; endmodule @@ -26207,9 +26212,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_55 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_56 ) ) ; endmodule @@ -26228,9 +26233,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_53 ( .A ( BUF_net_54 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_54 ) ) ; endmodule @@ -26249,9 +26254,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_52 ) ) ; endmodule @@ -26270,9 +26275,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_48 ( .A ( BUF_net_49 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_50 ) ) ; endmodule @@ -26291,9 +26296,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_47 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_48 ) ) ; endmodule @@ -26312,9 +26317,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_45 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_46 ) ) ; endmodule @@ -26353,7 +26358,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -26373,8 +26378,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; endmodule @@ -26424,6 +26430,7 @@ output [0:19] chanx_right_out ; output [0:0] ccff_tail ; input prog_clk_0_E_in ; +wire ropt_net_107 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -26480,92 +26487,92 @@ sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -26661,7 +26668,7 @@ sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , @@ -26669,7 +26676,7 @@ sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , @@ -26687,7 +26694,7 @@ sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , @@ -26695,7 +26702,7 @@ sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -26711,13 +26718,13 @@ sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 ( right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -26744,8 +26751,8 @@ sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) , .X ( chany_top_out[7] ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) , .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_107 ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) , @@ -26762,14 +26769,16 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , +sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , .HI ( optlc_net_79 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , + .HI ( optlc_net_80 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[9] ) ) ; endmodule @@ -26782,21 +26791,21 @@ output [0:1] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( copt_net_165 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1947 ( .A ( copt_net_162 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1943 ( .A ( mem_out[1] ) , .X ( copt_net_160 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1948 ( .A ( copt_net_160 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1944 ( .A ( copt_net_160 ) , .X ( copt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1949 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1945 ( .A ( copt_net_161 ) , .X ( copt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1950 ( .A ( copt_net_161 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1946 ( .A ( copt_net_162 ) , .X ( copt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1951 ( .A ( copt_net_163 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1947 ( .A ( copt_net_163 ) , .X ( copt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1952 ( .A ( copt_net_164 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1948 ( .A ( copt_net_164 ) , .X ( copt_net_165 ) ) ; endmodule @@ -26808,7 +26817,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -26825,7 +26834,7 @@ output [0:1] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26893,8 +26902,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( p_abuf0 ) , .Y ( BUF_net_121 ) ) ; +sky130_fd_sc_hd__buf_1 BUFT_RR_119 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; endmodule @@ -26913,8 +26921,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( p_abuf0 ) , .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( p_abuf0 ) , .Y ( BUF_net_118 ) ) ; endmodule @@ -26930,10 +26938,10 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , .Q ( net_net_73 ) ) ; sky130_fd_sc_hd__buf_8 BUFT_RR_73 ( .A ( copt_net_168 ) , .X ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1955 ( .A ( copt_net_169 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1950 ( .A ( net_net_73 ) , + .X ( copt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1951 ( .A ( copt_net_167 ) , .X ( copt_net_168 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1956 ( .A ( net_net_73 ) , - .X ( copt_net_169 ) ) ; endmodule @@ -27294,10 +27302,10 @@ grid_clb_mux_tree_size2_mem_31 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , grid_clb_mux_tree_size2_mem mem_ff_1_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; -sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( ropt_net_170 ) , .X ( fabric_reg_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1959 ( .A ( fabric_sc_out[0] ) , - .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1954 ( .A ( fabric_sc_out[0] ) , + .X ( ropt_net_170 ) ) ; endmodule @@ -27389,34 +27397,34 @@ sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -27437,10 +27445,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_117 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_116 ) ) ; endmodule @@ -27460,10 +27468,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_113 ) ) ; endmodule @@ -27510,18 +27518,18 @@ sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -27710,13 +27718,13 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -27739,7 +27747,7 @@ grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; @@ -27749,7 +27757,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -27764,7 +27772,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -27784,7 +27791,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -27815,7 +27822,7 @@ grid_clb_mux_tree_size2_27 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_38 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -27823,7 +27830,7 @@ grid_clb_mux_tree_size2_38 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_25 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -27846,7 +27853,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; + fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -27861,7 +27868,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , @@ -27869,7 +27875,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; endmodule @@ -27933,81 +27939,81 @@ sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_515_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_110 ) ) ; endmodule module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_514_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -28054,18 +28060,18 @@ sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -28254,13 +28260,13 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -28283,7 +28289,7 @@ grid_clb_mux_tree_size2_20 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_20 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; @@ -28293,7 +28299,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -28307,7 +28313,7 @@ output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -28327,7 +28333,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -28344,21 +28350,21 @@ grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_37 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -28366,7 +28372,7 @@ grid_clb_mux_tree_size2_37 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -28389,7 +28395,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p3 ) ; + fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -28403,7 +28409,7 @@ output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p3 ; +input p0 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , @@ -28411,7 +28417,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; endmodule @@ -28508,48 +28514,48 @@ endmodule module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_513_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_105 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_104 ) ) ; endmodule module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_512_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -28835,7 +28841,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p2 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -28850,7 +28856,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p2 ; -input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -28887,14 +28892,14 @@ grid_clb_mux_tree_size2_17 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_18 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_19 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -28932,7 +28937,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p2 , p3 ) ; + fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -28947,7 +28952,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p2 ; -input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , @@ -28955,7 +28959,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; endmodule @@ -29035,18 +29039,18 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -29067,33 +29071,33 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_511_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_98 ) ) ; endmodule module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , p_abuf0 , - p2 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_95 ) ) ; endmodule @@ -29140,18 +29144,18 @@ sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -29340,13 +29344,13 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -29369,7 +29373,7 @@ grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_12 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; @@ -29379,7 +29383,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -29393,6 +29397,7 @@ output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -29413,7 +29418,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -29430,7 +29435,7 @@ grid_clb_mux_tree_size2_13 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_14 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -29444,7 +29449,7 @@ grid_clb_mux_tree_size2_15 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -29475,7 +29480,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; + fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -29489,6 +29494,7 @@ output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -29497,7 +29503,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; endmodule @@ -29561,18 +29567,18 @@ sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -29609,10 +29615,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_509_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_92 ) ) ; endmodule @@ -29631,10 +29637,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -29681,18 +29687,18 @@ sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -29881,13 +29887,13 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -29910,7 +29916,7 @@ grid_clb_mux_tree_size2_8 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_8 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; @@ -29920,7 +29926,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fabric_in ; @@ -29935,7 +29941,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -29955,7 +29960,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -29994,7 +29999,7 @@ grid_clb_mux_tree_size2_34 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ; + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -30017,7 +30022,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ; + fle_reg_out , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:3] fle_in ; @@ -30032,7 +30037,6 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , @@ -30040,7 +30044,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; endmodule @@ -30104,18 +30108,18 @@ sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_33 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_33 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -30149,9 +30153,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( p_abuf0 ) , .Y ( BUF_net_87 ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -30168,9 +30175,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( out[0] ) , .Y ( BUF_net_85 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( p_abuf0 ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf0 ) , .Y ( BUF_net_83 ) ) ; endmodule @@ -30530,7 +30537,7 @@ grid_clb_mux_tree_size2_33 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_3_out ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_5 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -30685,12 +30692,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_82 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_82 ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( out[0] ) , .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( p_abuf0 ) ) ; endmodule @@ -30707,9 +30711,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( p_abuf0 ) , .Y ( BUF_net_77 ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_78 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -30779,7 +30786,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_167 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_159 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -30814,18 +30821,18 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1942 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1937 ( .A ( copt_net_156 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1938 ( .A ( copt_net_158 ) , .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1943 ( .A ( copt_net_155 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1939 ( .A ( copt_net_157 ) , .X ( copt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1944 ( .A ( copt_net_159 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1940 ( .A ( copt_net_155 ) , .X ( copt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1945 ( .A ( copt_net_157 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1941 ( .A ( ccff_head[0] ) , .X ( copt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1946 ( .A ( copt_net_156 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1942 ( .A ( copt_net_154 ) , .X ( copt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1954 ( .A ( copt_net_158 ) , - .X ( copt_net_167 ) ) ; endmodule @@ -31136,7 +31143,7 @@ module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clb_I0 , clb_reg_out , clb_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p0 , - p1 , p2 , p3 , p4 ) ; + p1 , p2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:2] clb_I0 ; @@ -31183,7 +31190,6 @@ input p0 ; input p1 ; input p2 ; input p3 ; -input p4 ; wire [0:0] direct_interc_29_out ; wire [0:0] direct_interc_36_out ; @@ -31240,7 +31246,7 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_reg_out ( direct_interc_43_out ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p_abuf0 ( p_abuf4 ) , .p_abuf1 ( p_abuf5 ) , .p0 ( p0 ) , .p2 ( p3 ) ) ; + .p_abuf0 ( p_abuf4 ) , .p_abuf1 ( p_abuf5 ) , .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3[2] , clb_I3i[0] } ) , @@ -31252,7 +31258,7 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .fle_reg_out ( direct_interc_50_out ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p_abuf0 ( p_abuf6 ) , .p_abuf1 ( p_abuf7 ) , .p2 ( p3 ) ) ; + .p_abuf0 ( p_abuf6 ) , .p_abuf1 ( p_abuf7 ) , .p0 ( p0 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4[2] , clb_I4i[0] } ) , @@ -31264,7 +31270,7 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_reg_out ( direct_interc_57_out ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf8 ) , .p_abuf1 ( p_abuf9 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf8 ) , .p_abuf1 ( p_abuf9 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5[2] , clb_I5i[0] } ) , @@ -31276,7 +31282,7 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_reg_out ( direct_interc_64_out ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p_abuf0 ( p_abuf10 ) , .p_abuf1 ( p_abuf11 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf10 ) , .p_abuf1 ( p_abuf11 ) , .p0 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6[2] , clb_I6i[0] } ) , @@ -31288,7 +31294,7 @@ grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle .fle_reg_out ( direct_interc_71_out ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p_abuf0 ( p_abuf12 ) , .p_abuf1 ( p_abuf13 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf12 ) , .p_abuf1 ( p_abuf13 ) , .p0 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7[2] , clb_I7i[0] } ) , @@ -31437,8 +31443,9 @@ output prog_clk_0_N_out ; input clk_0_N_in ; input clk_0_S_in ; -wire p_abuf0 ; -wire p_abuf3 ; +wire p_abuf2 ; +wire p_abuf8 ; +wire p_abuf12 ; wire prog_clk_0 ; wire [0:0] prog_clk ; wire [0:0] clk ; @@ -31486,56 +31493,58 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_reg_in ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_520_ , top_width_0_height_0__pin_35_lower[0] , - top_width_0_height_0__pin_36_lower[0] , aps_rename_523_ , - aps_rename_524_ , aps_rename_525_ , aps_rename_526_ , - aps_rename_527_ , aps_rename_528_ , aps_rename_529_ , + .clb_O ( { aps_rename_520_ , aps_rename_521_ , aps_rename_522_ , + top_width_0_height_0__pin_37_lower[0] , aps_rename_524_ , + aps_rename_525_ , aps_rename_526_ , aps_rename_527_ , + aps_rename_528_ , right_width_0_height_0__pin_43_lower[0] , aps_rename_530_ , aps_rename_531_ , aps_rename_532_ , - aps_rename_533_ , aps_rename_534_ , aps_rename_535_ } ) , + right_width_0_height_0__pin_47_lower[0] , aps_rename_534_ , + aps_rename_535_ } ) , .clb_reg_out ( bottom_width_0_height_0__pin_50_ ) , .clb_sc_out ( { SC_OUT_BOT } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , + .ccff_tail ( ccff_tail ) , + .p_abuf0 ( top_width_0_height_0__pin_35_lower[0] ) , .p_abuf1 ( top_width_0_height_0__pin_34_lower[0] ) , - .p_abuf2 ( top_width_0_height_0__pin_37_lower[0] ) , - .p_abuf3 ( p_abuf3 ) , + .p_abuf2 ( p_abuf2 ) , + .p_abuf3 ( top_width_0_height_0__pin_36_lower[0] ) , .p_abuf4 ( top_width_0_height_0__pin_39_lower[0] ) , .p_abuf5 ( top_width_0_height_0__pin_38_lower[0] ) , .p_abuf6 ( top_width_0_height_0__pin_41_lower[0] ) , .p_abuf7 ( top_width_0_height_0__pin_40_lower[0] ) , - .p_abuf8 ( right_width_0_height_0__pin_43_lower[0] ) , + .p_abuf8 ( p_abuf8 ) , .p_abuf9 ( right_width_0_height_0__pin_42_lower[0] ) , .p_abuf10 ( right_width_0_height_0__pin_45_lower[0] ) , .p_abuf11 ( right_width_0_height_0__pin_44_lower[0] ) , - .p_abuf12 ( right_width_0_height_0__pin_47_lower[0] ) , + .p_abuf12 ( p_abuf12 ) , .p_abuf13 ( right_width_0_height_0__pin_46_lower[0] ) , .p_abuf14 ( right_width_0_height_0__pin_49_lower[0] ) , .p_abuf15 ( right_width_0_height_0__pin_48_lower[0] ) , .p0 ( optlc_net_146 ) , .p1 ( optlc_net_147 ) , .p2 ( optlc_net_148 ) , - .p3 ( optlc_net_149 ) , .p4 ( optlc_net_150 ) ) ; + .p3 ( optlc_net_149 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) ) ; -sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , - .X ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , .X ( aps_rename_536_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( Test_en_E_out ) ) ; sky130_fd_sc_hd__buf_12 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1151 ) ) ; + .X ( ctsbuf_net_1150 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2152 ) ) ; + .X ( ctsbuf_net_2151 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3153 ) ) ; + .X ( ctsbuf_net_3152 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4154 ) ) ; + .X ( ctsbuf_net_4153 ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( aps_rename_520_ ) , .X ( top_width_0_height_0__pin_34_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( p_abuf0 ) , +sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( aps_rename_521_ ) , .X ( top_width_0_height_0__pin_35_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( p_abuf3 ) , +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( aps_rename_522_ ) , .X ( top_width_0_height_0__pin_36_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( aps_rename_523_ ) , +sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( p_abuf2 ) , .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( aps_rename_524_ ) , .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; @@ -31547,7 +31556,7 @@ sky130_fd_sc_hd__buf_6 FTB_64__63 ( .A ( aps_rename_527_ ) , .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_528_ ) , .X ( right_width_0_height_0__pin_42_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_529_ ) , +sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( p_abuf8 ) , .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_530_ ) , .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; @@ -31555,13 +31564,17 @@ sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_531_ ) , .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_532_ ) , .X ( right_width_0_height_0__pin_46_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_533_ ) , +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( p_abuf12 ) , .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_534_ ) , .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_535_ ) , .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( SC_OUT_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , + .Y ( Test_en_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( aps_rename_536_ ) , + .Y ( BUF_net_121 ) ) ; sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_146 ) ) ; sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , @@ -31570,17 +31583,13 @@ sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_148 ) ) ; sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_150 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_133 ( .A ( aps_rename_536_ ) , - .X ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3901298 ( .A ( ctsbuf_net_1151 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3901295 ( .A ( ctsbuf_net_1150 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3951303 ( .A ( ctsbuf_net_2152 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3951300 ( .A ( ctsbuf_net_2151 ) , .X ( prog_clk_0_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4001308 ( .A ( ctsbuf_net_3153 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4001305 ( .A ( ctsbuf_net_3152 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4051313 ( .A ( ctsbuf_net_4154 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4051310 ( .A ( ctsbuf_net_4153 ) , .X ( prog_clk_0_N_out ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv b/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv index 04f192d..62f5847 100644 --- a/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv +++ b/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv @@ -1,18 +1,18 @@ | Module | Util| Area| Sites| Insts| Std_Cells |--------------------|----------|-----------------|-------|-------|------- -|fpga_core_uut/sb_0__0_ | 31.45 | 8728.371200 | 6976 | 1 | 868 -|fpga_core_uut/sb_0__11_ | 47.54 | 9449.062400 | 7552 | 11 | 945 -|fpga_core_uut/sb_0__12_ | 31.62 | 8728.371200 | 6976 | 1 | 865 -|fpga_core_uut/sb_11__0_ | 47.53 | 10970.521600 | 8768 | 11 | 1033 -|fpga_core_uut/sb_11__11_ | 64.3 | 11691.212800 | 9344 | 121 | 999 -|fpga_core_uut/sb_11__12_ | 47.15 | 10970.521600 | 8768 | 11 | 1021 -|fpga_core_uut/sb_12__0_ | 42.63 | 8728.371200 | 6976 | 1 | 827 -|fpga_core_uut/sb_12__11_ | 54.85 | 9449.062400 | 7552 | 11 | 931 -|fpga_core_uut/sb_12__12_ | 43.81 | 8728.371200 | 6976 | 1 | 823 -|fpga_core_uut/cbx_12__0_ | 63.67 | 5765.529600 | 4608 | 12 | 558 -|fpga_core_uut/cbx_12__11_ | 78.43 | 5765.529600 | 4608 | 132 | 372 -|fpga_core_uut/cbx_12__12_ | 77.47 | 5765.529600 | 4608 | 12 | 366 -|fpga_core_uut/cby_0__12_ | 20.51 | 5044.838400 | 4032 | 12 | 556 -|fpga_core_uut/cby_11__12_ | 82.22 | 5044.838400 | 4032 | 132 | 291 -|fpga_core_uut/cby_12__12_ | 83.28 | 5044.838400 | 4032 | 12 | 267 -|fpga_core_uut/grid_clb_12__12_ | 77.94 | 11531.059200 | 9216 | 144 | 597 +|fpga_core_uut/sb_0__0_ | 31.64 | 8728.371200 | 6976 | 1 | 1059 +|fpga_core_uut/sb_0__11_ | 47.66 | 9449.062400 | 7552 | 11 | 1157 +|fpga_core_uut/sb_0__12_ | 31.42 | 8728.371200 | 6976 | 1 | 1044 +|fpga_core_uut/sb_11__0_ | 47.66 | 10970.521600 | 8768 | 11 | 1212 +|fpga_core_uut/sb_11__11_ | 64.33 | 11691.212800 | 9344 | 121 | 1170 +|fpga_core_uut/sb_11__12_ | 47.16 | 10970.521600 | 8768 | 11 | 1241 +|fpga_core_uut/sb_12__0_ | 42.82 | 8728.371200 | 6976 | 1 | 1038 +|fpga_core_uut/sb_12__11_ | 54.48 | 9449.062400 | 7552 | 11 | 1156 +|fpga_core_uut/sb_12__12_ | 43.74 | 8728.371200 | 6976 | 1 | 1042 +|fpga_core_uut/cbx_12__0_ | 64.32 | 5765.529600 | 4608 | 12 | 610 +|fpga_core_uut/cbx_12__11_ | 77.45 | 5765.529600 | 4608 | 132 | 481 +|fpga_core_uut/cbx_12__12_ | 77.65 | 5765.529600 | 4608 | 12 | 456 +|fpga_core_uut/cby_0__12_ | 21.25 | 5044.838400 | 4032 | 12 | 671 +|fpga_core_uut/cby_11__12_ | 83.95 | 5044.838400 | 4032 | 132 | 385 +|fpga_core_uut/cby_12__12_ | 86.76 | 5044.838400 | 4032 | 12 | 279 +|fpga_core_uut/grid_clb_12__12_ | 78.04 | 11531.059200 | 9216 | 144 | 819 diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv b/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv index 6160f4f..58b026a 100644 --- a/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv +++ b/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv @@ -1,35 +1,33 @@ Ref Name Total Area Utilization_% Instance Count ---------------------------------------------------------------------------------------------------- - sky130_fd_sc_hd__dfxtp_4 1330730.025600 12.95 55977 + sky130_fd_sc_hd__dfxtp_4 1434260.569600 13.96 60332 sky130_fd_sc_hd__mux2_1 1314450.662400 12.79 116728 - sky130_fd_sc_hd__buf_8 304882.406400 2.97 20306 - sky130_fd_sc_hd__dfxtp_1 237007.308800 2.31 11839 - sky130_fd_sc_hd__buf_6 156502.598400 1.52 13898 - sky130_fd_sc_hd__dlygate4sd3_1 71628.697600 0.70 7156 - sky130_fd_sc_hd__buf_1 71340.921600 0.69 19006 + sky130_fd_sc_hd__buf_8 305948.428800 2.98 20377 + sky130_fd_sc_hd__buf_6 155140.041600 1.51 13777 + sky130_fd_sc_hd__dfxtp_1 152225.996800 1.48 7604 + sky130_fd_sc_hd__buf_1 72470.755200 0.71 19307 + sky130_fd_sc_hd__dlygate4sd3_1 71979.033600 0.70 7191 sky130_fd_sc_hd__sdfxtp_1 60538.060800 0.59 2304 - sky130_fd_sc_hd__inv_8 44953.113600 0.44 3992 - sky130_fd_sc_hd__bufbuf_16 43331.558400 0.42 1332 - sky130_fd_sc_hd__inv_1 40520.112000 0.39 10795 - sky130_fd_sc_hd__conb_1 23561.347200 0.23 6277 - sky130_fd_sc_hd__buf_4 10089.676800 0.10 1344 + sky130_fd_sc_hd__inv_8 50211.907200 0.49 4459 + sky130_fd_sc_hd__inv_1 41969.001600 0.41 11181 + sky130_fd_sc_hd__bufbuf_16 34743.321600 0.34 1068 + sky130_fd_sc_hd__conb_1 22439.020800 0.22 5978 sky130_fd_sc_hd__mux2_8 7567.257600 0.07 288 sky130_fd_sc_hd__or2_0 7206.912000 0.07 1152 + sky130_fd_sc_hd__buf_12 6005.760000 0.06 300 + sky130_fd_sc_hd__buf_4 5945.702400 0.06 792 sky130_fd_sc_hd__ebufn_4 5758.022400 0.06 354 - sky130_fd_sc_hd__buf_12 5525.299200 0.05 276 - sky130_fd_sc_hd__inv_6 4195.273600 0.04 479 + sky130_fd_sc_hd__buf_16 3936.275200 0.04 143 sky130_fd_sc_hd__clkbuf_1 3828.672000 0.04 1020 - sky130_fd_sc_hd__dfxtp_2 3062.937600 0.03 144 - sky130_fd_sc_hd__bufbuf_8 2477.376000 0.02 132 - sky130_fd_sc_hd__buf_2 2342.246400 0.02 468 - sky130_fd_sc_hd__inv_2 2207.116800 0.02 588 - sky130_fd_sc_hd__dlygate4sd2_1 1366.310400 0.01 156 - sky130_fd_sc_hd__nand2b_1 825.792000 0.01 132 + sky130_fd_sc_hd__inv_6 3275.641600 0.03 374 + sky130_fd_sc_hd__inv_2 1621.555200 0.02 432 + sky130_fd_sc_hd__buf_2 1441.382400 0.01 288 + sky130_fd_sc_hd__dlygate4sd2_1 1269.968000 0.01 145 + sky130_fd_sc_hd__nand2b_1 900.864000 0.01 144 sky130_fd_sc_hd__inv_4 675.648000 0.01 108 - sky130_fd_sc_hd__buf_16 330.316800 0.00 12 - sky130_fd_sc_hd__dlygate4sd1_1 324.060800 0.00 37 + sky130_fd_sc_hd__dfxtp_2 510.489600 0.00 24 + sky130_fd_sc_hd__dlygate4sd1_1 297.785600 0.00 34 sky130_fd_sc_hd__clkbuf_8 165.158400 0.00 12 - sky130_fd_sc_hd__or2b_4 135.129600 0.00 12 FPGA_BBOX_AREA 5973088.6656 CORE_BBOX_AREA 10276128.1216 FPGA_BBOX_UTIL 58.1258679818 diff --git a/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt b/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt index 8bb06fd..51eed0a 100644 --- a/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt +++ b/FPGA1212_SOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt @@ -6,7 +6,7 @@ Report : clock timing -setup Design : fpga_top Version: P-2019.03-SP4 -Date : Mon Dec 7 11:48:29 2020 +Date : Mon Dec 14 01:06:09 2020 **************************************** Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) @@ -16,7 +16,7 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) --- Latency --- Clock Pin Trans Source Offset Network Total Corner --------------------------------------------------------------------------------------------------- - fpga_core_uut/sb_11__1_/mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_/CLK 4.283 0.000 -- 9.187 9.187 rp-+ nominal + fpga_core_uut/sb_2__11_/mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_/CLK 4.320 0.000 -- 9.569 9.569 rp-+ nominal --------------------------------------------------------------------------------------------------- Mode: full_chip @@ -25,7 +25,7 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) --- Latency --- Clock Pin Trans Source Offset Network Total Corner --------------------------------------------------------------------------------------------------- - fpga_core_uut/grid_clb_11__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.625 0.000 -- 6.546 6.546 rp-+ nominal + fpga_core_uut/grid_clb_11__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.723 0.000 -- 7.580 7.580 rp-+ nominal --------------------------------------------------------------------------------------------------- **************************************** Report : clock timing @@ -34,7 +34,7 @@ Report : clock timing -setup Design : fpga_top Version: P-2019.03-SP4 -Date : Mon Dec 7 11:48:29 2020 +Date : Mon Dec 14 01:06:09 2020 **************************************** Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) @@ -43,8 +43,8 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) Clock Pin Latency Skew Corner --------------------------------------------------------------------------------------------------- - fpga_core_uut/sb_10__5_/mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_/CLK 7.995 rp-+ nominal - fpga_core_uut/cbx_10__5_/mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_/CLK 5.257 2.737 rp-+ nominal + fpga_core_uut/sb_0__10_/mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_/CLK 8.678 rp-+ nominal + fpga_core_uut/cby_0__10_/mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_/CLK 5.853 2.826 rp-+ nominal --------------------------------------------------------------------------------------------------- @@ -53,8 +53,8 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) Clock Pin Latency Skew Corner --------------------------------------------------------------------------------------------------- - fpga_core_uut/grid_clb_8__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 5.962 rp-+ nominal - fpga_core_uut/grid_clb_8__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 5.241 0.721 rp-+ nominal + fpga_core_uut/grid_clb_8__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 6.870 rp-+ nominal + fpga_core_uut/grid_clb_8__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 5.991 0.879 rp-+ nominal --------------------------------------------------------------------------------------------------- Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) @@ -63,7 +63,7 @@ Report : global timing -format { narrow } Design : fpga_top Version: P-2019.03-SP4 -Date : Mon Dec 7 11:48:31 2020 +Date : Mon Dec 14 01:06:10 2020 **************************************** No setup violations found. diff --git a/FPGA1212_SOFA_HD_PNR/modules/gds/cbx_1__0__icv_in_design.gds.gz b/FPGA1212_SOFA_HD_PNR/modules/gds/cbx_1__0__icv_in_design.gds.gz index 006e420..8ec049a 100644 Binary files a/FPGA1212_SOFA_HD_PNR/modules/gds/cbx_1__0__icv_in_design.gds.gz and b/FPGA1212_SOFA_HD_PNR/modules/gds/cbx_1__0__icv_in_design.gds.gz differ diff --git a/FPGA1212_SOFA_HD_PNR/modules/gds/cbx_1__1__icv_in_design.gds.gz b/FPGA1212_SOFA_HD_PNR/modules/gds/cbx_1__1__icv_in_design.gds.gz index 64f152f..d321cf3 100644 Binary files a/FPGA1212_SOFA_HD_PNR/modules/gds/cbx_1__1__icv_in_design.gds.gz and b/FPGA1212_SOFA_HD_PNR/modules/gds/cbx_1__1__icv_in_design.gds.gz differ diff --git a/FPGA1212_SOFA_HD_PNR/modules/gds/cbx_1__2__icv_in_design.gds.gz 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b/FPGA1212_SOFA_HD_PNR/modules/gds/sb_2__2__icv_in_design.gds.gz index e58737a..f6eab55 100644 Binary files a/FPGA1212_SOFA_HD_PNR/modules/gds/sb_2__2__icv_in_design.gds.gz and b/FPGA1212_SOFA_HD_PNR/modules/gds/sb_2__2__icv_in_design.gds.gz differ diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__0__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__0__icv_in_design.lef index 4418009..f808d24 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__0__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__0__icv_in_design.lef @@ -1678,14 +1678,20 @@ MACRO cbx_1__0_ LAYER met3 ; POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ; POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ; - POLYGON 11.88 18.17 11.88 17.87 0.65 17.87 0.65 18.15 1.2 18.15 1.2 18.17 ; - POLYGON 65.04 15.45 65.04 15.43 65.59 15.43 65.59 15.15 56.2 15.15 56.2 15.45 ; + POLYGON 65.59 48.09 65.59 47.81 65.04 47.81 65.04 47.79 51.14 47.79 51.14 48.09 ; + POLYGON 16.02 18.17 16.02 17.87 0.65 17.87 0.65 18.15 1.2 18.15 1.2 18.17 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; POLYGON 65.84 86.64 65.84 83.85 65.04 83.85 65.04 82.75 65.84 82.75 65.84 81.81 65.04 81.81 65.04 80.71 65.84 80.71 65.84 80.45 65.04 80.45 65.04 79.35 65.84 79.35 65.84 79.09 65.04 79.09 65.04 77.99 65.84 77.99 65.84 77.73 65.04 77.73 65.04 76.63 65.84 76.63 65.84 75.69 65.04 75.69 65.04 74.59 65.84 74.59 65.84 74.33 65.04 74.33 65.04 73.23 65.84 73.23 65.84 72.97 65.04 72.97 65.04 71.87 65.84 71.87 65.84 71.61 65.04 71.61 65.04 70.51 65.84 70.51 65.84 70.25 65.04 70.25 65.04 69.15 65.84 69.15 65.84 68.89 65.04 68.89 65.04 67.79 65.84 67.79 65.84 67.53 65.04 67.53 65.04 66.43 65.84 66.43 65.84 65.49 65.04 65.49 65.04 64.39 65.84 64.39 65.84 64.13 65.04 64.13 65.04 63.03 65.84 63.03 65.84 62.77 65.04 62.77 65.04 61.67 65.84 61.67 65.84 61.41 65.04 61.41 65.04 60.31 65.84 60.31 65.84 60.05 65.04 60.05 65.04 58.95 65.84 58.95 65.84 58.01 65.04 58.01 65.04 56.91 65.84 56.91 65.84 56.65 65.04 56.65 65.04 55.55 65.84 55.55 65.84 55.29 65.04 55.29 65.04 54.19 65.84 54.19 65.84 53.93 65.04 53.93 65.04 52.83 65.84 52.83 65.84 51.89 65.04 51.89 65.04 50.79 65.84 50.79 65.84 50.53 65.04 50.53 65.04 49.43 65.84 49.43 65.84 49.17 65.04 49.17 65.04 48.07 65.84 48.07 65.84 47.81 65.04 47.81 65.04 46.71 65.84 46.71 65.84 46.45 65.04 46.45 65.04 45.35 65.84 45.35 65.84 45.09 65.04 45.09 65.04 43.99 65.84 43.99 65.84 43.73 65.04 43.73 65.04 42.63 65.84 42.63 65.84 42.37 65.04 42.37 65.04 41.27 65.84 41.27 65.84 40.33 65.04 40.33 65.04 39.23 65.84 39.23 65.84 38.97 65.04 38.97 65.04 37.87 65.84 37.87 65.84 37.61 65.04 37.61 65.04 36.51 65.84 36.51 65.84 36.25 65.04 36.25 65.04 35.15 65.84 35.15 65.84 34.89 65.04 34.89 65.04 33.79 65.84 33.79 65.84 33.53 65.04 33.53 65.04 32.43 65.84 32.43 65.84 32.17 65.04 32.17 65.04 31.07 65.84 31.07 65.84 30.13 65.04 30.13 65.04 29.03 65.84 29.03 65.84 28.77 65.04 28.77 65.04 27.67 65.84 27.67 65.84 27.41 65.04 27.41 65.04 26.31 65.84 26.31 65.84 26.05 65.04 26.05 65.04 24.95 65.84 24.95 65.84 24.69 65.04 24.69 65.04 23.59 65.84 23.59 65.84 23.33 65.04 23.33 65.04 22.23 65.84 22.23 65.84 21.97 65.04 21.97 65.04 20.87 65.84 20.87 65.84 20.61 65.04 20.61 65.04 19.51 65.84 19.51 65.84 19.25 65.04 19.25 65.04 18.15 65.84 18.15 65.84 17.89 65.04 17.89 65.04 16.79 65.84 16.79 65.84 16.53 65.04 16.53 65.04 15.43 65.84 15.43 65.84 15.17 65.04 15.17 65.04 14.07 65.84 14.07 65.84 13.81 65.04 13.81 65.04 12.71 65.84 12.71 65.84 12.45 65.04 12.45 65.04 11.35 65.84 11.35 65.84 11.09 65.04 11.09 65.04 9.99 65.84 9.99 65.84 9.73 65.04 9.73 65.04 8.63 65.84 8.63 65.84 0.4 0.4 0.4 0.4 3.19 1.2 3.19 1.2 4.29 0.4 4.29 0.4 4.55 1.2 4.55 1.2 5.65 0.4 5.65 0.4 5.91 1.2 5.91 1.2 7.01 0.4 7.01 0.4 7.27 1.2 7.27 1.2 8.37 0.4 8.37 0.4 8.63 1.2 8.63 1.2 9.73 0.4 9.73 0.4 9.99 1.2 9.99 1.2 11.09 0.4 11.09 0.4 11.35 1.2 11.35 1.2 12.45 0.4 12.45 0.4 12.71 1.2 12.71 1.2 13.81 0.4 13.81 0.4 14.07 1.2 14.07 1.2 15.17 0.4 15.17 0.4 15.43 1.2 15.43 1.2 16.53 0.4 16.53 0.4 16.79 1.2 16.79 1.2 17.89 0.4 17.89 0.4 18.15 1.2 18.15 1.2 19.25 0.4 19.25 0.4 19.51 1.2 19.51 1.2 20.61 0.4 20.61 0.4 20.87 1.2 20.87 1.2 21.97 0.4 21.97 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 23.59 1.2 23.59 1.2 24.69 0.4 24.69 0.4 24.95 1.2 24.95 1.2 26.05 0.4 26.05 0.4 26.31 1.2 26.31 1.2 27.41 0.4 27.41 0.4 27.67 1.2 27.67 1.2 28.77 0.4 28.77 0.4 29.03 1.2 29.03 1.2 30.13 0.4 30.13 0.4 31.07 1.2 31.07 1.2 32.17 0.4 32.17 0.4 32.43 1.2 32.43 1.2 33.53 0.4 33.53 0.4 33.79 1.2 33.79 1.2 34.89 0.4 34.89 0.4 35.15 1.2 35.15 1.2 36.25 0.4 36.25 0.4 36.51 1.2 36.51 1.2 37.61 0.4 37.61 0.4 37.87 1.2 37.87 1.2 38.97 0.4 38.97 0.4 39.23 1.2 39.23 1.2 40.33 0.4 40.33 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 50.79 1.2 50.79 1.2 51.89 0.4 51.89 0.4 52.15 1.2 52.15 1.2 53.25 0.4 53.25 0.4 53.51 1.2 53.51 1.2 54.61 0.4 54.61 0.4 54.87 1.2 54.87 1.2 55.97 0.4 55.97 0.4 56.23 1.2 56.23 1.2 57.33 0.4 57.33 0.4 57.59 1.2 57.59 1.2 58.69 0.4 58.69 0.4 58.95 1.2 58.95 1.2 60.05 0.4 60.05 0.4 60.31 1.2 60.31 1.2 61.41 0.4 61.41 0.4 61.67 1.2 61.67 1.2 62.77 0.4 62.77 0.4 63.71 1.2 63.71 1.2 64.81 0.4 64.81 0.4 65.07 1.2 65.07 1.2 66.17 0.4 66.17 0.4 66.43 1.2 66.43 1.2 67.53 0.4 67.53 0.4 67.79 1.2 67.79 1.2 68.89 0.4 68.89 0.4 69.15 1.2 69.15 1.2 70.25 0.4 70.25 0.4 70.51 1.2 70.51 1.2 71.61 0.4 71.61 0.4 72.55 1.2 72.55 1.2 73.65 0.4 73.65 0.4 73.91 1.2 73.91 1.2 75.01 0.4 75.01 0.4 75.27 1.2 75.27 1.2 76.37 0.4 76.37 0.4 77.31 1.2 77.31 1.2 78.41 0.4 78.41 0.4 78.67 1.2 78.67 1.2 79.77 0.4 79.77 0.4 80.03 1.2 80.03 1.2 81.13 0.4 81.13 0.4 81.39 1.2 81.39 1.2 82.49 0.4 82.49 0.4 82.75 1.2 82.75 1.2 83.85 0.4 83.85 0.4 86.64 ; LAYER met2 ; RECT 55.06 86.855 55.34 87.225 ; RECT 25.62 86.855 25.9 87.225 ; + POLYGON 10.42 17.24 10.42 0.24 10.46 0.24 10.46 0.1 10.28 0.1 10.28 17.24 ; + POLYGON 14.1 16.05 14.1 0.24 14.14 0.24 14.14 0.1 13.96 0.1 13.96 16.05 ; + POLYGON 3.06 7.38 3.06 0.1 2.88 0.1 2.88 0.24 2.92 0.24 2.92 7.38 ; + RECT 32.3 0.69 32.56 1.01 ; + RECT 30.46 0.69 30.72 1.01 ; + RECT 28.62 0.35 28.88 0.67 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; POLYGON 65.96 86.76 65.96 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 36.46 0.28 36.46 0.765 35.76 0.765 35.76 0.28 35.54 0.28 35.54 0.765 34.84 0.765 34.84 0.28 34.62 0.28 34.62 0.765 33.92 0.765 33.92 0.28 33.24 0.28 33.24 0.765 32.54 0.765 32.54 0.28 32.32 0.28 32.32 0.765 31.62 0.765 31.62 0.28 31.4 0.28 31.4 0.765 30.7 0.765 30.7 0.28 30.48 0.28 30.48 0.765 29.78 0.765 29.78 0.28 29.56 0.28 29.56 0.765 28.86 0.765 28.86 0.28 28.64 0.28 28.64 0.765 27.94 0.765 27.94 0.28 27.72 0.28 27.72 0.765 27.02 0.765 27.02 0.28 26.8 0.28 26.8 0.765 26.1 0.765 26.1 0.28 24.96 0.28 24.96 0.765 24.26 0.765 24.26 0.28 23.58 0.28 23.58 0.765 22.88 0.765 22.88 0.28 22.2 0.28 22.2 0.765 21.5 0.765 21.5 0.28 21.28 0.28 21.28 0.765 20.58 0.765 20.58 0.28 19.9 0.28 19.9 0.765 19.2 0.765 19.2 0.28 18.98 0.28 18.98 0.765 18.28 0.765 18.28 0.28 17.6 0.28 17.6 0.765 16.9 0.765 16.9 0.28 16.68 0.28 16.68 0.765 15.98 0.765 15.98 0.28 15.76 0.28 15.76 0.765 15.06 0.765 15.06 0.28 14.84 0.28 14.84 0.765 14.14 0.765 14.14 0.28 13.92 0.28 13.92 0.765 13.22 0.765 13.22 0.28 12.54 0.28 12.54 0.765 11.84 0.765 11.84 0.28 11.16 0.28 11.16 0.765 10.46 0.765 10.46 0.28 10.24 0.28 10.24 0.765 9.54 0.765 9.54 0.28 9.32 0.28 9.32 0.765 8.62 0.765 8.62 0.28 8.4 0.28 8.4 0.765 7.7 0.765 7.7 0.28 7.02 0.28 7.02 0.765 6.32 0.765 6.32 0.28 6.1 0.28 6.1 0.765 5.4 0.765 5.4 0.28 5.18 0.28 5.18 0.765 4.48 0.765 4.48 0.28 4.26 0.28 4.26 0.765 3.56 0.765 3.56 0.28 2.88 0.28 2.88 0.765 2.18 0.765 2.18 0.28 0.28 0.28 0.28 86.76 2.18 86.76 2.18 86.275 2.88 86.275 2.88 86.76 3.1 86.76 3.1 86.275 3.8 86.275 3.8 86.76 15.98 86.76 15.98 86.275 16.68 86.275 16.68 86.76 24.26 86.76 24.26 86.275 24.96 86.275 24.96 86.76 61.52 86.76 61.52 86.275 62.22 86.275 62.22 86.76 63.36 86.76 63.36 86.275 64.06 86.275 64.06 86.76 ; @@ -1695,11 +1701,14 @@ MACRO cbx_1__0_ POLYGON 64.64 85.44 64.64 77.32 61.44 77.32 61.44 70.92 64.64 70.92 64.64 56.92 61.44 56.92 61.44 50.52 64.64 50.52 64.64 36.52 61.44 36.52 61.44 30.12 64.64 30.12 64.64 16.12 61.44 16.12 61.44 9.72 64.64 9.72 64.64 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; LAYER met1 ; RECT 45.68 86.8 46.32 87.28 ; + POLYGON 51.895 86.645 51.895 86.415 51.605 86.415 51.605 86.46 41.7 86.46 41.7 85.78 41.56 85.78 41.56 86.6 51.605 86.6 51.605 86.645 ; + POLYGON 49.06 0.92 49.06 0.44 39.49 0.44 39.49 0.38 39.17 0.38 39.17 0.64 39.49 0.64 39.49 0.58 48.92 0.58 48.92 0.92 ; + POLYGON 32.04 0.92 32.04 0.44 28.91 0.44 28.91 0.38 28.59 0.38 28.59 0.64 28.91 0.64 28.91 0.58 31.9 0.58 31.9 0.92 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 86.76 46.32 86.52 65.96 86.52 65.96 84.84 65.48 84.84 65.48 83.8 65.96 83.8 65.96 82.12 65.48 82.12 65.48 81.08 65.96 81.08 65.96 79.4 65.48 79.4 65.48 78.36 65.96 78.36 65.96 76.68 65.48 76.68 65.48 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 45.68 86.52 45.68 86.76 ; LAYER li1 ; - RECT 0 86.955 66.24 87.125 ; - RECT 62.56 84.235 66.24 84.405 ; + POLYGON 66.24 87.125 66.24 86.955 59.715 86.955 59.715 86.23 59.425 86.23 59.425 86.955 58.905 86.955 58.905 86.475 58.735 86.475 58.735 86.955 58.065 86.955 58.065 86.475 57.895 86.475 57.895 86.955 57.305 86.955 57.305 86.475 56.975 86.475 56.975 86.955 56.465 86.955 56.465 86.475 56.135 86.475 56.135 86.955 55.625 86.955 55.625 86.155 55.295 86.155 55.295 86.955 52.355 86.955 52.355 86.23 52.065 86.23 52.065 86.955 51.34 86.955 51.34 86.495 51.015 86.495 51.015 86.955 49.225 86.955 49.225 86.495 48.955 86.495 48.955 86.955 47.66 86.955 47.66 86.495 47.335 86.495 47.335 86.955 45.545 86.955 45.545 86.495 45.275 86.495 45.275 86.955 43.98 86.955 43.98 86.495 43.655 86.495 43.655 86.955 41.865 86.955 41.865 86.495 41.595 86.495 41.595 86.955 40.415 86.955 40.415 86.575 40.085 86.575 40.085 86.955 37.635 86.955 37.635 86.23 37.345 86.23 37.345 86.955 25.235 86.955 25.235 86.575 24.905 86.575 24.905 86.955 22.455 86.955 22.455 86.23 22.165 86.23 22.165 86.955 11.865 86.955 11.865 86.155 11.535 86.155 11.535 86.955 11.025 86.955 11.025 86.475 10.695 86.475 10.695 86.955 10.185 86.955 10.185 86.475 9.855 86.475 9.855 86.955 9.265 86.955 9.265 86.475 9.095 86.475 9.095 86.955 8.425 86.955 8.425 86.475 8.255 86.475 8.255 86.955 7.735 86.955 7.735 86.23 7.445 86.23 7.445 86.955 0 86.955 0 87.125 ; + RECT 65.32 84.235 66.24 84.405 ; RECT 0 84.235 3.68 84.405 ; RECT 65.32 81.515 66.24 81.685 ; RECT 0 81.515 3.68 81.685 ; @@ -1707,22 +1716,22 @@ MACRO cbx_1__0_ RECT 0 78.795 3.68 78.965 ; RECT 65.32 76.075 66.24 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 62.56 73.355 66.24 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 62.56 70.635 66.24 70.805 ; - RECT 0 70.635 1.84 70.805 ; + RECT 65.32 73.355 66.24 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 65.32 70.635 66.24 70.805 ; + RECT 0 70.635 3.68 70.805 ; RECT 65.32 67.915 66.24 68.085 ; RECT 0 67.915 3.68 68.085 ; RECT 65.32 65.195 66.24 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 62.56 62.475 66.24 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 62.56 59.755 66.24 59.925 ; + RECT 65.32 62.475 66.24 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 65.32 59.755 66.24 59.925 ; RECT 0 59.755 3.68 59.925 ; RECT 65.32 57.035 66.24 57.205 ; RECT 0 57.035 3.68 57.205 ; RECT 65.32 54.315 66.24 54.485 ; - RECT 0 54.315 1.84 54.485 ; + RECT 0 54.315 3.68 54.485 ; RECT 65.32 51.595 66.24 51.765 ; RECT 0 51.595 3.68 51.765 ; RECT 65.32 48.875 66.24 49.045 ; @@ -1730,10 +1739,10 @@ MACRO cbx_1__0_ RECT 65.32 46.155 66.24 46.325 ; RECT 0 46.155 3.68 46.325 ; RECT 65.32 43.435 66.24 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 64.4 40.715 66.24 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 64.4 37.995 66.24 38.165 ; + RECT 0 43.435 3.68 43.605 ; + RECT 65.32 40.715 66.24 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 65.32 37.995 66.24 38.165 ; RECT 0 37.995 3.68 38.165 ; RECT 65.32 35.275 66.24 35.445 ; RECT 0 35.275 3.68 35.445 ; @@ -1752,26 +1761,29 @@ MACRO cbx_1__0_ RECT 65.32 16.235 66.24 16.405 ; RECT 0 16.235 3.68 16.405 ; RECT 65.32 13.515 66.24 13.685 ; - RECT 0 13.515 1.84 13.685 ; - RECT 65.32 10.795 66.24 10.965 ; - RECT 0 10.795 1.84 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; - RECT 0 8.075 3.68 8.245 ; + RECT 0 13.515 3.68 13.685 ; + RECT 62.56 10.795 66.24 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 62.56 8.075 66.24 8.245 ; + RECT 0 8.075 1.84 8.245 ; RECT 65.32 5.355 66.24 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 62.56 2.635 66.24 2.805 ; + RECT 0 5.355 1.84 5.525 ; + RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; + POLYGON 59.715 0.81 59.715 0.085 66.24 0.085 66.24 -0.085 0 -0.085 0 0.085 3.865 0.085 3.865 0.55 4.115 0.55 4.115 0.085 4.705 0.085 4.705 0.545 4.875 0.545 4.875 0.085 5.545 0.085 5.545 0.545 5.715 0.545 5.715 0.085 6.505 0.085 6.505 0.545 6.77 0.545 6.77 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 8.535 0.085 8.535 0.545 8.79 0.545 8.79 0.085 9.46 0.085 9.46 0.545 9.63 0.545 9.63 0.085 10.3 0.085 10.3 0.545 10.47 0.545 10.47 0.085 11.14 0.085 11.14 0.545 11.31 0.545 11.31 0.085 11.98 0.085 11.98 0.545 12.285 0.545 12.285 0.085 12.675 0.085 12.675 0.545 12.93 0.545 12.93 0.085 13.6 0.085 13.6 0.545 13.77 0.545 13.77 0.085 14.44 0.085 14.44 0.545 14.61 0.545 14.61 0.085 15.28 0.085 15.28 0.545 15.45 0.545 15.45 0.085 16.12 0.085 16.12 0.545 16.425 0.545 16.425 0.085 16.745 0.085 16.745 0.55 16.995 0.55 16.995 0.085 17.585 0.085 17.585 0.545 17.755 0.545 17.755 0.085 18.425 0.085 18.425 0.545 18.595 0.545 18.595 0.085 19.385 0.085 19.385 0.545 19.65 0.545 19.65 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 27.765 0.085 27.765 0.485 28.095 0.485 28.095 0.085 28.605 0.085 28.605 0.485 28.935 0.485 28.935 0.085 30.35 0.085 30.35 0.595 30.765 0.595 30.765 0.085 31.795 0.085 31.795 0.595 32.21 0.595 32.21 0.085 33.625 0.085 33.625 0.485 33.955 0.485 33.955 0.085 34.465 0.085 34.465 0.485 34.795 0.485 34.795 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 39.355 0.085 39.355 0.545 39.61 0.545 39.61 0.085 40.28 0.085 40.28 0.545 40.45 0.545 40.45 0.085 41.12 0.085 41.12 0.545 41.29 0.545 41.29 0.085 41.96 0.085 41.96 0.545 42.13 0.545 42.13 0.085 42.8 0.085 42.8 0.545 43.105 0.545 43.105 0.085 46.165 0.085 46.165 0.485 46.495 0.485 46.495 0.085 47.005 0.085 47.005 0.485 47.335 0.485 47.335 0.085 48.75 0.085 48.75 0.595 49.165 0.595 49.165 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 59.425 0.085 59.425 0.81 ; RECT 0.17 0.17 66.07 86.87 ; + LAYER mcon ; + RECT 51.665 86.445 51.835 86.615 ; LAYER via ; RECT 55.125 86.965 55.275 87.115 ; RECT 25.685 86.965 25.835 87.115 ; + RECT 39.255 0.435 39.405 0.585 ; + RECT 28.675 0.435 28.825 0.585 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 86.94 55.3 87.14 ; RECT 25.66 86.94 25.86 87.14 ; - RECT 1.05 36.96 1.25 37.16 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__1__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__1__icv_in_design.lef index 675ca4a..73c0767 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__1__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__1__icv_in_design.lef @@ -1502,13 +1502,14 @@ MACRO cbx_1__1_ LAYER met3 ; POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ; POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ; - POLYGON 1.315 38.585 1.315 38.57 10.5 38.57 10.5 38.27 1.315 38.27 1.315 38.255 0.985 38.255 0.985 38.585 ; + POLYGON 42.7 48.09 42.7 47.79 1.2 47.79 1.2 47.81 0.65 47.81 0.65 48.09 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; POLYGON 65.84 86.64 65.84 77.73 65.04 77.73 65.04 76.63 65.84 76.63 65.84 76.37 65.04 76.37 65.04 75.27 65.84 75.27 65.84 75.01 65.04 75.01 65.04 73.91 65.84 73.91 65.84 73.65 65.04 73.65 65.04 72.55 65.84 72.55 65.84 71.61 65.04 71.61 65.04 70.51 65.84 70.51 65.84 70.25 65.04 70.25 65.04 69.15 65.84 69.15 65.84 68.89 65.04 68.89 65.04 67.79 65.84 67.79 65.84 67.53 65.04 67.53 65.04 66.43 65.84 66.43 65.84 66.17 65.04 66.17 65.04 65.07 65.84 65.07 65.84 64.81 65.04 64.81 65.04 63.71 65.84 63.71 65.84 63.45 65.04 63.45 65.04 62.35 65.84 62.35 65.84 62.09 65.04 62.09 65.04 60.99 65.84 60.99 65.84 60.73 65.04 60.73 65.04 59.63 65.84 59.63 65.84 59.37 65.04 59.37 65.04 58.27 65.84 58.27 65.84 58.01 65.04 58.01 65.04 56.91 65.84 56.91 65.84 56.65 65.04 56.65 65.04 55.55 65.84 55.55 65.84 54.61 65.04 54.61 65.04 53.51 65.84 53.51 65.84 53.25 65.04 53.25 65.04 52.15 65.84 52.15 65.84 51.89 65.04 51.89 65.04 50.79 65.84 50.79 65.84 50.53 65.04 50.53 65.04 49.43 65.84 49.43 65.84 49.17 65.04 49.17 65.04 48.07 65.84 48.07 65.84 47.81 65.04 47.81 65.04 46.71 65.84 46.71 65.84 46.45 65.04 46.45 65.04 45.35 65.84 45.35 65.84 45.09 65.04 45.09 65.04 43.99 65.84 43.99 65.84 43.73 65.04 43.73 65.04 42.63 65.84 42.63 65.84 42.37 65.04 42.37 65.04 41.27 65.84 41.27 65.84 41.01 65.04 41.01 65.04 39.91 65.84 39.91 65.84 39.65 65.04 39.65 65.04 38.55 65.84 38.55 65.84 38.29 65.04 38.29 65.04 37.19 65.84 37.19 65.84 36.93 65.04 36.93 65.04 35.83 65.84 35.83 65.84 35.57 65.04 35.57 65.04 34.47 65.84 34.47 65.84 34.21 65.04 34.21 65.04 33.11 65.84 33.11 65.84 32.85 65.04 32.85 65.04 31.75 65.84 31.75 65.84 31.49 65.04 31.49 65.04 30.39 65.84 30.39 65.84 30.13 65.04 30.13 65.04 29.03 65.84 29.03 65.84 28.77 65.04 28.77 65.04 27.67 65.84 27.67 65.84 27.41 65.04 27.41 65.04 26.31 65.84 26.31 65.84 26.05 65.04 26.05 65.04 24.95 65.84 24.95 65.84 24.69 65.04 24.69 65.04 23.59 65.84 23.59 65.84 23.33 65.04 23.33 65.04 22.23 65.84 22.23 65.84 21.97 65.04 21.97 65.04 20.87 65.84 20.87 65.84 20.61 65.04 20.61 65.04 19.51 65.84 19.51 65.84 19.25 65.04 19.25 65.04 18.15 65.84 18.15 65.84 17.89 65.04 17.89 65.04 16.79 65.84 16.79 65.84 16.53 65.04 16.53 65.04 15.43 65.84 15.43 65.84 15.17 65.04 15.17 65.04 14.07 65.84 14.07 65.84 13.81 65.04 13.81 65.04 12.71 65.84 12.71 65.84 12.45 65.04 12.45 65.04 11.35 65.84 11.35 65.84 7.01 65.04 7.01 65.04 5.91 65.84 5.91 65.84 5.65 65.04 5.65 65.04 4.55 65.84 4.55 65.84 4.29 65.04 4.29 65.04 3.19 65.84 3.19 65.84 0.4 0.4 0.4 0.4 3.19 1.2 3.19 1.2 4.29 0.4 4.29 0.4 4.55 1.2 4.55 1.2 5.65 0.4 5.65 0.4 11.35 1.2 11.35 1.2 12.45 0.4 12.45 0.4 12.71 1.2 12.71 1.2 13.81 0.4 13.81 0.4 14.07 1.2 14.07 1.2 15.17 0.4 15.17 0.4 15.43 1.2 15.43 1.2 16.53 0.4 16.53 0.4 16.79 1.2 16.79 1.2 17.89 0.4 17.89 0.4 18.15 1.2 18.15 1.2 19.25 0.4 19.25 0.4 19.51 1.2 19.51 1.2 20.61 0.4 20.61 0.4 20.87 1.2 20.87 1.2 21.97 0.4 21.97 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 23.59 1.2 23.59 1.2 24.69 0.4 24.69 0.4 24.95 1.2 24.95 1.2 26.05 0.4 26.05 0.4 26.31 1.2 26.31 1.2 27.41 0.4 27.41 0.4 27.67 1.2 27.67 1.2 28.77 0.4 28.77 0.4 29.03 1.2 29.03 1.2 30.13 0.4 30.13 0.4 30.39 1.2 30.39 1.2 31.49 0.4 31.49 0.4 31.75 1.2 31.75 1.2 32.85 0.4 32.85 0.4 33.11 1.2 33.11 1.2 34.21 0.4 34.21 0.4 34.47 1.2 34.47 1.2 35.57 0.4 35.57 0.4 35.83 1.2 35.83 1.2 36.93 0.4 36.93 0.4 37.19 1.2 37.19 1.2 38.29 0.4 38.29 0.4 38.55 1.2 38.55 1.2 39.65 0.4 39.65 0.4 39.91 1.2 39.91 1.2 41.01 0.4 41.01 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 50.79 1.2 50.79 1.2 51.89 0.4 51.89 0.4 52.15 1.2 52.15 1.2 53.25 0.4 53.25 0.4 53.51 1.2 53.51 1.2 54.61 0.4 54.61 0.4 54.87 1.2 54.87 1.2 55.97 0.4 55.97 0.4 56.23 1.2 56.23 1.2 57.33 0.4 57.33 0.4 57.59 1.2 57.59 1.2 58.69 0.4 58.69 0.4 58.95 1.2 58.95 1.2 60.05 0.4 60.05 0.4 60.31 1.2 60.31 1.2 61.41 0.4 61.41 0.4 61.67 1.2 61.67 1.2 62.77 0.4 62.77 0.4 63.03 1.2 63.03 1.2 64.13 0.4 64.13 0.4 64.39 1.2 64.39 1.2 65.49 0.4 65.49 0.4 65.75 1.2 65.75 1.2 66.85 0.4 66.85 0.4 67.11 1.2 67.11 1.2 68.21 0.4 68.21 0.4 68.47 1.2 68.47 1.2 69.57 0.4 69.57 0.4 69.83 1.2 69.83 1.2 70.93 0.4 70.93 0.4 71.19 1.2 71.19 1.2 72.29 0.4 72.29 0.4 72.55 1.2 72.55 1.2 73.65 0.4 73.65 0.4 73.91 1.2 73.91 1.2 75.01 0.4 75.01 0.4 75.27 1.2 75.27 1.2 76.37 0.4 76.37 0.4 76.63 1.2 76.63 1.2 77.73 0.4 77.73 0.4 77.99 1.2 77.99 1.2 79.09 0.4 79.09 0.4 86.64 ; LAYER met2 ; RECT 55.06 86.855 55.34 87.225 ; RECT 25.62 86.855 25.9 87.225 ; + POLYGON 44.46 0.92 44.46 0.27 40.6 0.27 40.6 0.41 44.32 0.41 44.32 0.92 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; POLYGON 65.96 86.76 65.96 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 60.84 0.28 60.84 0.765 60.14 0.765 60.14 0.28 59.92 0.28 59.92 0.765 59.22 0.765 59.22 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 30.48 0.28 30.48 0.765 29.78 0.765 29.78 0.28 26.8 0.28 26.8 0.765 26.1 0.765 26.1 0.28 25.42 0.28 25.42 0.765 24.72 0.765 24.72 0.28 24.5 0.28 24.5 0.765 23.8 0.765 23.8 0.28 23.58 0.28 23.58 0.765 22.88 0.765 22.88 0.28 18.52 0.28 18.52 0.765 17.82 0.765 17.82 0.28 13.46 0.28 13.46 0.765 12.76 0.765 12.76 0.28 12.54 0.28 12.54 0.765 11.84 0.765 11.84 0.28 11.62 0.28 11.62 0.765 10.92 0.765 10.92 0.28 10.7 0.28 10.7 0.765 10 0.765 10 0.28 9.78 0.28 9.78 0.765 9.08 0.765 9.08 0.28 8.4 0.28 8.4 0.765 7.7 0.765 7.7 0.28 7.48 0.28 7.48 0.765 6.78 0.765 6.78 0.28 6.1 0.28 6.1 0.765 5.4 0.765 5.4 0.28 5.18 0.28 5.18 0.765 4.48 0.765 4.48 0.28 3.8 0.28 3.8 0.765 3.1 0.765 3.1 0.28 0.28 0.28 0.28 86.76 12.76 86.76 12.76 86.275 13.46 86.275 13.46 86.76 15.98 86.76 15.98 86.275 16.68 86.275 16.68 86.76 24.26 86.76 24.26 86.275 24.96 86.275 24.96 86.76 29.78 86.76 29.78 86.275 30.48 86.275 30.48 86.76 57.38 86.76 57.38 86.275 58.08 86.275 58.08 86.76 61.52 86.76 61.52 86.275 62.22 86.275 62.22 86.76 ; @@ -1518,11 +1519,16 @@ MACRO cbx_1__1_ POLYGON 64.64 85.44 64.64 77.32 61.44 77.32 61.44 70.92 64.64 70.92 64.64 56.92 61.44 56.92 61.44 50.52 64.64 50.52 64.64 36.52 61.44 36.52 61.44 30.12 64.64 30.12 64.64 16.12 61.44 16.12 61.44 9.72 64.64 9.72 64.64 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; LAYER met1 ; RECT 45.68 86.8 46.32 87.28 ; + POLYGON 13.27 86.66 13.27 86.6 26.52 86.6 26.52 86.12 26.38 86.12 26.38 86.46 13.27 86.46 13.27 86.4 12.95 86.4 12.95 86.66 ; + POLYGON 35.72 0.92 35.72 0.58 37.805 0.58 37.805 0.625 38.095 0.625 38.095 0.395 37.805 0.395 37.805 0.44 35.58 0.44 35.58 0.92 ; + POLYGON 29.28 0.92 29.28 0.44 26.61 0.44 26.61 0.38 26.29 0.38 26.29 0.64 26.61 0.64 26.61 0.58 29.14 0.58 29.14 0.92 ; + POLYGON 59.73 0.64 59.73 0.38 59.41 0.38 59.41 0.44 50.605 0.44 50.605 0.395 50.315 0.395 50.315 0.625 50.605 0.625 50.605 0.58 59.41 0.58 59.41 0.64 ; + POLYGON 25.23 0.64 25.23 0.58 25.755 0.58 25.755 0.625 26.045 0.625 26.045 0.395 25.755 0.395 25.755 0.44 25.23 0.44 25.23 0.38 24.91 0.38 24.91 0.64 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 86.76 46.32 86.52 65.96 86.52 65.96 84.84 65.48 84.84 65.48 83.8 65.96 83.8 65.96 82.12 65.48 82.12 65.48 81.08 65.96 81.08 65.96 79.4 65.48 79.4 65.48 78.36 65.96 78.36 65.96 76.68 65.48 76.68 65.48 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 45.68 86.52 45.68 86.76 ; LAYER li1 ; - RECT 0 86.955 66.24 87.125 ; - RECT 62.56 84.235 66.24 84.405 ; + POLYGON 66.24 87.125 66.24 86.955 59.715 86.955 59.715 86.23 59.425 86.23 59.425 86.955 58.825 86.955 58.825 86.475 58.495 86.475 58.495 86.955 57.985 86.955 57.985 86.475 57.655 86.475 57.655 86.955 57.145 86.955 57.145 86.475 56.815 86.475 56.815 86.955 56.305 86.955 56.305 86.475 55.975 86.475 55.975 86.955 55.465 86.955 55.465 86.475 55.135 86.475 55.135 86.955 54.625 86.955 54.625 86.155 54.295 86.155 54.295 86.955 53.295 86.955 53.295 86.575 52.965 86.575 52.965 86.955 52.355 86.955 52.355 86.23 52.065 86.23 52.065 86.955 51.465 86.955 51.465 86.475 51.135 86.475 51.135 86.955 50.625 86.955 50.625 86.475 50.295 86.475 50.295 86.955 49.785 86.955 49.785 86.475 49.455 86.475 49.455 86.955 48.945 86.955 48.945 86.475 48.615 86.475 48.615 86.955 48.105 86.955 48.105 86.475 47.775 86.475 47.775 86.955 47.265 86.955 47.265 86.155 46.935 86.155 46.935 86.955 46.235 86.955 46.235 86.48 46.065 86.48 46.065 86.955 45.385 86.955 45.385 86.48 45.215 86.48 45.215 86.955 44.515 86.955 44.515 86.475 44.345 86.475 44.345 86.955 43.515 86.955 43.515 86.425 43.345 86.425 43.345 86.955 41.49 86.955 41.49 86.455 41.12 86.455 41.12 86.955 39.425 86.955 39.425 86.495 39.175 86.495 39.175 86.955 38.565 86.955 38.565 86.575 38.235 86.575 38.235 86.955 37.635 86.955 37.635 86.23 37.345 86.23 37.345 86.955 36.575 86.955 36.575 86.48 36.405 86.48 36.405 86.955 35.725 86.955 35.725 86.48 35.555 86.48 35.555 86.955 34.855 86.955 34.855 86.475 34.685 86.475 34.685 86.955 33.855 86.955 33.855 86.425 33.685 86.425 33.685 86.955 31.83 86.955 31.83 86.455 31.46 86.455 31.46 86.955 29.765 86.955 29.765 86.495 29.515 86.495 29.515 86.955 28.905 86.955 28.905 86.575 28.575 86.575 28.575 86.955 26.585 86.955 26.585 86.155 26.255 86.155 26.255 86.955 25.745 86.955 25.745 86.475 25.415 86.475 25.415 86.955 24.905 86.955 24.905 86.475 24.575 86.475 24.575 86.955 23.985 86.955 23.985 86.475 23.815 86.475 23.815 86.955 23.145 86.955 23.145 86.475 22.975 86.475 22.975 86.955 22.455 86.955 22.455 86.23 22.165 86.23 22.165 86.955 18.385 86.955 18.385 86.155 18.055 86.155 18.055 86.955 17.545 86.955 17.545 86.475 17.215 86.475 17.215 86.955 16.705 86.955 16.705 86.475 16.375 86.475 16.375 86.955 15.865 86.955 15.865 86.475 15.535 86.475 15.535 86.955 15.025 86.955 15.025 86.475 14.695 86.475 14.695 86.955 14.185 86.955 14.185 86.475 13.855 86.475 13.855 86.955 12.865 86.955 12.865 86.155 12.535 86.155 12.535 86.955 12.025 86.955 12.025 86.475 11.695 86.475 11.695 86.955 11.185 86.955 11.185 86.475 10.855 86.475 10.855 86.955 10.345 86.955 10.345 86.475 10.015 86.475 10.015 86.955 9.505 86.955 9.505 86.475 9.175 86.475 9.175 86.955 8.665 86.955 8.665 86.475 8.335 86.475 8.335 86.955 7.735 86.955 7.735 86.23 7.445 86.23 7.445 86.955 0 86.955 0 87.125 ; + RECT 65.32 84.235 66.24 84.405 ; RECT 0 84.235 3.68 84.405 ; RECT 65.32 81.515 66.24 81.685 ; RECT 0 81.515 3.68 81.685 ; @@ -1532,30 +1538,30 @@ MACRO cbx_1__1_ RECT 0 76.075 3.68 76.245 ; RECT 65.32 73.355 66.24 73.525 ; RECT 0 73.355 1.84 73.525 ; - RECT 64.4 70.635 66.24 70.805 ; + RECT 65.32 70.635 66.24 70.805 ; RECT 0 70.635 1.84 70.805 ; - RECT 64.4 67.915 66.24 68.085 ; + RECT 65.32 67.915 66.24 68.085 ; RECT 0 67.915 3.68 68.085 ; RECT 65.32 65.195 66.24 65.365 ; RECT 0 65.195 3.68 65.365 ; RECT 65.32 62.475 66.24 62.645 ; - RECT 0 62.475 1.84 62.645 ; + RECT 0 62.475 3.68 62.645 ; RECT 65.32 59.755 66.24 59.925 ; - RECT 0 59.755 1.84 59.925 ; + RECT 0 59.755 3.68 59.925 ; RECT 65.32 57.035 66.24 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 64.4 54.315 66.24 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 64.4 51.595 66.24 51.765 ; - RECT 0 51.595 1.84 51.765 ; + RECT 0 57.035 3.68 57.205 ; + RECT 65.32 54.315 66.24 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 65.32 51.595 66.24 51.765 ; + RECT 0 51.595 3.68 51.765 ; RECT 65.32 48.875 66.24 49.045 ; RECT 0 48.875 3.68 49.045 ; RECT 65.32 46.155 66.24 46.325 ; RECT 0 46.155 3.68 46.325 ; RECT 65.32 43.435 66.24 43.605 ; - RECT 0 43.435 1.84 43.605 ; + RECT 0 43.435 3.68 43.605 ; RECT 65.32 40.715 66.24 40.885 ; - RECT 0 40.715 1.84 40.885 ; + RECT 0 40.715 3.68 40.885 ; RECT 65.32 37.995 66.24 38.165 ; RECT 0 37.995 3.68 38.165 ; RECT 65.32 35.275 66.24 35.445 ; @@ -1565,37 +1571,46 @@ MACRO cbx_1__1_ RECT 65.32 29.835 66.24 30.005 ; RECT 0 29.835 3.68 30.005 ; RECT 65.32 27.115 66.24 27.285 ; - RECT 0 27.115 1.84 27.285 ; + RECT 0 27.115 3.68 27.285 ; RECT 65.32 24.395 66.24 24.565 ; RECT 0 24.395 1.84 24.565 ; RECT 65.32 21.675 66.24 21.845 ; - RECT 0 21.675 3.68 21.845 ; + RECT 0 21.675 1.84 21.845 ; RECT 65.32 18.955 66.24 19.125 ; RECT 0 18.955 3.68 19.125 ; RECT 65.32 16.235 66.24 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 62.56 13.515 66.24 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 62.56 10.795 66.24 10.965 ; + RECT 65.32 13.515 66.24 13.685 ; + RECT 0 13.515 1.84 13.685 ; + RECT 65.32 10.795 66.24 10.965 ; RECT 0 10.795 3.68 10.965 ; RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; RECT 65.32 5.355 66.24 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 62.56 2.635 66.24 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; + RECT 0 5.355 1.84 5.525 ; + RECT 65.32 2.635 66.24 2.805 ; + RECT 0 2.635 1.84 2.805 ; + POLYGON 59.245 0.885 59.245 0.085 59.425 0.085 59.425 0.81 59.715 0.81 59.715 0.085 66.24 0.085 66.24 -0.085 0 -0.085 0 0.085 2.855 0.085 2.855 0.885 3.185 0.885 3.185 0.085 3.695 0.085 3.695 0.565 4.025 0.565 4.025 0.085 4.535 0.085 4.535 0.565 4.865 0.565 4.865 0.085 5.455 0.085 5.455 0.565 5.625 0.565 5.625 0.085 6.295 0.085 6.295 0.565 6.465 0.565 6.465 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 7.915 0.085 7.915 0.885 8.245 0.885 8.245 0.085 8.755 0.085 8.755 0.565 9.085 0.565 9.085 0.085 9.595 0.085 9.595 0.565 9.925 0.565 9.925 0.085 10.515 0.085 10.515 0.565 10.685 0.565 10.685 0.085 11.355 0.085 11.355 0.565 11.525 0.565 11.525 0.085 12.055 0.085 12.055 0.885 12.385 0.885 12.385 0.085 12.895 0.085 12.895 0.565 13.225 0.565 13.225 0.085 13.735 0.085 13.735 0.565 14.065 0.565 14.065 0.085 14.655 0.085 14.655 0.565 14.825 0.565 14.825 0.085 15.495 0.085 15.495 0.565 15.665 0.565 15.665 0.085 18.035 0.085 18.035 0.885 18.365 0.885 18.365 0.085 18.875 0.085 18.875 0.565 19.205 0.565 19.205 0.085 19.715 0.085 19.715 0.565 20.045 0.565 20.045 0.085 20.635 0.085 20.635 0.565 20.805 0.565 20.805 0.085 21.475 0.085 21.475 0.565 21.645 0.565 21.645 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 24.475 0.085 24.475 0.885 24.805 0.885 24.805 0.085 25.315 0.085 25.315 0.565 25.645 0.565 25.645 0.085 26.155 0.085 26.155 0.565 26.485 0.565 26.485 0.085 27.075 0.085 27.075 0.565 27.245 0.565 27.245 0.085 27.915 0.085 27.915 0.565 28.085 0.565 28.085 0.085 28.615 0.085 28.615 0.885 28.945 0.885 28.945 0.085 29.455 0.085 29.455 0.565 29.785 0.565 29.785 0.085 30.295 0.085 30.295 0.565 30.625 0.565 30.625 0.085 31.215 0.085 31.215 0.565 31.385 0.565 31.385 0.085 32.055 0.085 32.055 0.565 32.225 0.565 32.225 0.085 32.755 0.085 32.755 0.885 33.085 0.885 33.085 0.085 33.595 0.085 33.595 0.565 33.925 0.565 33.925 0.085 34.435 0.085 34.435 0.565 34.765 0.565 34.765 0.085 35.355 0.085 35.355 0.565 35.525 0.565 35.525 0.085 36.195 0.085 36.195 0.565 36.365 0.565 36.365 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 38.235 0.085 38.235 0.485 38.565 0.485 38.565 0.085 40.525 0.085 40.525 0.62 41.035 0.62 41.035 0.085 42.385 0.085 42.385 0.465 42.715 0.465 42.715 0.085 43.335 0.085 43.335 0.885 43.665 0.885 43.665 0.085 44.175 0.085 44.175 0.565 44.505 0.565 44.505 0.085 45.015 0.085 45.015 0.565 45.345 0.565 45.345 0.085 45.935 0.085 45.935 0.565 46.105 0.565 46.105 0.085 46.775 0.085 46.775 0.565 46.945 0.565 46.945 0.085 48.275 0.085 48.275 0.565 48.445 0.565 48.445 0.085 49.115 0.085 49.115 0.565 49.285 0.565 49.285 0.085 49.875 0.085 49.875 0.565 50.205 0.565 50.205 0.085 50.715 0.085 50.715 0.565 51.045 0.565 51.045 0.085 51.555 0.085 51.555 0.885 51.885 0.885 51.885 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 55.635 0.085 55.635 0.565 55.805 0.565 55.805 0.085 56.475 0.085 56.475 0.565 56.645 0.565 56.645 0.085 57.235 0.085 57.235 0.565 57.565 0.565 57.565 0.085 58.075 0.085 58.075 0.565 58.405 0.565 58.405 0.085 58.915 0.085 58.915 0.885 ; RECT 0.17 0.17 66.07 86.87 ; + LAYER mcon ; + RECT 50.375 0.425 50.545 0.595 ; + RECT 37.865 0.425 38.035 0.595 ; + RECT 25.815 0.425 25.985 0.595 ; LAYER via ; RECT 55.125 86.965 55.275 87.115 ; RECT 25.685 86.965 25.835 87.115 ; + RECT 13.035 86.455 13.185 86.605 ; + RECT 59.495 0.435 59.645 0.585 ; + RECT 26.375 0.435 26.525 0.585 ; + RECT 24.995 0.435 25.145 0.585 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 86.94 55.3 87.14 ; RECT 25.66 86.94 25.86 87.14 ; - RECT 1.05 66.2 1.25 66.4 ; - RECT 1.05 55.32 1.25 55.52 ; + RECT 64.99 44.44 65.19 44.64 ; + RECT 1.05 41.72 1.25 41.92 ; + RECT 1.05 36.28 1.25 36.48 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__2__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__2__icv_in_design.lef index 2aa7bd7..912a032 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__2__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/cbx_1__2__icv_in_design.lef @@ -1358,13 +1358,15 @@ MACRO cbx_1__2_ LAYER met3 ; POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ; POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ; - POLYGON 65.04 48.09 65.04 48.07 65.59 48.07 65.59 47.79 49.07 47.79 49.07 48.09 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; POLYGON 65.84 86.64 65.84 80.45 65.04 80.45 65.04 79.35 65.84 79.35 65.84 66.85 65.04 66.85 65.04 65.75 65.84 65.75 65.84 65.49 65.04 65.49 65.04 64.39 65.84 64.39 65.84 64.13 65.04 64.13 65.04 63.03 65.84 63.03 65.84 62.77 65.04 62.77 65.04 61.67 65.84 61.67 65.84 61.41 65.04 61.41 65.04 60.31 65.84 60.31 65.84 59.37 65.04 59.37 65.04 58.27 65.84 58.27 65.84 58.01 65.04 58.01 65.04 56.91 65.84 56.91 65.84 56.65 65.04 56.65 65.04 55.55 65.84 55.55 65.84 55.29 65.04 55.29 65.04 54.19 65.84 54.19 65.84 53.93 65.04 53.93 65.04 52.83 65.84 52.83 65.84 52.57 65.04 52.57 65.04 51.47 65.84 51.47 65.84 50.53 65.04 50.53 65.04 49.43 65.84 49.43 65.84 49.17 65.04 49.17 65.04 48.07 65.84 48.07 65.84 47.81 65.04 47.81 65.04 46.71 65.84 46.71 65.84 46.45 65.04 46.45 65.04 45.35 65.84 45.35 65.84 45.09 65.04 45.09 65.04 43.99 65.84 43.99 65.84 43.73 65.04 43.73 65.04 42.63 65.84 42.63 65.84 42.37 65.04 42.37 65.04 41.27 65.84 41.27 65.84 41.01 65.04 41.01 65.04 39.91 65.84 39.91 65.84 39.65 65.04 39.65 65.04 38.55 65.84 38.55 65.84 38.29 65.04 38.29 65.04 37.19 65.84 37.19 65.84 36.93 65.04 36.93 65.04 35.83 65.84 35.83 65.84 35.57 65.04 35.57 65.04 34.47 65.84 34.47 65.84 34.21 65.04 34.21 65.04 33.11 65.84 33.11 65.84 32.85 65.04 32.85 65.04 31.75 65.84 31.75 65.84 31.49 65.04 31.49 65.04 30.39 65.84 30.39 65.84 30.13 65.04 30.13 65.04 29.03 65.84 29.03 65.84 28.77 65.04 28.77 65.04 27.67 65.84 27.67 65.84 27.41 65.04 27.41 65.04 26.31 65.84 26.31 65.84 25.37 65.04 25.37 65.04 24.27 65.84 24.27 65.84 24.01 65.04 24.01 65.04 22.91 65.84 22.91 65.84 22.65 65.04 22.65 65.04 21.55 65.84 21.55 65.84 21.29 65.04 21.29 65.04 20.19 65.84 20.19 65.84 19.25 65.04 19.25 65.04 18.15 65.84 18.15 65.84 17.21 65.04 17.21 65.04 16.11 65.84 16.11 65.84 15.85 65.04 15.85 65.04 14.75 65.84 14.75 65.84 14.49 65.04 14.49 65.04 13.39 65.84 13.39 65.84 13.13 65.04 13.13 65.04 12.03 65.84 12.03 65.84 11.77 65.04 11.77 65.04 10.67 65.84 10.67 65.84 10.41 65.04 10.41 65.04 9.31 65.84 9.31 65.84 8.37 65.04 8.37 65.04 7.27 65.84 7.27 65.84 7.01 65.04 7.01 65.04 5.91 65.84 5.91 65.84 5.65 65.04 5.65 65.04 4.55 65.84 4.55 65.84 4.29 65.04 4.29 65.04 3.19 65.84 3.19 65.84 0.4 0.4 0.4 0.4 3.19 1.2 3.19 1.2 4.29 0.4 4.29 0.4 4.55 1.2 4.55 1.2 5.65 0.4 5.65 0.4 6.59 1.2 6.59 1.2 7.69 0.4 7.69 0.4 7.95 1.2 7.95 1.2 9.05 0.4 9.05 0.4 9.31 1.2 9.31 1.2 10.41 0.4 10.41 0.4 11.35 1.2 11.35 1.2 12.45 0.4 12.45 0.4 12.71 1.2 12.71 1.2 13.81 0.4 13.81 0.4 14.07 1.2 14.07 1.2 15.17 0.4 15.17 0.4 15.43 1.2 15.43 1.2 16.53 0.4 16.53 0.4 16.79 1.2 16.79 1.2 17.89 0.4 17.89 0.4 18.15 1.2 18.15 1.2 19.25 0.4 19.25 0.4 19.51 1.2 19.51 1.2 20.61 0.4 20.61 0.4 20.87 1.2 20.87 1.2 21.97 0.4 21.97 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 24.27 1.2 24.27 1.2 25.37 0.4 25.37 0.4 25.63 1.2 25.63 1.2 26.73 0.4 26.73 0.4 26.99 1.2 26.99 1.2 28.09 0.4 28.09 0.4 28.35 1.2 28.35 1.2 29.45 0.4 29.45 0.4 29.71 1.2 29.71 1.2 30.81 0.4 30.81 0.4 31.07 1.2 31.07 1.2 32.17 0.4 32.17 0.4 32.43 1.2 32.43 1.2 33.53 0.4 33.53 0.4 33.79 1.2 33.79 1.2 34.89 0.4 34.89 0.4 35.15 1.2 35.15 1.2 36.25 0.4 36.25 0.4 36.51 1.2 36.51 1.2 37.61 0.4 37.61 0.4 38.55 1.2 38.55 1.2 39.65 0.4 39.65 0.4 39.91 1.2 39.91 1.2 41.01 0.4 41.01 0.4 41.95 1.2 41.95 1.2 43.05 0.4 43.05 0.4 43.31 1.2 43.31 1.2 44.41 0.4 44.41 0.4 44.67 1.2 44.67 1.2 45.77 0.4 45.77 0.4 46.03 1.2 46.03 1.2 47.13 0.4 47.13 0.4 47.39 1.2 47.39 1.2 48.49 0.4 48.49 0.4 48.75 1.2 48.75 1.2 49.85 0.4 49.85 0.4 50.11 1.2 50.11 1.2 51.21 0.4 51.21 0.4 51.47 1.2 51.47 1.2 52.57 0.4 52.57 0.4 52.83 1.2 52.83 1.2 53.93 0.4 53.93 0.4 54.19 1.2 54.19 1.2 55.29 0.4 55.29 0.4 55.55 1.2 55.55 1.2 56.65 0.4 56.65 0.4 56.91 1.2 56.91 1.2 58.01 0.4 58.01 0.4 58.27 1.2 58.27 1.2 59.37 0.4 59.37 0.4 59.63 1.2 59.63 1.2 60.73 0.4 60.73 0.4 60.99 1.2 60.99 1.2 62.09 0.4 62.09 0.4 62.35 1.2 62.35 1.2 63.45 0.4 63.45 0.4 63.71 1.2 63.71 1.2 64.81 0.4 64.81 0.4 65.07 1.2 65.07 1.2 66.17 0.4 66.17 0.4 79.35 1.2 79.35 1.2 80.45 0.4 80.45 0.4 86.64 ; LAYER met2 ; RECT 55.06 86.855 55.34 87.225 ; RECT 25.62 86.855 25.9 87.225 ; + RECT 28.16 86.03 28.42 86.35 ; + POLYGON 11.8 6.02 11.8 0.1 11.62 0.1 11.62 0.24 11.66 0.24 11.66 6.02 ; + POLYGON 4.44 3.3 4.44 0.24 4.48 0.24 4.48 0.1 4.3 0.1 4.3 3.3 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; POLYGON 65.96 86.76 65.96 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 60.84 0.28 60.84 0.765 60.14 0.765 60.14 0.28 59.92 0.28 59.92 0.765 59.22 0.765 59.22 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 26.8 0.28 26.8 0.765 26.1 0.765 26.1 0.28 25.42 0.28 25.42 0.765 24.72 0.765 24.72 0.28 24.5 0.28 24.5 0.765 23.8 0.765 23.8 0.28 23.58 0.28 23.58 0.765 22.88 0.765 22.88 0.28 18.52 0.28 18.52 0.765 17.82 0.765 17.82 0.28 12.54 0.28 12.54 0.765 11.84 0.765 11.84 0.28 11.62 0.28 11.62 0.765 10.92 0.765 10.92 0.28 10.7 0.28 10.7 0.765 10 0.765 10 0.28 8.4 0.28 8.4 0.765 7.7 0.765 7.7 0.28 7.48 0.28 7.48 0.765 6.78 0.765 6.78 0.28 6.1 0.28 6.1 0.765 5.4 0.765 5.4 0.28 5.18 0.28 5.18 0.765 4.48 0.765 4.48 0.28 3.8 0.28 3.8 0.765 3.1 0.765 3.1 0.28 2.88 0.28 2.88 0.765 2.18 0.765 2.18 0.28 0.28 0.28 0.28 86.76 19.2 86.76 19.2 86.275 19.9 86.275 19.9 86.76 24.72 86.76 24.72 86.275 25.42 86.275 25.42 86.76 28.4 86.76 28.4 86.275 29.1 86.275 29.1 86.76 ; @@ -1374,32 +1376,38 @@ MACRO cbx_1__2_ POLYGON 64.64 85.44 64.64 77.32 61.44 77.32 61.44 70.92 64.64 70.92 64.64 56.92 61.44 56.92 61.44 50.52 64.64 50.52 64.64 36.52 61.44 36.52 61.44 30.12 64.64 30.12 64.64 16.12 61.44 16.12 61.44 9.72 64.64 9.72 64.64 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; LAYER met1 ; RECT 45.68 86.8 46.32 87.28 ; + RECT 57.57 86.4 57.89 86.66 ; + POLYGON 28.91 86.66 28.91 86.6 30.2 86.6 30.2 86.12 30.06 86.12 30.06 86.46 28.91 86.46 28.91 86.4 28.59 86.4 28.59 86.66 ; + POLYGON 22.93 86.66 22.93 86.6 27.9 86.6 27.9 86.12 27.76 86.12 27.76 86.46 22.93 86.46 22.93 86.4 22.61 86.4 22.61 86.66 ; + RECT 19.39 86.4 19.71 86.66 ; + RECT 5.13 86.4 5.45 86.66 ; + POLYGON 15.94 1.26 15.94 0.44 5.91 0.44 5.91 0.38 5.59 0.38 5.59 0.64 5.91 0.64 5.91 0.58 15.8 0.58 15.8 1.26 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 86.76 46.32 86.52 65.96 86.52 65.96 84.84 65.48 84.84 65.48 83.8 65.96 83.8 65.96 82.12 65.48 82.12 65.48 81.08 65.96 81.08 65.96 79.4 65.48 79.4 65.48 78.36 65.96 78.36 65.96 76.68 65.48 76.68 65.48 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 45.68 86.52 45.68 86.76 ; LAYER li1 ; - RECT 0 86.955 66.24 87.125 ; - RECT 62.56 84.235 66.24 84.405 ; + POLYGON 66.24 87.125 66.24 86.955 60.655 86.955 60.655 86.575 60.325 86.575 60.325 86.955 59.715 86.955 59.715 86.23 59.425 86.23 59.425 86.955 58.515 86.955 58.515 86.42 58.005 86.42 58.005 86.955 56.045 86.955 56.045 86.555 55.715 86.555 55.715 86.955 52.355 86.955 52.355 86.23 52.065 86.23 52.065 86.955 50.545 86.955 50.545 86.555 50.215 86.555 50.215 86.955 48.255 86.955 48.255 86.42 47.745 86.42 47.745 86.955 46.235 86.955 46.235 86.48 46.065 86.48 46.065 86.955 45.385 86.955 45.385 86.48 45.215 86.48 45.215 86.955 44.515 86.955 44.515 86.475 44.345 86.475 44.345 86.955 43.515 86.955 43.515 86.425 43.345 86.425 43.345 86.955 41.49 86.955 41.49 86.455 41.12 86.455 41.12 86.955 39.425 86.955 39.425 86.495 39.175 86.495 39.175 86.955 38.565 86.955 38.565 86.575 38.235 86.575 38.235 86.955 37.635 86.955 37.635 86.23 37.345 86.23 37.345 86.955 32.955 86.955 32.955 86.555 32.625 86.555 32.625 86.955 32.115 86.955 32.115 86.555 31.785 86.555 31.785 86.955 30.37 86.955 30.37 86.445 29.955 86.445 29.955 86.955 28.465 86.955 28.465 86.445 28.05 86.445 28.05 86.955 26.635 86.955 26.635 86.555 26.305 86.555 26.305 86.955 25.795 86.955 25.795 86.555 25.465 86.555 25.465 86.955 22.455 86.955 22.455 86.23 22.165 86.23 22.165 86.955 21.825 86.955 21.825 86.495 21.57 86.495 21.57 86.955 20.9 86.955 20.9 86.495 20.73 86.495 20.73 86.955 20.06 86.955 20.06 86.495 19.89 86.495 19.89 86.955 19.22 86.955 19.22 86.495 19.05 86.495 19.05 86.955 18.38 86.955 18.38 86.495 18.075 86.495 18.075 86.955 16.335 86.955 16.335 86.48 16.165 86.48 16.165 86.955 15.485 86.955 15.485 86.48 15.315 86.48 15.315 86.955 14.615 86.955 14.615 86.475 14.445 86.475 14.445 86.955 13.615 86.955 13.615 86.425 13.445 86.425 13.445 86.955 11.59 86.955 11.59 86.455 11.22 86.455 11.22 86.955 9.525 86.955 9.525 86.495 9.275 86.495 9.275 86.955 8.665 86.955 8.665 86.575 8.335 86.575 8.335 86.955 7.735 86.955 7.735 86.23 7.445 86.23 7.445 86.955 6.075 86.955 6.075 86.42 5.565 86.42 5.565 86.955 3.605 86.955 3.605 86.555 3.275 86.555 3.275 86.955 0 86.955 0 87.125 ; + RECT 65.32 84.235 66.24 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 62.56 81.515 66.24 81.685 ; - RECT 0 81.515 1.84 81.685 ; + RECT 65.32 81.515 66.24 81.685 ; + RECT 0 81.515 3.68 81.685 ; RECT 65.32 78.795 66.24 78.965 ; RECT 0 78.795 1.84 78.965 ; RECT 65.32 76.075 66.24 76.245 ; RECT 0 76.075 1.84 76.245 ; RECT 65.32 73.355 66.24 73.525 ; - RECT 0 73.355 3.68 73.525 ; + RECT 0 73.355 1.84 73.525 ; RECT 65.32 70.635 66.24 70.805 ; RECT 0 70.635 3.68 70.805 ; RECT 65.32 67.915 66.24 68.085 ; - RECT 0 67.915 1.84 68.085 ; + RECT 0 67.915 3.68 68.085 ; RECT 65.32 65.195 66.24 65.365 ; - RECT 0 65.195 3.68 65.365 ; + RECT 0 65.195 1.84 65.365 ; RECT 65.32 62.475 66.24 62.645 ; RECT 0 62.475 3.68 62.645 ; RECT 65.32 59.755 66.24 59.925 ; RECT 0 59.755 3.68 59.925 ; RECT 65.32 57.035 66.24 57.205 ; - RECT 0 57.035 3.68 57.205 ; + RECT 0 57.035 1.84 57.205 ; RECT 65.32 54.315 66.24 54.485 ; RECT 0 54.315 1.84 54.485 ; RECT 65.32 51.595 66.24 51.765 ; @@ -1411,9 +1419,9 @@ MACRO cbx_1__2_ RECT 65.32 43.435 66.24 43.605 ; RECT 0 43.435 3.68 43.605 ; RECT 65.32 40.715 66.24 40.885 ; - RECT 0 40.715 1.84 40.885 ; + RECT 0 40.715 3.68 40.885 ; RECT 65.32 37.995 66.24 38.165 ; - RECT 0 37.995 1.84 38.165 ; + RECT 0 37.995 3.68 38.165 ; RECT 65.32 35.275 66.24 35.445 ; RECT 0 35.275 3.68 35.445 ; RECT 65.32 32.555 66.24 32.725 ; @@ -1423,34 +1431,46 @@ MACRO cbx_1__2_ RECT 65.32 27.115 66.24 27.285 ; RECT 0 27.115 3.68 27.285 ; RECT 65.32 24.395 66.24 24.565 ; - RECT 0 24.395 1.84 24.565 ; + RECT 0 24.395 3.68 24.565 ; RECT 65.32 21.675 66.24 21.845 ; - RECT 0 21.675 1.84 21.845 ; + RECT 0 21.675 3.68 21.845 ; RECT 65.32 18.955 66.24 19.125 ; RECT 0 18.955 3.68 19.125 ; RECT 65.32 16.235 66.24 16.405 ; RECT 0 16.235 3.68 16.405 ; RECT 65.32 13.515 66.24 13.685 ; - RECT 0 13.515 1.84 13.685 ; + RECT 0 13.515 3.68 13.685 ; RECT 65.32 10.795 66.24 10.965 ; RECT 0 10.795 3.68 10.965 ; RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 65.78 5.355 66.24 5.525 ; - RECT 0 5.355 1.84 5.525 ; - RECT 62.56 2.635 66.24 2.805 ; + RECT 65.32 5.355 66.24 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; + POLYGON 57.865 0.885 57.865 0.085 59.425 0.085 59.425 0.81 59.715 0.81 59.715 0.085 66.24 0.085 66.24 -0.085 0 -0.085 0 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 9.295 0.085 9.295 0.885 9.625 0.885 9.625 0.085 10.135 0.085 10.135 0.565 10.465 0.565 10.465 0.085 10.975 0.085 10.975 0.565 11.305 0.565 11.305 0.085 11.895 0.085 11.895 0.565 12.065 0.565 12.065 0.085 12.735 0.085 12.735 0.565 12.905 0.565 12.905 0.085 14.815 0.085 14.815 0.885 15.145 0.885 15.145 0.085 15.655 0.085 15.655 0.565 15.985 0.565 15.985 0.085 16.495 0.085 16.495 0.565 16.825 0.565 16.825 0.085 17.415 0.085 17.415 0.565 17.585 0.565 17.585 0.085 18.255 0.085 18.255 0.565 18.425 0.565 18.425 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 22.975 0.085 22.975 0.565 23.145 0.565 23.145 0.085 23.815 0.085 23.815 0.565 23.985 0.565 23.985 0.085 24.575 0.085 24.575 0.565 24.905 0.565 24.905 0.085 25.415 0.085 25.415 0.565 25.745 0.565 25.745 0.085 26.255 0.085 26.255 0.885 26.585 0.885 26.585 0.085 29.535 0.085 29.535 0.885 29.865 0.885 29.865 0.085 30.375 0.085 30.375 0.565 30.705 0.565 30.705 0.085 31.215 0.085 31.215 0.565 31.545 0.565 31.545 0.085 32.135 0.085 32.135 0.565 32.305 0.565 32.305 0.085 32.975 0.085 32.975 0.565 33.145 0.565 33.145 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 37.975 0.085 37.975 0.545 38.23 0.545 38.23 0.085 38.9 0.085 38.9 0.545 39.07 0.545 39.07 0.085 39.74 0.085 39.74 0.545 39.91 0.545 39.91 0.085 40.58 0.085 40.58 0.545 40.75 0.545 40.75 0.085 41.42 0.085 41.42 0.545 41.725 0.545 41.725 0.085 41.955 0.085 41.955 0.885 42.285 0.885 42.285 0.085 42.795 0.085 42.795 0.565 43.125 0.565 43.125 0.085 43.635 0.085 43.635 0.565 43.965 0.565 43.965 0.085 44.555 0.085 44.555 0.565 44.725 0.565 44.725 0.085 45.395 0.085 45.395 0.565 45.565 0.565 45.565 0.085 47.475 0.085 47.475 0.885 47.805 0.885 47.805 0.085 48.315 0.085 48.315 0.565 48.645 0.565 48.645 0.085 49.155 0.085 49.155 0.565 49.485 0.565 49.485 0.085 50.075 0.085 50.075 0.565 50.245 0.565 50.245 0.085 50.915 0.085 50.915 0.565 51.085 0.565 51.085 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 54.255 0.085 54.255 0.565 54.425 0.565 54.425 0.085 55.095 0.085 55.095 0.565 55.265 0.565 55.265 0.085 55.855 0.085 55.855 0.565 56.185 0.565 56.185 0.085 56.695 0.085 56.695 0.565 57.025 0.565 57.025 0.085 57.535 0.085 57.535 0.885 ; RECT 0.17 0.17 66.07 86.87 ; + LAYER mcon ; + RECT 57.645 86.445 57.815 86.615 ; + RECT 19.465 86.445 19.635 86.615 ; + RECT 5.205 86.445 5.375 86.615 ; LAYER via ; RECT 55.125 86.965 55.275 87.115 ; RECT 25.685 86.965 25.835 87.115 ; + RECT 57.655 86.455 57.805 86.605 ; + RECT 28.675 86.455 28.825 86.605 ; + RECT 22.695 86.455 22.845 86.605 ; + RECT 19.475 86.455 19.625 86.605 ; + RECT 5.215 86.455 5.365 86.605 ; + RECT 5.675 0.435 5.825 0.585 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 86.94 55.3 87.14 ; RECT 25.66 86.94 25.86 87.14 ; - RECT 64.99 43.08 65.19 43.28 ; + RECT 64.99 62.12 65.19 62.32 ; + RECT 1.05 56 1.25 56.2 ; + RECT 64.99 36.28 65.19 36.48 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/cby_0__1__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/cby_0__1__icv_in_design.lef index 7b06400..fed0166 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/cby_0__1__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/cby_0__1__icv_in_design.lef @@ -1182,6 +1182,10 @@ MACRO cby_0__1_ LAYER met2 ; RECT 55.06 75.975 55.34 76.345 ; RECT 25.62 75.975 25.9 76.345 ; + POLYGON 39.9 76.06 39.9 75.92 39.86 75.92 39.86 71.84 39.72 71.84 39.72 76.06 ; + POLYGON 11.8 76.06 11.8 47.7 11.66 47.7 11.66 75.92 11.62 75.92 11.62 76.06 ; + RECT 36.9 75.15 37.16 75.47 ; + POLYGON 39.86 6.7 39.86 0.24 39.9 0.24 39.9 0.1 39.72 0.1 39.72 6.7 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; POLYGON 65.96 75.88 65.96 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 61.3 0.28 61.3 0.765 60.6 0.765 60.6 0.28 60.38 0.28 60.38 0.765 59.68 0.765 59.68 0.28 59.46 0.28 59.46 0.765 58.76 0.765 58.76 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 53.94 0.28 53.94 0.765 53.24 0.765 53.24 0.28 53.02 0.28 53.02 0.765 52.32 0.765 52.32 0.28 52.1 0.28 52.1 0.765 51.4 0.765 51.4 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 50.26 0.28 50.26 0.765 49.56 0.765 49.56 0.28 49.34 0.28 49.34 0.765 48.64 0.765 48.64 0.28 48.42 0.28 48.42 0.765 47.72 0.765 47.72 0.28 47.5 0.28 47.5 0.765 46.8 0.765 46.8 0.28 43.36 0.28 43.36 0.765 42.66 0.765 42.66 0.28 42.44 0.28 42.44 0.765 41.74 0.765 41.74 0.28 41.52 0.28 41.52 0.765 40.82 0.765 40.82 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 37.84 0.28 37.84 0.765 37.14 0.765 37.14 0.28 36.92 0.28 36.92 0.765 36.22 0.765 36.22 0.28 36 0.28 36 0.765 35.3 0.765 35.3 0.28 35.08 0.28 35.08 0.765 34.38 0.765 34.38 0.28 34.16 0.28 34.16 0.765 33.46 0.765 33.46 0.28 33.24 0.28 33.24 0.765 32.54 0.765 32.54 0.28 32.32 0.28 32.32 0.765 31.62 0.765 31.62 0.28 31.4 0.28 31.4 0.765 30.7 0.765 30.7 0.28 26.8 0.28 26.8 0.765 26.1 0.765 26.1 0.28 25.42 0.28 25.42 0.765 24.72 0.765 24.72 0.28 18.98 0.28 18.98 0.765 18.28 0.765 18.28 0.28 18.06 0.28 18.06 0.765 17.36 0.765 17.36 0.28 17.14 0.28 17.14 0.765 16.44 0.765 16.44 0.28 16.22 0.28 16.22 0.765 15.52 0.765 15.52 0.28 15.3 0.28 15.3 0.765 14.6 0.765 14.6 0.28 14.38 0.28 14.38 0.765 13.68 0.765 13.68 0.28 13.46 0.28 13.46 0.765 12.76 0.765 12.76 0.28 0.28 0.28 0.28 75.88 2.18 75.88 2.18 75.395 2.88 75.395 2.88 75.88 8.16 75.88 8.16 75.395 8.86 75.395 8.86 75.88 9.08 75.88 9.08 75.395 9.78 75.395 9.78 75.88 10 75.88 10 75.395 10.7 75.395 10.7 75.88 10.92 75.88 10.92 75.395 11.62 75.395 11.62 75.88 11.84 75.88 11.84 75.395 12.54 75.395 12.54 75.88 12.76 75.88 12.76 75.395 13.46 75.395 13.46 75.88 13.68 75.88 13.68 75.395 14.38 75.395 14.38 75.88 14.6 75.88 14.6 75.395 15.3 75.395 15.3 75.88 15.52 75.88 15.52 75.395 16.22 75.395 16.22 75.88 16.44 75.88 16.44 75.395 17.14 75.395 17.14 75.88 17.36 75.88 17.36 75.395 18.06 75.395 18.06 75.88 18.28 75.88 18.28 75.395 18.98 75.395 18.98 75.88 19.2 75.88 19.2 75.395 19.9 75.395 19.9 75.88 20.12 75.88 20.12 75.395 20.82 75.395 20.82 75.88 21.04 75.88 21.04 75.395 21.74 75.395 21.74 75.88 26.1 75.88 26.1 75.395 26.8 75.395 26.8 75.88 32.54 75.88 32.54 75.395 33.24 75.395 33.24 75.88 33.46 75.88 33.46 75.395 34.16 75.395 34.16 75.88 34.38 75.88 34.38 75.395 35.08 75.395 35.08 75.88 35.3 75.88 35.3 75.395 36 75.395 36 75.88 36.22 75.88 36.22 75.395 36.92 75.395 36.92 75.88 37.14 75.88 37.14 75.395 37.84 75.395 37.84 75.88 38.06 75.88 38.06 75.395 38.76 75.395 38.76 75.88 38.98 75.88 38.98 75.395 39.68 75.395 39.68 75.88 39.9 75.88 39.9 75.395 40.6 75.395 40.6 75.88 40.82 75.88 40.82 75.395 41.52 75.395 41.52 75.88 49.56 75.88 49.56 75.395 50.26 75.395 50.26 75.88 50.48 75.88 50.48 75.395 51.18 75.395 51.18 75.88 51.4 75.88 51.4 75.395 52.1 75.395 52.1 75.88 52.32 75.88 52.32 75.395 53.02 75.395 53.02 75.88 53.24 75.88 53.24 75.395 53.94 75.395 53.94 75.88 54.16 75.88 54.16 75.395 54.86 75.395 54.86 75.88 56 75.88 56 75.395 56.7 75.395 56.7 75.88 56.92 75.88 56.92 75.395 57.62 75.395 57.62 75.88 57.84 75.88 57.84 75.395 58.54 75.395 58.54 75.88 58.76 75.88 58.76 75.395 59.46 75.395 59.46 75.88 59.68 75.88 59.68 75.395 60.38 75.395 60.38 75.88 60.6 75.88 60.6 75.395 61.3 75.395 61.3 75.88 61.52 75.88 61.52 75.395 62.22 75.395 62.22 75.88 62.44 75.88 62.44 75.395 63.14 75.395 63.14 75.88 63.36 75.88 63.36 75.395 64.06 75.395 64.06 75.88 ; @@ -1200,42 +1204,42 @@ MACRO cby_0__1_ RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 75.88 46.32 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 45.68 75.64 45.68 75.88 ; LAYER li1 ; - RECT 0 76.075 66.24 76.245 ; - RECT 62.56 73.355 66.24 73.525 ; + POLYGON 66.24 76.245 66.24 76.075 59.715 76.075 59.715 75.35 59.425 75.35 59.425 76.075 52.355 76.075 52.355 75.35 52.065 75.35 52.065 76.075 37.635 76.075 37.635 75.35 37.345 75.35 37.345 76.075 22.455 76.075 22.455 75.35 22.165 75.35 22.165 76.075 16.005 76.075 16.005 75.275 15.675 75.275 15.675 76.075 15.165 76.075 15.165 75.595 14.835 75.595 14.835 76.075 14.325 76.075 14.325 75.595 13.995 75.595 13.995 76.075 13.405 76.075 13.405 75.595 13.235 75.595 13.235 76.075 12.565 76.075 12.565 75.595 12.395 75.595 12.395 76.075 7.735 76.075 7.735 75.35 7.445 75.35 7.445 76.075 0 76.075 0 76.245 ; + RECT 65.32 73.355 66.24 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 65.78 70.635 66.24 70.805 ; + RECT 65.32 70.635 66.24 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 65.78 67.915 66.24 68.085 ; + RECT 65.32 67.915 66.24 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 64.4 65.195 66.24 65.365 ; + RECT 65.32 65.195 66.24 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 64.4 62.475 66.24 62.645 ; + RECT 65.32 62.475 66.24 62.645 ; RECT 0 62.475 3.68 62.645 ; RECT 65.32 59.755 66.24 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 64.4 57.035 66.24 57.205 ; + RECT 65.32 57.035 66.24 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 64.4 54.315 66.24 54.485 ; + RECT 65.32 54.315 66.24 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 65.78 51.595 66.24 51.765 ; + RECT 65.32 51.595 66.24 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 65.78 48.875 66.24 49.045 ; + RECT 65.32 48.875 66.24 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 65.78 46.155 66.24 46.325 ; + RECT 65.32 46.155 66.24 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 62.56 43.435 66.24 43.605 ; + RECT 65.32 43.435 66.24 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 62.56 40.715 66.24 40.885 ; + RECT 65.32 40.715 66.24 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 64.4 37.995 66.24 38.165 ; + RECT 65.32 37.995 66.24 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 62.56 35.275 66.24 35.445 ; + RECT 65.32 35.275 66.24 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 62.56 32.555 66.24 32.725 ; + RECT 65.32 32.555 66.24 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 62.56 29.835 66.24 30.005 ; + RECT 65.32 29.835 66.24 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 62.56 27.115 66.24 27.285 ; + RECT 65.32 27.115 66.24 27.285 ; RECT 0 27.115 3.68 27.285 ; RECT 65.32 24.395 66.24 24.565 ; RECT 0 24.395 3.68 24.565 ; @@ -1243,7 +1247,7 @@ MACRO cby_0__1_ RECT 0 21.675 3.68 21.845 ; RECT 65.32 18.955 66.24 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 65.78 16.235 66.24 16.405 ; + RECT 65.32 16.235 66.24 16.405 ; RECT 0 16.235 3.68 16.405 ; RECT 65.32 13.515 66.24 13.685 ; RECT 0 13.515 3.68 13.685 ; @@ -1253,9 +1257,9 @@ MACRO cby_0__1_ RECT 0 8.075 3.68 8.245 ; RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 62.56 2.635 66.24 2.805 ; + RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; + POLYGON 57.865 0.885 57.865 0.085 59.425 0.085 59.425 0.81 59.715 0.81 59.715 0.085 66.24 0.085 66.24 -0.085 0 -0.085 0 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 22.975 0.085 22.975 0.565 23.145 0.565 23.145 0.085 23.815 0.085 23.815 0.565 23.985 0.565 23.985 0.085 24.575 0.085 24.575 0.565 24.905 0.565 24.905 0.085 25.415 0.085 25.415 0.565 25.745 0.565 25.745 0.085 26.255 0.085 26.255 0.885 26.585 0.885 26.585 0.085 31.715 0.085 31.715 0.565 31.885 0.565 31.885 0.085 32.555 0.085 32.555 0.565 32.725 0.565 32.725 0.085 33.315 0.085 33.315 0.565 33.645 0.565 33.645 0.085 34.155 0.085 34.155 0.565 34.485 0.565 34.485 0.085 34.995 0.085 34.995 0.885 35.325 0.885 35.325 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 38.155 0.085 38.155 0.565 38.325 0.565 38.325 0.085 38.995 0.085 38.995 0.565 39.165 0.565 39.165 0.085 39.755 0.085 39.755 0.565 40.085 0.565 40.085 0.085 40.595 0.085 40.595 0.565 40.925 0.565 40.925 0.085 41.435 0.085 41.435 0.885 41.765 0.885 41.765 0.085 46.935 0.085 46.935 0.885 47.265 0.885 47.265 0.085 47.775 0.085 47.775 0.565 48.105 0.565 48.105 0.085 48.615 0.085 48.615 0.565 48.945 0.565 48.945 0.085 49.455 0.085 49.455 0.565 49.785 0.565 49.785 0.085 50.295 0.085 50.295 0.565 50.625 0.565 50.625 0.085 51.135 0.085 51.135 0.565 51.465 0.565 51.465 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 54.255 0.085 54.255 0.565 54.425 0.565 54.425 0.085 55.095 0.085 55.095 0.565 55.265 0.565 55.265 0.085 55.855 0.085 55.855 0.565 56.185 0.565 56.185 0.085 56.695 0.085 56.695 0.565 57.025 0.565 57.025 0.085 57.535 0.085 57.535 0.885 ; RECT 0.17 0.17 66.07 75.99 ; LAYER via ; RECT 55.125 76.085 55.275 76.235 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/cby_1__1__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/cby_1__1__icv_in_design.lef index c831c57..b5eb0a2 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/cby_1__1__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/cby_1__1__icv_in_design.lef @@ -1438,13 +1438,21 @@ MACRO cby_1__1_ LAYER met2 ; RECT 55.06 75.975 55.34 76.345 ; RECT 25.62 75.975 25.9 76.345 ; + POLYGON 10.46 76.06 10.46 75.92 10.42 75.92 10.42 72.35 10.28 72.35 10.28 76.06 ; + RECT 9.3 75.49 9.56 75.81 ; + RECT 49.78 75.15 50.04 75.47 ; + RECT 42.42 75.15 42.68 75.47 ; + POLYGON 28.36 7.38 28.36 0.1 27.72 0.1 27.72 0.24 28.22 0.24 28.22 7.38 ; + RECT 60.82 0.35 61.08 0.67 ; + RECT 39.2 0.35 39.46 0.67 ; + RECT 14.35 0.155 14.63 0.525 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; POLYGON 65.96 75.88 65.96 0.28 63.6 0.28 63.6 0.765 62.9 0.765 62.9 0.28 62.68 0.28 62.68 0.765 61.98 0.765 61.98 0.28 61.76 0.28 61.76 0.765 61.06 0.765 61.06 0.28 60.84 0.28 60.84 0.765 60.14 0.765 60.14 0.28 59.92 0.28 59.92 0.765 59.22 0.765 59.22 0.28 59 0.28 59 0.765 58.3 0.765 58.3 0.28 58.08 0.28 58.08 0.765 57.38 0.765 57.38 0.28 57.16 0.28 57.16 0.765 56.46 0.765 56.46 0.28 56.24 0.28 56.24 0.765 55.54 0.765 55.54 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 53.94 0.28 53.94 0.765 53.24 0.765 53.24 0.28 53.02 0.28 53.02 0.765 52.32 0.765 52.32 0.28 52.1 0.28 52.1 0.765 51.4 0.765 51.4 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 50.26 0.28 50.26 0.765 49.56 0.765 49.56 0.28 49.34 0.28 49.34 0.765 48.64 0.765 48.64 0.28 48.42 0.28 48.42 0.765 47.72 0.765 47.72 0.28 47.04 0.28 47.04 0.765 46.34 0.765 46.34 0.28 45.66 0.28 45.66 0.765 44.96 0.765 44.96 0.28 44.74 0.28 44.74 0.765 44.04 0.765 44.04 0.28 43.82 0.28 43.82 0.765 43.12 0.765 43.12 0.28 42.9 0.28 42.9 0.765 42.2 0.765 42.2 0.28 41.98 0.28 41.98 0.765 41.28 0.765 41.28 0.28 41.06 0.28 41.06 0.765 40.36 0.765 40.36 0.28 40.14 0.28 40.14 0.765 39.44 0.765 39.44 0.28 39.22 0.28 39.22 0.765 38.52 0.765 38.52 0.28 37.84 0.28 37.84 0.765 37.14 0.765 37.14 0.28 36.92 0.28 36.92 0.765 36.22 0.765 36.22 0.28 36 0.28 36 0.765 35.3 0.765 35.3 0.28 35.08 0.28 35.08 0.765 34.38 0.765 34.38 0.28 34.16 0.28 34.16 0.765 33.46 0.765 33.46 0.28 33.24 0.28 33.24 0.765 32.54 0.765 32.54 0.28 32.32 0.28 32.32 0.765 31.62 0.765 31.62 0.28 31.4 0.28 31.4 0.765 30.7 0.765 30.7 0.28 30.02 0.28 30.02 0.765 29.32 0.765 29.32 0.28 29.1 0.28 29.1 0.765 28.4 0.765 28.4 0.28 27.72 0.28 27.72 0.765 27.02 0.765 27.02 0.28 26.8 0.28 26.8 0.765 26.1 0.765 26.1 0.28 13.92 0.28 13.92 0.765 13.22 0.765 13.22 0.28 13 0.28 13 0.765 12.3 0.765 12.3 0.28 0.28 0.28 0.28 75.88 6.78 75.88 6.78 75.395 7.48 75.395 7.48 75.88 7.7 75.88 7.7 75.395 8.4 75.395 8.4 75.88 8.62 75.88 8.62 75.395 9.32 75.395 9.32 75.88 9.54 75.88 9.54 75.395 10.24 75.395 10.24 75.88 10.46 75.88 10.46 75.395 11.16 75.395 11.16 75.88 11.38 75.88 11.38 75.395 12.08 75.395 12.08 75.88 12.3 75.88 12.3 75.395 13 75.395 13 75.88 13.22 75.88 13.22 75.395 13.92 75.395 13.92 75.88 14.14 75.88 14.14 75.395 14.84 75.395 14.84 75.88 26.1 75.88 26.1 75.395 26.8 75.395 26.8 75.88 27.02 75.88 27.02 75.395 27.72 75.395 27.72 75.88 27.94 75.88 27.94 75.395 28.64 75.395 28.64 75.88 28.86 75.88 28.86 75.395 29.56 75.395 29.56 75.88 29.78 75.88 29.78 75.395 30.48 75.395 30.48 75.88 30.7 75.88 30.7 75.395 31.4 75.395 31.4 75.88 31.62 75.88 31.62 75.395 32.32 75.395 32.32 75.88 32.54 75.88 32.54 75.395 33.24 75.395 33.24 75.88 33.46 75.88 33.46 75.395 34.16 75.395 34.16 75.88 34.38 75.88 34.38 75.395 35.08 75.395 35.08 75.88 35.3 75.88 35.3 75.395 36 75.395 36 75.88 36.22 75.88 36.22 75.395 36.92 75.395 36.92 75.88 37.14 75.88 37.14 75.395 37.84 75.395 37.84 75.88 38.06 75.88 38.06 75.395 38.76 75.395 38.76 75.88 38.98 75.88 38.98 75.395 39.68 75.395 39.68 75.88 39.9 75.88 39.9 75.395 40.6 75.395 40.6 75.88 40.82 75.88 40.82 75.395 41.52 75.395 41.52 75.88 41.74 75.88 41.74 75.395 42.44 75.395 42.44 75.88 43.12 75.88 43.12 75.395 43.82 75.395 43.82 75.88 44.04 75.88 44.04 75.395 44.74 75.395 44.74 75.88 44.96 75.88 44.96 75.395 45.66 75.395 45.66 75.88 46.34 75.88 46.34 75.395 47.04 75.395 47.04 75.88 47.26 75.88 47.26 75.395 47.96 75.395 47.96 75.88 48.18 75.88 48.18 75.395 48.88 75.395 48.88 75.88 49.1 75.88 49.1 75.395 49.8 75.395 49.8 75.88 50.02 75.88 50.02 75.395 50.72 75.395 50.72 75.88 50.94 75.88 50.94 75.395 51.64 75.395 51.64 75.88 52.32 75.88 52.32 75.395 53.02 75.395 53.02 75.88 53.24 75.88 53.24 75.395 53.94 75.395 53.94 75.88 54.16 75.88 54.16 75.395 54.86 75.395 54.86 75.88 55.54 75.88 55.54 75.395 56.24 75.395 56.24 75.88 56.46 75.88 56.46 75.395 57.16 75.395 57.16 75.88 57.38 75.88 57.38 75.395 58.08 75.395 58.08 75.88 58.3 75.88 58.3 75.395 59 75.395 59 75.88 59.22 75.88 59.22 75.395 59.92 75.395 59.92 75.88 60.14 75.88 60.14 75.395 60.84 75.395 60.84 75.88 61.52 75.88 61.52 75.395 62.22 75.395 62.22 75.88 62.44 75.88 62.44 75.395 63.14 75.395 63.14 75.88 63.36 75.88 63.36 75.395 64.06 75.395 64.06 75.88 ; LAYER met3 ; POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; - POLYGON 53.28 75.97 53.28 74.31 52.98 74.31 52.98 75.67 36.49 75.67 36.49 74.31 36.19 74.31 36.19 75.97 ; + POLYGON 14.655 0.505 14.655 0.175 14.325 0.175 14.325 0.19 12.815 0.19 12.815 0.175 12.485 0.175 12.485 0.505 12.815 0.505 12.815 0.49 14.325 0.49 14.325 0.505 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; POLYGON 65.84 75.76 65.84 38.97 65.04 38.97 65.04 37.87 65.84 37.87 65.84 35.57 65.04 35.57 65.04 34.47 65.84 34.47 65.84 24.69 65.04 24.69 65.04 23.59 65.84 23.59 65.84 0.4 0.4 0.4 0.4 3.19 1.2 3.19 1.2 4.29 0.4 4.29 0.4 4.55 1.2 4.55 1.2 5.65 0.4 5.65 0.4 5.91 1.2 5.91 1.2 7.01 0.4 7.01 0.4 7.27 1.2 7.27 1.2 8.37 0.4 8.37 0.4 8.63 1.2 8.63 1.2 9.73 0.4 9.73 0.4 9.99 1.2 9.99 1.2 11.09 0.4 11.09 0.4 18.83 1.2 18.83 1.2 19.93 0.4 19.93 0.4 20.19 1.2 20.19 1.2 21.29 0.4 21.29 0.4 21.55 1.2 21.55 1.2 22.65 0.4 22.65 0.4 22.91 1.2 22.91 1.2 24.01 0.4 24.01 0.4 24.27 1.2 24.27 1.2 25.37 0.4 25.37 0.4 25.63 1.2 25.63 1.2 26.73 0.4 26.73 0.4 33.11 1.2 33.11 1.2 34.21 0.4 34.21 0.4 34.47 1.2 34.47 1.2 35.57 0.4 35.57 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 75.76 ; @@ -1454,12 +1462,21 @@ MACRO cby_1__1_ POLYGON 64.64 74.56 64.64 71.88 61.44 71.88 61.44 65.48 64.64 65.48 64.64 51.48 61.44 51.48 61.44 45.08 64.64 45.08 64.64 31.08 61.44 31.08 61.44 24.68 64.64 24.68 64.64 10.68 61.44 10.68 61.44 4.28 64.64 4.28 64.64 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; LAYER met1 ; RECT 45.68 75.92 46.32 76.4 ; + POLYGON 38.57 75.78 38.57 75.72 53.2 75.72 53.2 74.9 53.06 74.9 53.06 75.58 38.57 75.58 38.57 75.52 38.25 75.52 38.25 75.78 ; + POLYGON 12.81 75.78 12.81 75.52 12.72 75.52 12.72 74.9 12.58 74.9 12.58 75.52 12.49 75.52 12.49 75.78 ; + POLYGON 9.59 75.78 9.59 75.52 9.27 75.52 9.27 75.58 8.41 75.58 8.41 75.535 8.12 75.535 8.12 75.765 8.41 75.765 8.41 75.72 9.27 75.72 9.27 75.78 ; + POLYGON 43.54 1.26 43.54 0.64 43.63 0.64 43.63 0.38 43.31 0.38 43.31 0.64 43.4 0.64 43.4 1.26 ; + RECT 14.33 0.51 14.65 0.83 ; + RECT 4.21 0.44 4.53 0.76 ; + POLYGON 61.11 0.64 61.11 0.38 60.79 0.38 60.79 0.44 52.815 0.44 52.815 0.395 52.525 0.395 52.525 0.625 52.815 0.625 52.815 0.58 60.79 0.58 60.79 0.64 ; + POLYGON 40.87 0.64 40.87 0.38 40.55 0.38 40.55 0.44 39.49 0.44 39.49 0.38 39.17 0.38 39.17 0.64 39.49 0.64 39.49 0.58 40.55 0.58 40.55 0.64 ; + POLYGON 10.51 0.64 10.51 0.38 10.19 0.38 10.19 0.395 9.805 0.395 9.805 0.625 10.19 0.625 10.19 0.64 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 75.88 46.32 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 45.68 75.64 45.68 75.88 ; LAYER li1 ; - RECT 0 76.075 66.24 76.245 ; - RECT 62.56 73.355 66.24 73.525 ; - RECT 0 73.355 3.68 73.525 ; + POLYGON 66.24 76.245 66.24 76.075 59.715 76.075 59.715 75.35 59.425 75.35 59.425 76.075 58.815 76.075 58.815 75.695 58.485 75.695 58.485 76.075 57.485 76.075 57.485 75.275 57.155 75.275 57.155 76.075 56.645 76.075 56.645 75.595 56.315 75.595 56.315 76.075 55.805 76.075 55.805 75.595 55.475 75.595 55.475 76.075 54.965 76.075 54.965 75.595 54.635 75.595 54.635 76.075 54.125 76.075 54.125 75.595 53.795 75.595 53.795 76.075 53.285 76.075 53.285 75.595 52.955 75.595 52.955 76.075 52.355 76.075 52.355 75.35 52.065 75.35 52.065 76.075 51.465 76.075 51.465 75.675 51.135 75.675 51.135 76.075 49.175 76.075 49.175 75.54 48.665 75.54 48.665 76.075 47.325 76.075 47.325 75.595 46.995 75.595 46.995 76.075 46.485 76.075 46.485 75.595 46.155 75.595 46.155 76.075 45.645 76.075 45.645 75.595 45.315 75.595 45.315 76.075 44.805 76.075 44.805 75.595 44.475 75.595 44.475 76.075 43.965 76.075 43.965 75.595 43.635 75.595 43.635 76.075 43.125 76.075 43.125 75.275 42.795 75.275 42.795 76.075 41.885 76.075 41.885 75.595 41.715 75.595 41.715 76.075 41.045 76.075 41.045 75.595 40.875 75.595 40.875 76.075 40.285 76.075 40.285 75.595 39.955 75.595 39.955 76.075 39.445 76.075 39.445 75.595 39.115 75.595 39.115 76.075 38.605 76.075 38.605 75.275 38.275 75.275 38.275 76.075 37.635 76.075 37.635 75.35 37.345 75.35 37.345 76.075 36.735 76.075 36.735 75.595 36.495 75.595 36.495 76.075 35.905 76.075 35.905 75.595 35.575 75.595 35.575 76.075 35.065 76.075 35.065 75.275 34.735 75.275 34.735 76.075 34.025 76.075 34.025 75.275 33.695 75.275 33.695 76.075 33.185 76.075 33.185 75.595 32.855 75.595 32.855 76.075 32.345 76.075 32.345 75.595 32.015 75.595 32.015 76.075 31.505 76.075 31.505 75.595 31.175 75.595 31.175 76.075 30.665 76.075 30.665 75.595 30.335 75.595 30.335 76.075 29.825 76.075 29.825 75.595 29.495 75.595 29.495 76.075 27.545 76.075 27.545 75.595 27.215 75.595 27.215 76.075 26.705 76.075 26.705 75.595 26.375 75.595 26.375 76.075 25.865 76.075 25.865 75.595 25.535 75.595 25.535 76.075 25.025 76.075 25.025 75.595 24.695 75.595 24.695 76.075 24.185 76.075 24.185 75.595 23.855 75.595 23.855 76.075 23.345 76.075 23.345 75.275 23.015 75.275 23.015 76.075 22.455 76.075 22.455 75.35 22.165 75.35 22.165 76.075 19.765 76.075 19.765 75.275 19.435 75.275 19.435 76.075 18.925 76.075 18.925 75.595 18.595 75.595 18.595 76.075 18.085 76.075 18.085 75.595 17.755 75.595 17.755 76.075 17.245 76.075 17.245 75.595 16.915 75.595 16.915 76.075 16.405 76.075 16.405 75.595 16.075 75.595 16.075 76.075 15.565 76.075 15.565 75.595 15.235 75.595 15.235 76.075 14.205 76.075 14.205 75.595 13.875 75.595 13.875 76.075 13.365 76.075 13.365 75.595 13.035 75.595 13.035 76.075 12.525 76.075 12.525 75.595 12.195 75.595 12.195 76.075 11.685 76.075 11.685 75.595 11.355 75.595 11.355 76.075 10.845 76.075 10.845 75.595 10.515 75.595 10.515 76.075 10.005 76.075 10.005 75.275 9.675 75.275 9.675 76.075 8.88 76.075 8.88 75.255 8.65 75.255 8.65 76.075 7.735 76.075 7.735 75.35 7.445 75.35 7.445 76.075 6.845 76.075 6.845 75.675 6.515 75.675 6.515 76.075 4.555 76.075 4.555 75.54 4.045 75.54 4.045 76.075 0 76.075 0 76.245 ; + RECT 65.32 73.355 66.24 73.525 ; + RECT 0 73.355 1.84 73.525 ; RECT 65.32 70.635 66.24 70.805 ; RECT 0 70.635 1.84 70.805 ; RECT 65.32 67.915 66.24 68.085 ; @@ -1471,58 +1488,73 @@ MACRO cby_1__1_ RECT 65.32 59.755 66.24 59.925 ; RECT 0 59.755 1.84 59.925 ; RECT 65.32 57.035 66.24 57.205 ; - RECT 0 57.035 3.68 57.205 ; + RECT 0 57.035 1.84 57.205 ; RECT 65.32 54.315 66.24 54.485 ; - RECT 0 54.315 3.68 54.485 ; + RECT 0 54.315 1.84 54.485 ; RECT 65.32 51.595 66.24 51.765 ; - RECT 0 51.595 3.68 51.765 ; + RECT 0 51.595 1.84 51.765 ; RECT 65.32 48.875 66.24 49.045 ; RECT 0 48.875 1.84 49.045 ; RECT 65.32 46.155 66.24 46.325 ; - RECT 0 46.155 3.68 46.325 ; + RECT 0 46.155 1.84 46.325 ; RECT 65.32 43.435 66.24 43.605 ; RECT 0 43.435 3.68 43.605 ; RECT 65.32 40.715 66.24 40.885 ; - RECT 0 40.715 1.84 40.885 ; + RECT 0 40.715 3.68 40.885 ; RECT 65.32 37.995 66.24 38.165 ; RECT 0 37.995 1.84 38.165 ; RECT 65.32 35.275 66.24 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 62.56 32.555 66.24 32.725 ; + RECT 65.32 32.555 66.24 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 62.56 29.835 66.24 30.005 ; - RECT 0 29.835 3.68 30.005 ; + RECT 65.32 29.835 66.24 30.005 ; + RECT 0 29.835 1.84 30.005 ; RECT 65.32 27.115 66.24 27.285 ; - RECT 0 27.115 3.68 27.285 ; + RECT 0 27.115 1.84 27.285 ; RECT 65.32 24.395 66.24 24.565 ; - RECT 0 24.395 3.68 24.565 ; + RECT 0 24.395 1.84 24.565 ; RECT 65.32 21.675 66.24 21.845 ; - RECT 0 21.675 3.68 21.845 ; + RECT 0 21.675 1.84 21.845 ; RECT 65.32 18.955 66.24 19.125 ; RECT 0 18.955 1.84 19.125 ; RECT 65.32 16.235 66.24 16.405 ; RECT 0 16.235 1.84 16.405 ; RECT 65.32 13.515 66.24 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 62.56 10.795 66.24 10.965 ; - RECT 0 10.795 1.84 10.965 ; + RECT 65.32 10.795 66.24 10.965 ; + RECT 0 10.795 3.68 10.965 ; RECT 62.56 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; - RECT 0 5.355 3.68 5.525 ; + RECT 62.56 5.355 66.24 5.525 ; + RECT 0 5.355 1.84 5.525 ; RECT 62.56 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; + POLYGON 60.365 0.885 60.365 0.085 60.875 0.085 60.875 0.565 61.205 0.565 61.205 0.085 61.795 0.085 61.795 0.565 62.035 0.565 62.035 0.085 66.24 0.085 66.24 -0.085 0 -0.085 0 0.085 4.665 0.085 4.665 0.465 4.995 0.465 4.995 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 8.335 0.085 8.335 0.485 8.665 0.485 8.665 0.085 10.625 0.085 10.625 0.62 11.135 0.62 11.135 0.085 12.395 0.085 12.395 0.565 12.565 0.565 12.565 0.085 13.235 0.085 13.235 0.565 13.405 0.565 13.405 0.085 13.995 0.085 13.995 0.565 14.325 0.565 14.325 0.085 14.835 0.085 14.835 0.565 15.165 0.565 15.165 0.085 15.675 0.085 15.675 0.885 16.005 0.885 16.005 0.085 17.075 0.085 17.075 0.565 17.405 0.565 17.405 0.085 17.915 0.085 17.915 0.565 18.245 0.565 18.245 0.085 18.755 0.085 18.755 0.565 19.085 0.565 19.085 0.085 19.595 0.085 19.595 0.565 19.925 0.565 19.925 0.085 20.435 0.085 20.435 0.565 20.765 0.565 20.765 0.085 21.275 0.085 21.275 0.885 21.605 0.885 21.605 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 23.195 0.085 23.195 0.545 23.465 0.545 23.465 0.085 25.255 0.085 25.255 0.545 25.58 0.545 25.58 0.085 26.735 0.085 26.735 0.565 27.065 0.565 27.065 0.085 27.575 0.085 27.575 0.565 27.905 0.565 27.905 0.085 28.415 0.085 28.415 0.565 28.745 0.565 28.745 0.085 29.255 0.085 29.255 0.565 29.585 0.565 29.585 0.085 30.095 0.085 30.095 0.565 30.425 0.565 30.425 0.085 30.935 0.085 30.935 0.885 31.265 0.885 31.265 0.085 32.255 0.085 32.255 0.565 32.585 0.565 32.585 0.085 33.095 0.085 33.095 0.565 33.425 0.565 33.425 0.085 33.935 0.085 33.935 0.565 34.265 0.565 34.265 0.085 34.775 0.085 34.775 0.565 35.105 0.565 35.105 0.085 35.615 0.085 35.615 0.565 35.945 0.565 35.945 0.085 36.455 0.085 36.455 0.885 36.785 0.885 36.785 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 37.905 0.085 37.905 0.55 38.155 0.55 38.155 0.085 38.745 0.085 38.745 0.545 38.915 0.545 38.915 0.085 39.585 0.085 39.585 0.545 39.755 0.545 39.755 0.085 40.545 0.085 40.545 0.545 40.81 0.545 40.81 0.085 41.455 0.085 41.455 0.565 41.785 0.565 41.785 0.085 42.295 0.085 42.295 0.565 42.625 0.565 42.625 0.085 43.135 0.085 43.135 0.565 43.465 0.565 43.465 0.085 43.975 0.085 43.975 0.565 44.305 0.565 44.305 0.085 44.815 0.085 44.815 0.565 45.145 0.565 45.145 0.085 45.655 0.085 45.655 0.885 45.985 0.885 45.985 0.085 46.975 0.085 46.975 0.565 47.305 0.565 47.305 0.085 47.815 0.085 47.815 0.565 48.145 0.565 48.145 0.085 48.655 0.085 48.655 0.565 48.985 0.565 48.985 0.085 49.495 0.085 49.495 0.565 49.825 0.565 49.825 0.085 50.335 0.085 50.335 0.565 50.665 0.565 50.665 0.085 51.175 0.085 51.175 0.885 51.505 0.885 51.505 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 52.965 0.085 52.965 0.465 53.295 0.465 53.295 0.085 54.335 0.085 54.335 0.565 54.665 0.565 54.665 0.085 55.175 0.085 55.175 0.565 55.505 0.565 55.505 0.085 56.015 0.085 56.015 0.565 56.345 0.565 56.345 0.085 56.855 0.085 56.855 0.565 57.185 0.565 57.185 0.085 57.695 0.085 57.695 0.565 58.025 0.565 58.025 0.085 58.535 0.085 58.535 0.885 58.865 0.885 58.865 0.085 59.425 0.085 59.425 0.81 59.715 0.81 59.715 0.085 60.035 0.085 60.035 0.885 ; RECT 0.17 0.17 66.07 75.99 ; + LAYER mcon ; + RECT 8.18 75.565 8.35 75.735 ; + RECT 4.285 0.5 4.455 0.67 ; + RECT 52.585 0.425 52.755 0.595 ; + RECT 9.865 0.425 10.035 0.595 ; LAYER via ; RECT 55.125 76.085 55.275 76.235 ; RECT 25.685 76.085 25.835 76.235 ; + RECT 38.335 75.575 38.485 75.725 ; + RECT 12.575 75.575 12.725 75.725 ; + RECT 9.355 75.575 9.505 75.725 ; + RECT 60.875 0.435 61.025 0.585 ; + RECT 43.395 0.435 43.545 0.585 ; + RECT 40.635 0.435 40.785 0.585 ; + RECT 39.255 0.435 39.405 0.585 ; + RECT 10.275 0.435 10.425 0.585 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 76.06 55.3 76.26 ; RECT 25.66 76.06 25.86 76.26 ; - RECT 1.05 5 1.25 5.2 ; + RECT 1.05 6.36 1.25 6.56 ; + RECT 14.39 0.24 14.59 0.44 ; + RECT 12.55 0.24 12.75 0.44 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/cby_2__1__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/cby_2__1__icv_in_design.lef index d0d6b9c..a9a0a59 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/cby_2__1__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/cby_2__1__icv_in_design.lef @@ -1326,46 +1326,53 @@ MACRO cby_2__1_ LAYER met2 ; RECT 55.06 75.975 55.34 76.345 ; RECT 25.62 75.975 25.9 76.345 ; + POLYGON 39.86 28.46 39.86 0.24 39.9 0.24 39.9 0.1 39.72 0.1 39.72 28.46 ; + POLYGON 13.64 6.7 13.64 0.1 13 0.1 13 0.24 13.5 0.24 13.5 6.7 ; + RECT 45.64 0.69 45.9 1.01 ; + RECT 47.48 0.35 47.74 0.67 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; POLYGON 65.96 75.88 65.96 0.28 53.94 0.28 53.94 0.765 53.24 0.765 53.24 0.28 53.02 0.28 53.02 0.765 52.32 0.765 52.32 0.28 52.1 0.28 52.1 0.765 51.4 0.765 51.4 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 50.26 0.28 50.26 0.765 49.56 0.765 49.56 0.28 49.34 0.28 49.34 0.765 48.64 0.765 48.64 0.28 48.42 0.28 48.42 0.765 47.72 0.765 47.72 0.28 47.5 0.28 47.5 0.765 46.8 0.765 46.8 0.28 46.58 0.28 46.58 0.765 45.88 0.765 45.88 0.28 45.66 0.28 45.66 0.765 44.96 0.765 44.96 0.28 44.74 0.28 44.74 0.765 44.04 0.765 44.04 0.28 43.82 0.28 43.82 0.765 43.12 0.765 43.12 0.28 42.44 0.28 42.44 0.765 41.74 0.765 41.74 0.28 41.52 0.28 41.52 0.765 40.82 0.765 40.82 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 37.84 0.28 37.84 0.765 37.14 0.765 37.14 0.28 36.92 0.28 36.92 0.765 36.22 0.765 36.22 0.28 36 0.28 36 0.765 35.3 0.765 35.3 0.28 34.62 0.28 34.62 0.765 33.92 0.765 33.92 0.28 33.7 0.28 33.7 0.765 33 0.765 33 0.28 32.78 0.28 32.78 0.765 32.08 0.765 32.08 0.28 31.4 0.28 31.4 0.765 30.7 0.765 30.7 0.28 30.48 0.28 30.48 0.765 29.78 0.765 29.78 0.28 29.56 0.28 29.56 0.765 28.86 0.765 28.86 0.28 28.64 0.28 28.64 0.765 27.94 0.765 27.94 0.28 27.72 0.28 27.72 0.765 27.02 0.765 27.02 0.28 26.8 0.28 26.8 0.765 26.1 0.765 26.1 0.28 25.42 0.28 25.42 0.765 24.72 0.765 24.72 0.28 24.5 0.28 24.5 0.765 23.8 0.765 23.8 0.28 23.12 0.28 23.12 0.765 22.42 0.765 22.42 0.28 22.2 0.28 22.2 0.765 21.5 0.765 21.5 0.28 21.28 0.28 21.28 0.765 20.58 0.765 20.58 0.28 20.36 0.28 20.36 0.765 19.66 0.765 19.66 0.28 19.44 0.28 19.44 0.765 18.74 0.765 18.74 0.28 18.52 0.28 18.52 0.765 17.82 0.765 17.82 0.28 13 0.28 13 0.765 12.3 0.765 12.3 0.28 12.08 0.28 12.08 0.765 11.38 0.765 11.38 0.28 7.94 0.28 7.94 0.765 7.24 0.765 7.24 0.28 7.02 0.28 7.02 0.765 6.32 0.765 6.32 0.28 6.1 0.28 6.1 0.765 5.4 0.765 5.4 0.28 5.18 0.28 5.18 0.765 4.48 0.765 4.48 0.28 0.28 0.28 0.28 75.88 5.4 75.88 5.4 75.395 6.1 75.395 6.1 75.88 6.32 75.88 6.32 75.395 7.02 75.395 7.02 75.88 7.7 75.88 7.7 75.395 8.4 75.395 8.4 75.88 9.08 75.88 9.08 75.395 9.78 75.395 9.78 75.88 12.3 75.88 12.3 75.395 13 75.395 13 75.88 13.22 75.88 13.22 75.395 13.92 75.395 13.92 75.88 21.04 75.88 21.04 75.395 21.74 75.395 21.74 75.88 21.96 75.88 21.96 75.395 22.66 75.395 22.66 75.88 23.34 75.88 23.34 75.395 24.04 75.395 24.04 75.88 24.26 75.88 24.26 75.395 24.96 75.395 24.96 75.88 26.1 75.88 26.1 75.395 26.8 75.395 26.8 75.88 27.02 75.88 27.02 75.395 27.72 75.395 27.72 75.88 28.4 75.88 28.4 75.395 29.1 75.395 29.1 75.88 29.32 75.88 29.32 75.395 30.02 75.395 30.02 75.88 30.24 75.88 30.24 75.395 30.94 75.395 30.94 75.88 31.16 75.88 31.16 75.395 31.86 75.395 31.86 75.88 32.08 75.88 32.08 75.395 32.78 75.395 32.78 75.88 33 75.88 33 75.395 33.7 75.395 33.7 75.88 33.92 75.88 33.92 75.395 34.62 75.395 34.62 75.88 35.3 75.88 35.3 75.395 36 75.395 36 75.88 36.22 75.88 36.22 75.395 36.92 75.395 36.92 75.88 37.6 75.88 37.6 75.395 38.3 75.395 38.3 75.88 38.52 75.88 38.52 75.395 39.22 75.395 39.22 75.88 39.44 75.88 39.44 75.395 40.14 75.395 40.14 75.88 40.36 75.88 40.36 75.395 41.06 75.395 41.06 75.88 41.28 75.88 41.28 75.395 41.98 75.395 41.98 75.88 42.2 75.88 42.2 75.395 42.9 75.395 42.9 75.88 43.12 75.88 43.12 75.395 43.82 75.395 43.82 75.88 44.04 75.88 44.04 75.395 44.74 75.395 44.74 75.88 44.96 75.88 44.96 75.395 45.66 75.395 45.66 75.88 45.88 75.88 45.88 75.395 46.58 75.395 46.58 75.88 46.8 75.88 46.8 75.395 47.5 75.395 47.5 75.88 47.72 75.88 47.72 75.395 48.42 75.395 48.42 75.88 48.64 75.88 48.64 75.395 49.34 75.395 49.34 75.88 49.56 75.88 49.56 75.395 50.26 75.395 50.26 75.88 50.48 75.88 50.48 75.395 51.18 75.395 51.18 75.88 51.4 75.88 51.4 75.395 52.1 75.395 52.1 75.88 52.32 75.88 52.32 75.395 53.02 75.395 53.02 75.88 53.24 75.88 53.24 75.395 53.94 75.395 53.94 75.88 54.16 75.88 54.16 75.395 54.86 75.395 54.86 75.88 55.54 75.88 55.54 75.395 56.24 75.395 56.24 75.88 56.46 75.88 56.46 75.395 57.16 75.395 57.16 75.88 ; LAYER met3 ; POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; - POLYGON 7.74 12.73 7.74 12.43 0.65 12.43 0.65 12.71 1.2 12.71 1.2 12.73 ; + POLYGON 51.915 75.985 51.915 75.98 52.17 75.98 52.17 75.66 51.915 75.66 51.915 75.655 51.585 75.655 51.585 75.66 51.215 75.66 51.215 75.98 51.585 75.98 51.585 75.985 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; POLYGON 65.84 75.76 65.84 11.09 65.04 11.09 65.04 9.99 65.84 9.99 65.84 7.01 65.04 7.01 65.04 5.91 65.84 5.91 65.84 5.65 65.04 5.65 65.04 4.55 65.84 4.55 65.84 0.4 0.4 0.4 0.4 3.19 1.2 3.19 1.2 4.29 0.4 4.29 0.4 4.55 1.2 4.55 1.2 5.65 0.4 5.65 0.4 5.91 1.2 5.91 1.2 7.01 0.4 7.01 0.4 7.27 1.2 7.27 1.2 8.37 0.4 8.37 0.4 8.63 1.2 8.63 1.2 9.73 0.4 9.73 0.4 9.99 1.2 9.99 1.2 11.09 0.4 11.09 0.4 11.35 1.2 11.35 1.2 12.45 0.4 12.45 0.4 12.71 1.2 12.71 1.2 13.81 0.4 13.81 0.4 14.07 1.2 14.07 1.2 15.17 0.4 15.17 0.4 18.83 1.2 18.83 1.2 19.93 0.4 19.93 0.4 20.19 1.2 20.19 1.2 21.29 0.4 21.29 0.4 21.55 1.2 21.55 1.2 22.65 0.4 22.65 0.4 22.91 1.2 22.91 1.2 24.01 0.4 24.01 0.4 24.27 1.2 24.27 1.2 25.37 0.4 25.37 0.4 25.63 1.2 25.63 1.2 26.73 0.4 26.73 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 75.76 ; LAYER met5 ; POLYGON 64.64 74.56 64.64 71.88 61.44 71.88 61.44 65.48 64.64 65.48 64.64 51.48 61.44 51.48 61.44 45.08 64.64 45.08 64.64 31.08 61.44 31.08 61.44 24.68 64.64 24.68 64.64 10.68 61.44 10.68 61.44 4.28 64.64 4.28 64.64 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; LAYER met4 ; + POLYGON 52.145 75.985 52.145 75.655 52.13 75.655 52.13 26.2 51.83 26.2 51.83 75.655 51.815 75.655 51.815 75.985 ; POLYGON 65.84 75.76 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; LAYER met1 ; RECT 45.68 75.92 46.32 76.4 ; + POLYGON 35.81 75.78 35.81 75.72 41.7 75.72 41.7 74.9 41.56 74.9 41.56 75.58 35.81 75.58 35.81 75.52 35.49 75.52 35.49 75.78 ; + POLYGON 47.77 0.64 47.77 0.38 47.45 0.38 47.45 0.44 46.39 0.44 46.39 0.38 46.07 0.38 46.07 0.64 46.39 0.64 46.39 0.58 47.45 0.58 47.45 0.64 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 75.88 46.32 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 45.68 75.64 45.68 75.88 ; LAYER li1 ; - RECT 0 76.075 66.24 76.245 ; - RECT 62.56 73.355 66.24 73.525 ; + POLYGON 66.24 76.245 66.24 76.075 63.005 76.075 63.005 75.275 62.675 75.275 62.675 76.075 62.165 76.075 62.165 75.595 61.835 75.595 61.835 76.075 61.325 76.075 61.325 75.595 60.995 75.595 60.995 76.075 60.485 76.075 60.485 75.595 60.155 75.595 60.155 76.075 59.645 76.075 59.645 75.595 59.315 75.595 59.315 76.075 58.805 76.075 58.805 75.595 58.475 75.595 58.475 76.075 57.485 76.075 57.485 75.275 57.155 75.275 57.155 76.075 56.645 76.075 56.645 75.595 56.315 75.595 56.315 76.075 55.805 76.075 55.805 75.595 55.475 75.595 55.475 76.075 54.965 76.075 54.965 75.595 54.635 75.595 54.635 76.075 54.125 76.075 54.125 75.595 53.795 75.595 53.795 76.075 53.285 76.075 53.285 75.595 52.955 75.595 52.955 76.075 51.965 76.075 51.965 75.275 51.635 75.275 51.635 76.075 51.125 76.075 51.125 75.595 50.795 75.595 50.795 76.075 50.285 76.075 50.285 75.595 49.955 75.595 49.955 76.075 49.445 76.075 49.445 75.595 49.115 75.595 49.115 76.075 48.605 76.075 48.605 75.595 48.275 75.595 48.275 76.075 47.765 76.075 47.765 75.595 47.435 75.595 47.435 76.075 46.445 76.075 46.445 75.275 46.115 75.275 46.115 76.075 45.605 76.075 45.605 75.595 45.275 75.595 45.275 76.075 44.765 76.075 44.765 75.595 44.435 75.595 44.435 76.075 43.925 76.075 43.925 75.595 43.595 75.595 43.595 76.075 43.085 76.075 43.085 75.595 42.755 75.595 42.755 76.075 42.245 76.075 42.245 75.595 41.915 75.595 41.915 76.075 40.885 76.075 40.885 75.595 40.555 75.595 40.555 76.075 40.045 76.075 40.045 75.595 39.715 75.595 39.715 76.075 39.205 76.075 39.205 75.595 38.875 75.595 38.875 76.075 38.365 76.075 38.365 75.595 38.035 75.595 38.035 76.075 37.525 76.075 37.525 75.595 37.195 75.595 37.195 76.075 36.685 76.075 36.685 75.275 36.355 75.275 36.355 76.075 35.405 76.075 35.405 75.275 35.075 75.275 35.075 76.075 34.565 76.075 34.565 75.595 34.235 75.595 34.235 76.075 33.725 76.075 33.725 75.595 33.395 75.595 33.395 76.075 32.885 76.075 32.885 75.595 32.555 75.595 32.555 76.075 32.045 76.075 32.045 75.595 31.715 75.595 31.715 76.075 31.205 76.075 31.205 75.595 30.875 75.595 30.875 76.075 29.885 76.075 29.885 75.275 29.555 75.275 29.555 76.075 29.045 76.075 29.045 75.595 28.715 75.595 28.715 76.075 28.205 76.075 28.205 75.595 27.875 75.595 27.875 76.075 27.365 76.075 27.365 75.595 27.035 75.595 27.035 76.075 26.525 76.075 26.525 75.595 26.195 75.595 26.195 76.075 25.685 76.075 25.685 75.595 25.355 75.595 25.355 76.075 24.325 76.075 24.325 75.595 23.995 75.595 23.995 76.075 23.485 76.075 23.485 75.595 23.155 75.595 23.155 76.075 22.645 76.075 22.645 75.595 22.315 75.595 22.315 76.075 21.805 76.075 21.805 75.595 21.475 75.595 21.475 76.075 20.965 76.075 20.965 75.595 20.635 75.595 20.635 76.075 20.125 76.075 20.125 75.275 19.795 75.275 19.795 76.075 18.845 76.075 18.845 75.275 18.515 75.275 18.515 76.075 18.005 76.075 18.005 75.595 17.675 75.595 17.675 76.075 17.165 76.075 17.165 75.595 16.835 75.595 16.835 76.075 16.325 76.075 16.325 75.595 15.995 75.595 15.995 76.075 15.485 76.075 15.485 75.595 15.155 75.595 15.155 76.075 14.645 76.075 14.645 75.595 14.315 75.595 14.315 76.075 13.325 76.075 13.325 75.275 12.995 75.275 12.995 76.075 12.485 76.075 12.485 75.595 12.155 75.595 12.155 76.075 11.645 76.075 11.645 75.595 11.315 75.595 11.315 76.075 10.805 76.075 10.805 75.595 10.475 75.595 10.475 76.075 9.965 76.075 9.965 75.595 9.635 75.595 9.635 76.075 9.125 76.075 9.125 75.595 8.795 75.595 8.795 76.075 7.805 76.075 7.805 75.275 7.475 75.275 7.475 76.075 6.965 76.075 6.965 75.595 6.635 75.595 6.635 76.075 6.125 76.075 6.125 75.595 5.795 75.595 5.795 76.075 5.285 76.075 5.285 75.595 4.955 75.595 4.955 76.075 4.445 76.075 4.445 75.595 4.115 75.595 4.115 76.075 3.605 76.075 3.605 75.595 3.275 75.595 3.275 76.075 0 76.075 0 76.245 ; + RECT 64.4 73.355 66.24 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 65.32 70.635 66.24 70.805 ; - RECT 0 70.635 1.84 70.805 ; + RECT 64.4 70.635 66.24 70.805 ; + RECT 0 70.635 3.68 70.805 ; RECT 65.32 67.915 66.24 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 65.32 65.195 66.24 65.365 ; + RECT 0 67.915 3.68 68.085 ; + RECT 62.56 65.195 66.24 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 65.32 62.475 66.24 62.645 ; + RECT 62.56 62.475 66.24 62.645 ; RECT 0 62.475 1.84 62.645 ; RECT 65.32 59.755 66.24 59.925 ; - RECT 0 59.755 1.84 59.925 ; + RECT 0 59.755 3.68 59.925 ; RECT 65.32 57.035 66.24 57.205 ; - RECT 0 57.035 1.84 57.205 ; + RECT 0 57.035 3.68 57.205 ; RECT 65.32 54.315 66.24 54.485 ; RECT 0 54.315 1.84 54.485 ; RECT 65.32 51.595 66.24 51.765 ; - RECT 0 51.595 1.84 51.765 ; + RECT 0 51.595 3.68 51.765 ; RECT 65.32 48.875 66.24 49.045 ; - RECT 0 48.875 1.84 49.045 ; + RECT 0 48.875 3.68 49.045 ; RECT 65.32 46.155 66.24 46.325 ; RECT 0 46.155 1.84 46.325 ; RECT 65.32 43.435 66.24 43.605 ; @@ -1373,19 +1380,19 @@ MACRO cby_2__1_ RECT 65.32 40.715 66.24 40.885 ; RECT 0 40.715 1.84 40.885 ; RECT 65.32 37.995 66.24 38.165 ; - RECT 0 37.995 3.68 38.165 ; + RECT 0 37.995 1.84 38.165 ; RECT 65.32 35.275 66.24 35.445 ; - RECT 0 35.275 3.68 35.445 ; + RECT 0 35.275 1.84 35.445 ; RECT 65.32 32.555 66.24 32.725 ; - RECT 0 32.555 1.84 32.725 ; + RECT 0 32.555 3.68 32.725 ; RECT 65.32 29.835 66.24 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 65.32 27.115 66.24 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 65.32 24.395 66.24 24.565 ; + RECT 0 29.835 3.68 30.005 ; + RECT 62.56 27.115 66.24 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 62.56 24.395 66.24 24.565 ; RECT 0 24.395 3.68 24.565 ; RECT 65.32 21.675 66.24 21.845 ; - RECT 0 21.675 3.68 21.845 ; + RECT 0 21.675 1.84 21.845 ; RECT 65.32 18.955 66.24 19.125 ; RECT 0 18.955 1.84 19.125 ; RECT 65.32 16.235 66.24 16.405 ; @@ -1395,28 +1402,31 @@ MACRO cby_2__1_ RECT 65.32 10.795 66.24 10.965 ; RECT 0 10.795 1.84 10.965 ; RECT 65.32 8.075 66.24 8.245 ; - RECT 0 8.075 1.84 8.245 ; + RECT 0 8.075 3.68 8.245 ; RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 62.56 2.635 66.24 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; + RECT 64.4 2.635 66.24 2.805 ; + RECT 0 2.635 1.84 2.805 ; + POLYGON 60.245 0.885 60.245 0.085 66.24 0.085 66.24 -0.085 0 -0.085 0 0.085 3.235 0.085 3.235 0.885 3.565 0.885 3.565 0.085 4.075 0.085 4.075 0.565 4.405 0.565 4.405 0.085 4.915 0.085 4.915 0.565 5.245 0.565 5.245 0.085 5.755 0.085 5.755 0.565 6.085 0.565 6.085 0.085 6.595 0.085 6.595 0.565 6.925 0.565 6.925 0.085 7.435 0.085 7.435 0.565 7.765 0.565 7.765 0.085 8.935 0.085 8.935 0.545 9.205 0.545 9.205 0.085 10.995 0.085 10.995 0.545 11.32 0.545 11.32 0.085 12.395 0.085 12.395 0.565 12.565 0.565 12.565 0.085 13.235 0.085 13.235 0.565 13.405 0.565 13.405 0.085 13.995 0.085 13.995 0.565 14.325 0.565 14.325 0.085 14.835 0.085 14.835 0.565 15.165 0.565 15.165 0.085 15.675 0.085 15.675 0.885 16.005 0.885 16.005 0.085 16.615 0.085 16.615 0.565 16.945 0.565 16.945 0.085 17.455 0.085 17.455 0.565 17.785 0.565 17.785 0.085 18.295 0.085 18.295 0.565 18.625 0.565 18.625 0.085 19.135 0.085 19.135 0.565 19.465 0.565 19.465 0.085 19.975 0.085 19.975 0.565 20.305 0.565 20.305 0.085 20.815 0.085 20.815 0.885 21.145 0.885 21.145 0.085 22.135 0.085 22.135 0.565 22.465 0.565 22.465 0.085 22.975 0.085 22.975 0.565 23.305 0.565 23.305 0.085 23.815 0.085 23.815 0.565 24.145 0.565 24.145 0.085 24.655 0.085 24.655 0.565 24.985 0.565 24.985 0.085 25.495 0.085 25.495 0.565 25.825 0.565 25.825 0.085 26.335 0.085 26.335 0.885 26.665 0.885 26.665 0.085 28.115 0.085 28.115 0.565 28.445 0.565 28.445 0.085 28.955 0.085 28.955 0.565 29.285 0.565 29.285 0.085 29.795 0.085 29.795 0.565 30.125 0.565 30.125 0.085 30.635 0.085 30.635 0.565 30.965 0.565 30.965 0.085 31.475 0.085 31.475 0.565 31.805 0.565 31.805 0.085 32.315 0.085 32.315 0.885 32.645 0.885 32.645 0.085 33.635 0.085 33.635 0.565 33.965 0.565 33.965 0.085 34.475 0.085 34.475 0.565 34.805 0.565 34.805 0.085 35.315 0.085 35.315 0.565 35.645 0.565 35.645 0.085 36.155 0.085 36.155 0.565 36.485 0.565 36.485 0.085 36.995 0.085 36.995 0.565 37.325 0.565 37.325 0.085 37.835 0.085 37.835 0.885 38.165 0.885 38.165 0.085 39.155 0.085 39.155 0.565 39.485 0.565 39.485 0.085 39.995 0.085 39.995 0.565 40.325 0.565 40.325 0.085 40.835 0.085 40.835 0.565 41.165 0.565 41.165 0.085 41.675 0.085 41.675 0.565 42.005 0.565 42.005 0.085 42.515 0.085 42.515 0.565 42.845 0.565 42.845 0.085 43.355 0.085 43.355 0.885 43.685 0.885 43.685 0.085 44.675 0.085 44.675 0.565 45.005 0.565 45.005 0.085 45.515 0.085 45.515 0.565 45.845 0.565 45.845 0.085 46.355 0.085 46.355 0.565 46.685 0.565 46.685 0.085 47.195 0.085 47.195 0.565 47.525 0.565 47.525 0.085 48.035 0.085 48.035 0.565 48.365 0.565 48.365 0.085 48.875 0.085 48.875 0.885 49.205 0.885 49.205 0.085 50.195 0.085 50.195 0.565 50.525 0.565 50.525 0.085 51.035 0.085 51.035 0.565 51.365 0.565 51.365 0.085 51.875 0.085 51.875 0.565 52.205 0.565 52.205 0.085 52.715 0.085 52.715 0.565 53.045 0.565 53.045 0.085 53.555 0.085 53.555 0.565 53.885 0.565 53.885 0.085 54.395 0.085 54.395 0.885 54.725 0.885 54.725 0.085 55.715 0.085 55.715 0.565 56.045 0.565 56.045 0.085 56.555 0.085 56.555 0.565 56.885 0.565 56.885 0.085 57.395 0.085 57.395 0.565 57.725 0.565 57.725 0.085 58.235 0.085 58.235 0.565 58.565 0.565 58.565 0.085 59.075 0.085 59.075 0.565 59.405 0.565 59.405 0.085 59.915 0.085 59.915 0.885 ; RECT 0.17 0.17 66.07 75.99 ; LAYER via ; RECT 55.125 76.085 55.275 76.235 ; RECT 25.685 76.085 25.835 76.235 ; + RECT 35.575 75.575 35.725 75.725 ; + RECT 47.535 0.435 47.685 0.585 ; + RECT 46.155 0.435 46.305 0.585 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 76.06 55.3 76.26 ; RECT 25.66 76.06 25.86 76.26 ; - RECT 1.05 45.8 1.25 46 ; - RECT 64.99 6.36 65.19 6.56 ; + RECT 51.65 75.72 51.85 75.92 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; RECT 55.1 76.06 55.3 76.26 ; RECT 25.66 76.06 25.86 76.26 ; + RECT 51.88 75.72 52.08 75.92 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER OVERLAP ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__0__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__0__icv_in_design.lef index cc01410..d3a6b95 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__0__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__0__icv_in_design.lef @@ -1216,44 +1216,48 @@ MACRO sb_0__0_ LAYER met2 ; RECT 55.06 97.735 55.34 98.105 ; RECT 25.62 97.735 25.9 98.105 ; - POLYGON 66.08 92.04 66.08 81.02 65.94 81.02 65.94 91.9 65.02 91.9 65.02 92.04 ; + POLYGON 39.9 97.82 39.9 97.68 39.86 97.68 39.86 92.07 39.72 92.07 39.72 97.82 ; + POLYGON 65.16 19.62 65.16 0.24 65.66 0.24 65.66 0.1 65.02 0.1 65.02 19.62 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; POLYGON 65.96 97.64 65.96 86.76 82.22 86.76 82.22 86.275 82.92 86.275 82.92 86.76 91.72 86.76 91.72 0.28 66.36 0.28 66.36 0.765 65.66 0.765 65.66 0.28 0.28 0.28 0.28 97.64 12.76 97.64 12.76 97.155 13.46 97.155 13.46 97.64 13.68 97.64 13.68 97.155 14.38 97.155 14.38 97.64 14.6 97.64 14.6 97.155 15.3 97.155 15.3 97.64 15.52 97.64 15.52 97.155 16.22 97.155 16.22 97.64 16.44 97.64 16.44 97.155 17.14 97.155 17.14 97.64 17.36 97.64 17.36 97.155 18.06 97.155 18.06 97.64 18.28 97.64 18.28 97.155 18.98 97.155 18.98 97.64 24.72 97.64 24.72 97.155 25.42 97.155 25.42 97.64 26.1 97.64 26.1 97.155 26.8 97.155 26.8 97.64 30.7 97.64 30.7 97.155 31.4 97.155 31.4 97.64 31.62 97.64 31.62 97.155 32.32 97.155 32.32 97.64 32.54 97.64 32.54 97.155 33.24 97.155 33.24 97.64 33.46 97.64 33.46 97.155 34.16 97.155 34.16 97.64 34.38 97.64 34.38 97.155 35.08 97.155 35.08 97.64 35.3 97.64 35.3 97.155 36 97.155 36 97.64 36.22 97.64 36.22 97.155 36.92 97.155 36.92 97.64 37.14 97.64 37.14 97.155 37.84 97.155 37.84 97.64 38.06 97.64 38.06 97.155 38.76 97.155 38.76 97.64 38.98 97.64 38.98 97.155 39.68 97.155 39.68 97.64 39.9 97.64 39.9 97.155 40.6 97.155 40.6 97.64 40.82 97.64 40.82 97.155 41.52 97.155 41.52 97.64 41.74 97.64 41.74 97.155 42.44 97.155 42.44 97.64 42.66 97.64 42.66 97.155 43.36 97.155 43.36 97.64 46.8 97.64 46.8 97.155 47.5 97.155 47.5 97.64 47.72 97.64 47.72 97.155 48.42 97.155 48.42 97.64 48.64 97.64 48.64 97.155 49.34 97.155 49.34 97.64 49.56 97.64 49.56 97.155 50.26 97.155 50.26 97.64 50.48 97.64 50.48 97.155 51.18 97.155 51.18 97.64 51.4 97.64 51.4 97.155 52.1 97.155 52.1 97.64 52.32 97.64 52.32 97.155 53.02 97.155 53.02 97.64 53.24 97.64 53.24 97.155 53.94 97.155 53.94 97.64 54.16 97.64 54.16 97.155 54.86 97.155 54.86 97.64 56 97.64 56 97.155 56.7 97.155 56.7 97.64 56.92 97.64 56.92 97.155 57.62 97.155 57.62 97.64 57.84 97.64 57.84 97.155 58.54 97.155 58.54 97.64 58.76 97.64 58.76 97.155 59.46 97.155 59.46 97.64 59.68 97.64 59.68 97.155 60.38 97.155 60.38 97.64 60.6 97.64 60.6 97.155 61.3 97.155 61.3 97.64 61.52 97.64 61.52 97.155 62.22 97.155 62.22 97.64 62.44 97.64 62.44 97.155 63.14 97.155 63.14 97.64 63.36 97.64 63.36 97.155 64.06 97.155 64.06 97.64 ; LAYER met3 ; POLYGON 55.365 98.085 55.365 98.08 55.58 98.08 55.58 97.76 55.365 97.76 55.365 97.755 55.035 97.755 55.035 97.76 54.82 97.76 54.82 98.08 55.035 98.08 55.035 98.085 ; POLYGON 25.925 98.085 25.925 98.08 26.14 98.08 26.14 97.76 25.925 97.76 25.925 97.755 25.595 97.755 25.595 97.76 25.38 97.76 25.38 98.08 25.595 98.08 25.595 98.085 ; + POLYGON 38.575 97.745 38.575 97.73 51.79 97.73 51.79 97.74 52.17 97.74 52.17 97.42 51.79 97.42 51.79 97.43 38.575 97.43 38.575 97.415 38.245 97.415 38.245 97.745 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; POLYGON 65.84 97.52 65.84 86.64 91.6 86.64 91.6 83.85 90.8 83.85 90.8 82.75 91.6 82.75 91.6 82.49 90.8 82.49 90.8 81.39 91.6 81.39 91.6 81.13 90.8 81.13 90.8 80.03 91.6 80.03 91.6 79.77 90.8 79.77 90.8 78.67 91.6 78.67 91.6 78.41 90.8 78.41 90.8 77.31 91.6 77.31 91.6 76.37 90.8 76.37 90.8 75.27 91.6 75.27 91.6 75.01 90.8 75.01 90.8 73.91 91.6 73.91 91.6 73.65 90.8 73.65 90.8 72.55 91.6 72.55 91.6 71.61 90.8 71.61 90.8 70.51 91.6 70.51 91.6 70.25 90.8 70.25 90.8 69.15 91.6 69.15 91.6 68.89 90.8 68.89 90.8 67.79 91.6 67.79 91.6 67.53 90.8 67.53 90.8 66.43 91.6 66.43 91.6 66.17 90.8 66.17 90.8 65.07 91.6 65.07 91.6 64.81 90.8 64.81 90.8 63.71 91.6 63.71 91.6 62.77 90.8 62.77 90.8 61.67 91.6 61.67 91.6 61.41 90.8 61.41 90.8 60.31 91.6 60.31 91.6 60.05 90.8 60.05 90.8 58.95 91.6 58.95 91.6 58.69 90.8 58.69 90.8 57.59 91.6 57.59 91.6 57.33 90.8 57.33 90.8 56.23 91.6 56.23 91.6 55.97 90.8 55.97 90.8 54.87 91.6 54.87 91.6 54.61 90.8 54.61 90.8 53.51 91.6 53.51 91.6 53.25 90.8 53.25 90.8 52.15 91.6 52.15 91.6 51.89 90.8 51.89 90.8 50.79 91.6 50.79 91.6 50.53 90.8 50.53 90.8 49.43 91.6 49.43 91.6 49.17 90.8 49.17 90.8 48.07 91.6 48.07 91.6 47.81 90.8 47.81 90.8 46.71 91.6 46.71 91.6 46.45 90.8 46.45 90.8 45.35 91.6 45.35 91.6 45.09 90.8 45.09 90.8 43.99 91.6 43.99 91.6 43.73 90.8 43.73 90.8 42.63 91.6 42.63 91.6 42.37 90.8 42.37 90.8 41.27 91.6 41.27 91.6 40.33 90.8 40.33 90.8 39.23 91.6 39.23 91.6 38.97 90.8 38.97 90.8 37.87 91.6 37.87 91.6 37.61 90.8 37.61 90.8 36.51 91.6 36.51 91.6 36.25 90.8 36.25 90.8 35.15 91.6 35.15 91.6 34.89 90.8 34.89 90.8 33.79 91.6 33.79 91.6 33.53 90.8 33.53 90.8 32.43 91.6 32.43 91.6 32.17 90.8 32.17 90.8 31.07 91.6 31.07 91.6 30.13 90.8 30.13 90.8 29.03 91.6 29.03 91.6 28.77 90.8 28.77 90.8 27.67 91.6 27.67 91.6 27.41 90.8 27.41 90.8 26.31 91.6 26.31 91.6 26.05 90.8 26.05 90.8 24.95 91.6 24.95 91.6 24.69 90.8 24.69 90.8 23.59 91.6 23.59 91.6 23.33 90.8 23.33 90.8 22.23 91.6 22.23 91.6 21.97 90.8 21.97 90.8 20.87 91.6 20.87 91.6 20.61 90.8 20.61 90.8 19.51 91.6 19.51 91.6 19.25 90.8 19.25 90.8 18.15 91.6 18.15 91.6 17.89 90.8 17.89 90.8 16.79 91.6 16.79 91.6 16.53 90.8 16.53 90.8 15.43 91.6 15.43 91.6 13.81 90.8 13.81 90.8 12.71 91.6 12.71 91.6 8.37 90.8 8.37 90.8 7.27 91.6 7.27 91.6 0.4 0.4 0.4 0.4 97.52 ; LAYER met1 ; RECT 45.68 97.68 46.32 98.16 ; - RECT 46.53 87.42 46.85 87.68 ; - POLYGON 62.49 86.66 62.49 86.4 62.17 86.4 62.17 86.46 57.065 86.46 57.065 86.415 56.775 86.415 56.775 86.645 57.065 86.645 57.065 86.6 62.17 86.6 62.17 86.66 ; - POLYGON 52.37 86.66 52.37 86.6 53.445 86.6 53.445 86.645 53.735 86.645 53.735 86.415 53.445 86.415 53.445 86.46 52.37 86.46 52.37 86.4 52.05 86.4 52.05 86.66 ; - POLYGON 50.53 86.66 50.53 86.645 50.575 86.645 50.575 86.415 50.53 86.415 50.53 86.4 50.21 86.4 50.21 86.66 ; - POLYGON 48.675 86.645 48.675 86.415 48.6 86.415 48.6 86.12 48.46 86.12 48.46 86.415 48.385 86.415 48.385 86.645 ; + POLYGON 90.09 86.66 90.09 86.4 89.77 86.4 89.77 86.46 65.295 86.46 65.295 86.415 65.005 86.415 65.005 86.645 65.295 86.645 65.295 86.6 89.77 86.6 89.77 86.66 ; + POLYGON 57.89 86.66 57.89 86.6 58.505 86.6 58.505 86.645 58.795 86.645 58.795 86.415 58.505 86.415 58.505 86.46 57.89 86.46 57.89 86.4 57.57 86.4 57.57 86.66 ; + POLYGON 51.45 86.66 51.45 86.6 55.745 86.6 55.745 86.645 56.035 86.645 56.035 86.415 55.745 86.415 55.745 86.46 51.45 86.46 51.45 86.4 51.13 86.4 51.13 86.66 ; + RECT 46.07 86.4 46.39 86.66 ; + POLYGON 61.095 86.645 61.095 86.6 61.94 86.6 61.94 85.1 61.8 85.1 61.8 86.46 61.095 86.46 61.095 86.415 60.805 86.415 60.805 86.645 ; + POLYGON 46.835 86.645 46.835 86.415 46.76 86.415 46.76 86.12 46.62 86.12 46.62 86.415 46.545 86.415 46.545 86.645 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 97.64 46.32 97.4 65.96 97.4 65.96 95.72 65.48 95.72 65.48 94.68 65.96 94.68 65.96 93 65.48 93 65.48 91.96 65.96 91.96 65.96 90.28 65.48 90.28 65.48 89.24 65.96 89.24 65.96 87.56 46.32 87.56 46.32 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 91.24 11.4 91.24 10.36 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 45.68 97.4 45.68 97.64 ; LAYER met4 ; + POLYGON 52.145 97.745 52.145 97.415 52.13 97.415 52.13 36.23 51.83 36.23 51.83 97.415 51.815 97.415 51.815 97.745 ; POLYGON 65.84 97.52 65.84 86.64 80.26 86.64 80.26 86.04 81.66 86.04 81.66 86.64 91.6 86.64 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 25.06 97.52 25.06 96.92 26.46 96.92 26.46 97.52 39.78 97.52 39.78 96.92 41.18 96.92 41.18 97.52 54.5 97.52 54.5 96.92 55.9 96.92 55.9 97.52 ; LAYER met5 ; POLYGON 64.64 96.32 64.64 85.44 90.4 85.44 90.4 77.32 87.2 77.32 87.2 70.92 90.4 70.92 90.4 56.92 87.2 56.92 87.2 50.52 90.4 50.52 90.4 36.52 87.2 36.52 87.2 30.12 90.4 30.12 90.4 16.12 87.2 16.12 87.2 9.72 90.4 9.72 90.4 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 96.32 ; LAYER li1 ; - RECT 0 97.835 66.24 98.005 ; - RECT 62.56 95.115 66.24 95.285 ; + POLYGON 66.24 98.005 66.24 97.835 59.715 97.835 59.715 97.11 59.425 97.11 59.425 97.835 59.245 97.835 59.245 97.035 58.915 97.035 58.915 97.835 58.405 97.835 58.405 97.355 58.075 97.355 58.075 97.835 57.565 97.835 57.565 97.355 57.235 97.355 57.235 97.835 56.645 97.835 56.645 97.355 56.475 97.355 56.475 97.835 55.805 97.835 55.805 97.355 55.635 97.355 55.635 97.835 52.355 97.835 52.355 97.11 52.065 97.11 52.065 97.835 51.755 97.835 51.755 97.36 51.585 97.36 51.585 97.835 50.905 97.835 50.905 97.36 50.735 97.36 50.735 97.835 50.035 97.835 50.035 97.355 49.865 97.355 49.865 97.835 49.035 97.835 49.035 97.305 48.865 97.305 48.865 97.835 47.01 97.835 47.01 97.335 46.64 97.335 46.64 97.835 44.945 97.835 44.945 97.375 44.695 97.375 44.695 97.835 44.085 97.835 44.085 97.455 43.755 97.455 43.755 97.835 37.635 97.835 37.635 97.11 37.345 97.11 37.345 97.835 29.005 97.835 29.005 97.355 28.835 97.355 28.835 97.835 28.165 97.835 28.165 97.355 27.995 97.355 27.995 97.835 27.405 97.835 27.405 97.355 27.075 97.355 27.075 97.835 26.565 97.835 26.565 97.355 26.235 97.355 26.235 97.835 25.725 97.835 25.725 97.035 25.395 97.035 25.395 97.835 22.455 97.835 22.455 97.11 22.165 97.11 22.165 97.835 7.735 97.835 7.735 97.11 7.445 97.11 7.445 97.835 0 97.835 0 98.005 ; + RECT 65.32 95.115 66.24 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 65.32 92.395 66.24 92.565 ; + RECT 62.56 92.395 66.24 92.565 ; RECT 0 92.395 3.68 92.565 ; - RECT 65.32 89.675 66.24 89.845 ; + RECT 62.56 89.675 66.24 89.845 ; RECT 0 89.675 3.68 89.845 ; - RECT 62.56 86.955 92 87.125 ; + POLYGON 92 87.125 92 86.955 89.615 86.955 89.615 86.23 89.325 86.23 89.325 86.955 88.345 86.955 88.345 86.475 88.175 86.475 88.175 86.955 87.505 86.955 87.505 86.475 87.335 86.475 87.335 86.955 86.745 86.955 86.745 86.475 86.415 86.475 86.415 86.955 85.905 86.955 85.905 86.475 85.575 86.475 85.575 86.955 85.065 86.955 85.065 86.155 84.735 86.155 84.735 86.955 82.255 86.955 82.255 86.23 81.965 86.23 81.965 86.955 80.275 86.955 80.275 86.48 80.105 86.48 80.105 86.955 79.425 86.955 79.425 86.48 79.255 86.48 79.255 86.955 78.555 86.955 78.555 86.475 78.385 86.475 78.385 86.955 77.555 86.955 77.555 86.425 77.385 86.425 77.385 86.955 75.53 86.955 75.53 86.455 75.16 86.455 75.16 86.955 73.465 86.955 73.465 86.495 73.215 86.495 73.215 86.955 72.605 86.955 72.605 86.575 72.275 86.575 72.275 86.955 67.535 86.955 67.535 86.23 67.245 86.23 67.245 86.955 66.335 86.955 66.335 86.42 65.825 86.42 65.825 86.955 63.865 86.955 63.865 86.555 63.535 86.555 63.535 86.955 63.02 86.955 63.02 87.125 ; RECT 0 86.955 3.68 87.125 ; - RECT 88.32 84.235 92 84.405 ; + RECT 91.54 84.235 92 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 88.32 81.515 92 81.685 ; + RECT 91.54 81.515 92 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 88.32 78.795 92 78.965 ; + RECT 91.54 78.795 92 78.965 ; RECT 0 78.795 3.68 78.965 ; RECT 91.08 76.075 92 76.245 ; RECT 0 76.075 3.68 76.245 ; @@ -1263,80 +1267,81 @@ MACRO sb_0__0_ RECT 0 70.635 3.68 70.805 ; RECT 91.08 67.915 92 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 91.08 65.195 92 65.365 ; + RECT 91.54 65.195 92 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 91.08 62.475 92 62.645 ; + RECT 91.54 62.475 92 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 88.32 59.755 92 59.925 ; + RECT 91.54 59.755 92 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 88.32 57.035 92 57.205 ; + RECT 91.54 57.035 92 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 91.08 54.315 92 54.485 ; + RECT 91.54 54.315 92 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 91.08 51.595 92 51.765 ; + RECT 91.54 51.595 92 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 90.16 48.875 92 49.045 ; + RECT 91.08 48.875 92 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 90.16 46.155 92 46.325 ; + RECT 91.08 46.155 92 46.325 ; RECT 0 46.155 3.68 46.325 ; RECT 91.08 43.435 92 43.605 ; RECT 0 43.435 3.68 43.605 ; RECT 91.08 40.715 92 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 91.08 37.995 92 38.165 ; + RECT 91.54 37.995 92 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 91.08 35.275 92 35.445 ; + RECT 91.54 35.275 92 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 91.08 32.555 92 32.725 ; + RECT 91.54 32.555 92 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 91.08 29.835 92 30.005 ; + RECT 91.54 29.835 92 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 91.08 27.115 92 27.285 ; + RECT 91.54 27.115 92 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 91.08 24.395 92 24.565 ; + RECT 91.54 24.395 92 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 88.32 21.675 92 21.845 ; + RECT 91.54 21.675 92 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 88.32 18.955 92 19.125 ; + RECT 91.54 18.955 92 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 90.16 16.235 92 16.405 ; + RECT 91.54 16.235 92 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 88.32 13.515 92 13.685 ; + RECT 91.54 13.515 92 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 88.32 10.795 92 10.965 ; + RECT 91.54 10.795 92 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 88.32 8.075 92 8.245 ; + RECT 91.54 8.075 92 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 88.32 5.355 92 5.525 ; + RECT 91.54 5.355 92 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 88.32 2.635 92 2.805 ; + RECT 91.54 2.635 92 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 92 0.085 ; + POLYGON 89.615 0.81 89.615 0.085 92 0.085 92 -0.085 0 -0.085 0 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 89.325 0.085 89.325 0.81 ; POLYGON 66.07 97.75 66.07 86.87 91.83 86.87 91.83 0.17 0.17 0.17 0.17 97.75 ; LAYER mcon ; - RECT 46.605 87.465 46.775 87.635 ; - RECT 56.835 86.445 57.005 86.615 ; - RECT 53.505 86.445 53.675 86.615 ; - RECT 50.345 86.445 50.515 86.615 ; - RECT 48.445 86.445 48.615 86.615 ; + RECT 65.065 86.445 65.235 86.615 ; + RECT 60.865 86.445 61.035 86.615 ; + RECT 58.565 86.445 58.735 86.615 ; + RECT 55.805 86.445 55.975 86.615 ; + RECT 46.605 86.445 46.775 86.615 ; LAYER via ; RECT 55.125 97.845 55.275 97.995 ; RECT 25.685 97.845 25.835 97.995 ; - RECT 46.615 87.475 46.765 87.625 ; RECT 55.125 86.965 55.275 87.115 ; - RECT 62.255 86.455 62.405 86.605 ; - RECT 52.135 86.455 52.285 86.605 ; - RECT 50.295 86.455 50.445 86.605 ; + RECT 89.855 86.455 90.005 86.605 ; + RECT 57.655 86.455 57.805 86.605 ; + RECT 51.215 86.455 51.365 86.605 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 97.82 55.3 98.02 ; RECT 25.66 97.82 25.86 98.02 ; + RECT 38.31 97.48 38.51 97.68 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; RECT 55.1 97.82 55.3 98.02 ; RECT 25.66 97.82 25.86 98.02 ; + RECT 51.88 97.48 52.08 97.68 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER OVERLAP ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__1__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__1__icv_in_design.lef index 9474689..c9b3dee 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__1__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__1__icv_in_design.lef @@ -1544,12 +1544,18 @@ MACRO sb_0__1_ LAYER met2 ; RECT 55.06 108.615 55.34 108.985 ; RECT 25.62 108.615 25.9 108.985 ; + POLYGON 39.9 108.7 39.9 108.56 39.86 108.56 39.86 105.16 39.72 105.16 39.72 108.7 ; + RECT 74.61 97.395 74.89 97.765 ; + POLYGON 60.56 22.68 60.56 0.1 60.38 0.1 60.38 0.24 60.42 0.24 60.42 22.68 ; + POLYGON 11.8 6.36 11.8 0.1 11.62 0.1 11.62 0.24 11.66 0.24 11.66 6.36 ; + POLYGON 39.86 5 39.86 0.24 39.9 0.24 39.9 0.1 39.72 0.1 39.72 5 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; POLYGON 65.96 108.52 65.96 97.64 91.72 97.64 91.72 11.16 87.52 11.16 87.52 11.645 86.82 11.645 86.82 11.16 86.14 11.16 86.14 11.645 85.44 11.645 85.44 11.16 83.38 11.16 83.38 11.645 82.68 11.645 82.68 11.16 82.46 11.16 82.46 11.645 81.76 11.645 81.76 11.16 81.54 11.16 81.54 11.645 80.84 11.645 80.84 11.16 80.62 11.16 80.62 11.645 79.92 11.645 79.92 11.16 79.7 11.16 79.7 11.645 79 11.645 79 11.16 78.78 11.16 78.78 11.645 78.08 11.645 78.08 11.16 65.96 11.16 65.96 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 61.3 0.28 61.3 0.765 60.6 0.765 60.6 0.28 60.38 0.28 60.38 0.765 59.68 0.765 59.68 0.28 59.46 0.28 59.46 0.765 58.76 0.765 58.76 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 53.94 0.28 53.94 0.765 53.24 0.765 53.24 0.28 53.02 0.28 53.02 0.765 52.32 0.765 52.32 0.28 52.1 0.28 52.1 0.765 51.4 0.765 51.4 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 50.26 0.28 50.26 0.765 49.56 0.765 49.56 0.28 41.52 0.28 41.52 0.765 40.82 0.765 40.82 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 37.84 0.28 37.84 0.765 37.14 0.765 37.14 0.28 36.92 0.28 36.92 0.765 36.22 0.765 36.22 0.28 36 0.28 36 0.765 35.3 0.765 35.3 0.28 35.08 0.28 35.08 0.765 34.38 0.765 34.38 0.28 34.16 0.28 34.16 0.765 33.46 0.765 33.46 0.28 33.24 0.28 33.24 0.765 32.54 0.765 32.54 0.28 26.8 0.28 26.8 0.765 26.1 0.765 26.1 0.28 21.74 0.28 21.74 0.765 21.04 0.765 21.04 0.28 20.82 0.28 20.82 0.765 20.12 0.765 20.12 0.28 19.9 0.28 19.9 0.765 19.2 0.765 19.2 0.28 18.98 0.28 18.98 0.765 18.28 0.765 18.28 0.28 18.06 0.28 18.06 0.765 17.36 0.765 17.36 0.28 17.14 0.28 17.14 0.765 16.44 0.765 16.44 0.28 16.22 0.28 16.22 0.765 15.52 0.765 15.52 0.28 15.3 0.28 15.3 0.765 14.6 0.765 14.6 0.28 14.38 0.28 14.38 0.765 13.68 0.765 13.68 0.28 13.46 0.28 13.46 0.765 12.76 0.765 12.76 0.28 12.54 0.28 12.54 0.765 11.84 0.765 11.84 0.28 11.62 0.28 11.62 0.765 10.92 0.765 10.92 0.28 10.7 0.28 10.7 0.765 10 0.765 10 0.28 9.78 0.28 9.78 0.765 9.08 0.765 9.08 0.28 8.86 0.28 8.86 0.765 8.16 0.765 8.16 0.28 2.88 0.28 2.88 0.765 2.18 0.765 2.18 0.28 0.28 0.28 0.28 108.52 12.76 108.52 12.76 108.035 13.46 108.035 13.46 108.52 13.68 108.52 13.68 108.035 14.38 108.035 14.38 108.52 14.6 108.52 14.6 108.035 15.3 108.035 15.3 108.52 15.52 108.52 15.52 108.035 16.22 108.035 16.22 108.52 16.44 108.52 16.44 108.035 17.14 108.035 17.14 108.52 17.36 108.52 17.36 108.035 18.06 108.035 18.06 108.52 18.28 108.52 18.28 108.035 18.98 108.035 18.98 108.52 24.72 108.52 24.72 108.035 25.42 108.035 25.42 108.52 26.1 108.52 26.1 108.035 26.8 108.035 26.8 108.52 30.7 108.52 30.7 108.035 31.4 108.035 31.4 108.52 31.62 108.52 31.62 108.035 32.32 108.035 32.32 108.52 32.54 108.52 32.54 108.035 33.24 108.035 33.24 108.52 33.46 108.52 33.46 108.035 34.16 108.035 34.16 108.52 34.38 108.52 34.38 108.035 35.08 108.035 35.08 108.52 35.3 108.52 35.3 108.035 36 108.035 36 108.52 36.22 108.52 36.22 108.035 36.92 108.035 36.92 108.52 37.14 108.52 37.14 108.035 37.84 108.035 37.84 108.52 38.06 108.52 38.06 108.035 38.76 108.035 38.76 108.52 38.98 108.52 38.98 108.035 39.68 108.035 39.68 108.52 39.9 108.52 39.9 108.035 40.6 108.035 40.6 108.52 40.82 108.52 40.82 108.035 41.52 108.035 41.52 108.52 41.74 108.52 41.74 108.035 42.44 108.035 42.44 108.52 42.66 108.52 42.66 108.035 43.36 108.035 43.36 108.52 46.8 108.52 46.8 108.035 47.5 108.035 47.5 108.52 47.72 108.52 47.72 108.035 48.42 108.035 48.42 108.52 48.64 108.52 48.64 108.035 49.34 108.035 49.34 108.52 49.56 108.52 49.56 108.035 50.26 108.035 50.26 108.52 50.48 108.52 50.48 108.035 51.18 108.035 51.18 108.52 51.4 108.52 51.4 108.035 52.1 108.035 52.1 108.52 52.32 108.52 52.32 108.035 53.02 108.035 53.02 108.52 53.24 108.52 53.24 108.035 53.94 108.035 53.94 108.52 54.16 108.52 54.16 108.035 54.86 108.035 54.86 108.52 56 108.52 56 108.035 56.7 108.035 56.7 108.52 56.92 108.52 56.92 108.035 57.62 108.035 57.62 108.52 57.84 108.52 57.84 108.035 58.54 108.035 58.54 108.52 58.76 108.52 58.76 108.035 59.46 108.035 59.46 108.52 59.68 108.52 59.68 108.035 60.38 108.035 60.38 108.52 60.6 108.52 60.6 108.035 61.3 108.035 61.3 108.52 61.52 108.52 61.52 108.035 62.22 108.035 62.22 108.52 62.44 108.52 62.44 108.035 63.14 108.035 63.14 108.52 63.36 108.52 63.36 108.035 64.06 108.035 64.06 108.52 ; LAYER met3 ; POLYGON 55.365 108.965 55.365 108.96 55.58 108.96 55.58 108.64 55.365 108.64 55.365 108.635 55.035 108.635 55.035 108.64 54.82 108.64 54.82 108.96 55.035 108.96 55.035 108.965 ; POLYGON 25.925 108.965 25.925 108.96 26.14 108.96 26.14 108.64 25.925 108.64 25.925 108.635 25.595 108.635 25.595 108.64 25.38 108.64 25.38 108.96 25.595 108.96 25.595 108.965 ; + POLYGON 74.915 97.745 74.915 97.415 74.585 97.415 74.585 97.43 57.58 97.43 57.58 97.73 74.585 97.73 74.585 97.745 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; POLYGON 65.84 108.4 65.84 97.52 91.6 97.52 91.6 89.97 90.8 89.97 90.8 88.87 91.6 88.87 91.6 88.61 90.8 88.61 90.8 87.51 91.6 87.51 91.6 87.25 90.8 87.25 90.8 86.15 91.6 86.15 91.6 85.89 90.8 85.89 90.8 84.79 91.6 84.79 91.6 73.65 90.8 73.65 90.8 72.55 91.6 72.55 91.6 72.29 90.8 72.29 90.8 71.19 91.6 71.19 91.6 70.93 90.8 70.93 90.8 69.83 91.6 69.83 91.6 69.57 90.8 69.57 90.8 68.47 91.6 68.47 91.6 68.21 90.8 68.21 90.8 67.11 91.6 67.11 91.6 66.85 90.8 66.85 90.8 65.75 91.6 65.75 91.6 65.49 90.8 65.49 90.8 64.39 91.6 64.39 91.6 64.13 90.8 64.13 90.8 63.03 91.6 63.03 91.6 62.77 90.8 62.77 90.8 61.67 91.6 61.67 91.6 61.41 90.8 61.41 90.8 60.31 91.6 60.31 91.6 60.05 90.8 60.05 90.8 58.95 91.6 58.95 91.6 58.69 90.8 58.69 90.8 57.59 91.6 57.59 91.6 57.33 90.8 57.33 90.8 56.23 91.6 56.23 91.6 55.97 90.8 55.97 90.8 54.87 91.6 54.87 91.6 54.61 90.8 54.61 90.8 53.51 91.6 53.51 91.6 53.25 90.8 53.25 90.8 52.15 91.6 52.15 91.6 51.89 90.8 51.89 90.8 50.79 91.6 50.79 91.6 50.53 90.8 50.53 90.8 49.43 91.6 49.43 91.6 49.17 90.8 49.17 90.8 48.07 91.6 48.07 91.6 47.81 90.8 47.81 90.8 46.71 91.6 46.71 91.6 46.45 90.8 46.45 90.8 45.35 91.6 45.35 91.6 45.09 90.8 45.09 90.8 43.99 91.6 43.99 91.6 43.73 90.8 43.73 90.8 42.63 91.6 42.63 91.6 42.37 90.8 42.37 90.8 41.27 91.6 41.27 91.6 41.01 90.8 41.01 90.8 39.91 91.6 39.91 91.6 36.93 90.8 36.93 90.8 35.83 91.6 35.83 91.6 35.57 90.8 35.57 90.8 34.47 91.6 34.47 91.6 34.21 90.8 34.21 90.8 33.11 91.6 33.11 91.6 32.85 90.8 32.85 90.8 31.75 91.6 31.75 91.6 31.49 90.8 31.49 90.8 30.39 91.6 30.39 91.6 30.13 90.8 30.13 90.8 29.03 91.6 29.03 91.6 28.77 90.8 28.77 90.8 27.67 91.6 27.67 91.6 27.41 90.8 27.41 90.8 26.31 91.6 26.31 91.6 26.05 90.8 26.05 90.8 24.95 91.6 24.95 91.6 24.69 90.8 24.69 90.8 23.59 91.6 23.59 91.6 23.33 90.8 23.33 90.8 22.23 91.6 22.23 91.6 16.53 90.8 16.53 90.8 15.43 91.6 15.43 91.6 15.17 90.8 15.17 90.8 14.07 91.6 14.07 91.6 11.28 65.84 11.28 65.84 0.4 0.4 0.4 0.4 108.4 ; @@ -1559,47 +1565,54 @@ MACRO sb_0__1_ POLYGON 64.64 107.2 64.64 96.32 90.4 96.32 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 12.48 64.64 12.48 64.64 1.6 1.6 1.6 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 107.2 ; LAYER met1 ; RECT 45.68 108.56 46.32 109.04 ; - POLYGON 47.22 98.84 47.22 98.545 47.295 98.545 47.295 98.315 47.005 98.315 47.005 98.545 47.08 98.545 47.08 98.84 ; - POLYGON 58.81 98.56 58.81 98.5 62.4 98.5 62.4 98.545 62.69 98.545 62.69 98.315 62.4 98.315 62.4 98.36 58.81 98.36 58.81 98.3 58.49 98.3 58.49 98.56 ; - POLYGON 73.44 12.48 73.44 11.32 50.07 11.32 50.07 11.26 49.75 11.26 49.75 11.32 48.275 11.32 48.275 11.275 47.985 11.275 47.985 11.505 48.275 11.505 48.275 11.46 49.75 11.46 49.75 11.52 50.07 11.52 50.07 11.46 73.3 11.46 73.3 12.48 ; - POLYGON 47.755 10.485 47.755 10.255 47.68 10.255 47.68 9.96 47.54 9.96 47.54 10.255 47.465 10.255 47.465 10.485 ; + RECT 74.59 97.28 74.91 97.54 ; + POLYGON 59.27 97.54 59.27 97.48 62.08 97.48 62.08 97.525 62.37 97.525 62.37 97.295 62.08 97.295 62.08 97.34 59.27 97.34 59.27 97.28 58.95 97.28 58.95 97.54 ; + RECT 49.29 97.28 49.61 97.54 ; + POLYGON 47.7 97.525 47.7 97.295 47.41 97.295 47.41 97.34 44.32 97.34 44.32 97.48 47.41 97.48 47.41 97.525 ; + POLYGON 80.34 12.14 80.34 11.32 67.075 11.32 67.075 11.275 66.785 11.275 66.785 11.505 67.075 11.505 67.075 11.46 80.2 11.46 80.2 12.14 ; + POLYGON 49.52 11.8 49.52 11.32 48.675 11.32 48.675 11.275 48.385 11.275 48.385 11.505 48.675 11.505 48.675 11.46 49.38 11.46 49.38 11.8 ; + POLYGON 84.57 11.52 84.57 11.26 84.25 11.26 84.25 11.32 81.795 11.32 81.795 11.275 81.505 11.275 81.505 11.505 81.795 11.505 81.795 11.46 84.25 11.46 84.25 11.52 ; + POLYGON 65.25 11.52 65.25 11.26 64.93 11.26 64.93 11.275 64.88 11.275 64.88 11.505 64.93 11.505 64.93 11.52 ; + POLYGON 54.67 11.52 54.67 11.46 57.125 11.46 57.125 11.505 57.415 11.505 57.415 11.275 57.125 11.275 57.125 11.32 54.67 11.32 54.67 11.26 54.35 11.26 54.35 11.52 ; + POLYGON 63.41 10.5 63.41 10.24 63.09 10.24 63.09 10.3 37.88 10.3 37.88 10.44 63.09 10.44 63.09 10.5 ; + POLYGON 33.97 0.64 33.97 0.58 34.215 0.58 34.215 0.625 34.505 0.625 34.505 0.395 34.215 0.395 34.215 0.44 33.97 0.44 33.97 0.38 33.65 0.38 33.65 0.64 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 108.52 46.32 108.28 65.96 108.28 65.96 106.6 65.48 106.6 65.48 105.56 65.96 105.56 65.96 103.88 65.48 103.88 65.48 102.84 65.96 102.84 65.96 101.16 65.48 101.16 65.48 100.12 65.96 100.12 65.96 98.44 46.32 98.44 46.32 97.4 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 46.32 11.4 46.32 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 0.76 97.4 0.76 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 0.76 102.84 0.76 103.88 0.28 103.88 0.28 105.56 0.76 105.56 0.76 106.6 0.28 106.6 0.28 108.28 45.68 108.28 45.68 108.52 ; LAYER li1 ; - RECT 0 108.715 66.24 108.885 ; - RECT 62.56 105.995 66.24 106.165 ; + POLYGON 66.24 108.885 66.24 108.715 59.715 108.715 59.715 107.99 59.425 107.99 59.425 108.715 57.945 108.715 57.945 107.915 57.615 107.915 57.615 108.715 57.105 108.715 57.105 108.235 56.775 108.235 56.775 108.715 56.265 108.715 56.265 108.235 55.935 108.235 55.935 108.715 55.425 108.715 55.425 108.235 55.095 108.235 55.095 108.715 54.585 108.715 54.585 108.235 54.255 108.235 54.255 108.715 53.745 108.715 53.745 108.235 53.415 108.235 53.415 108.715 52.355 108.715 52.355 107.99 52.065 107.99 52.065 108.715 51.465 108.715 51.465 108.235 51.135 108.235 51.135 108.715 50.625 108.715 50.625 108.235 50.295 108.235 50.295 108.715 49.785 108.715 49.785 108.235 49.455 108.235 49.455 108.715 48.945 108.715 48.945 108.235 48.615 108.235 48.615 108.715 48.105 108.715 48.105 108.235 47.775 108.235 47.775 108.715 47.265 108.715 47.265 107.915 46.935 107.915 46.935 108.715 45.745 108.715 45.745 108.255 45.49 108.255 45.49 108.715 44.82 108.715 44.82 108.255 44.65 108.255 44.65 108.715 43.98 108.715 43.98 108.255 43.81 108.255 43.81 108.715 43.14 108.715 43.14 108.255 42.97 108.255 42.97 108.715 42.3 108.715 42.3 108.255 41.995 108.255 41.995 108.715 37.635 108.715 37.635 107.99 37.345 107.99 37.345 108.715 36.745 108.715 36.745 108.235 36.415 108.235 36.415 108.715 35.905 108.715 35.905 108.235 35.575 108.235 35.575 108.715 35.065 108.715 35.065 108.235 34.735 108.235 34.735 108.715 34.225 108.715 34.225 108.235 33.895 108.235 33.895 108.715 33.385 108.715 33.385 108.235 33.055 108.235 33.055 108.715 32.545 108.715 32.545 107.915 32.215 107.915 32.215 108.715 31.225 108.715 31.225 108.235 30.895 108.235 30.895 108.715 30.385 108.715 30.385 108.235 30.055 108.235 30.055 108.715 29.545 108.715 29.545 108.235 29.215 108.235 29.215 108.715 28.705 108.715 28.705 108.235 28.375 108.235 28.375 108.715 27.865 108.715 27.865 108.235 27.535 108.235 27.535 108.715 27.025 108.715 27.025 107.915 26.695 107.915 26.695 108.715 22.455 108.715 22.455 107.99 22.165 107.99 22.165 108.715 19.265 108.715 19.265 108.235 18.935 108.235 18.935 108.715 18.425 108.715 18.425 108.235 18.095 108.235 18.095 108.715 17.585 108.715 17.585 108.235 17.255 108.235 17.255 108.715 16.745 108.715 16.745 108.235 16.415 108.235 16.415 108.715 15.905 108.715 15.905 108.235 15.575 108.235 15.575 108.715 15.065 108.715 15.065 107.915 14.735 107.915 14.735 108.715 7.735 108.715 7.735 107.99 7.445 107.99 7.445 108.715 0 108.715 0 108.885 ; + RECT 65.32 105.995 66.24 106.165 ; RECT 0 105.995 3.68 106.165 ; RECT 65.32 103.275 66.24 103.445 ; RECT 0 103.275 3.68 103.445 ; RECT 65.32 100.555 66.24 100.725 ; RECT 0 100.555 3.68 100.725 ; - RECT 64.86 97.835 92 98.005 ; + POLYGON 92 98.005 92 97.835 89.615 97.835 89.615 97.11 89.325 97.11 89.325 97.835 82.255 97.835 82.255 97.11 81.965 97.11 81.965 97.835 77.835 97.835 77.835 97.3 77.325 97.3 77.325 97.835 75.365 97.835 75.365 97.435 75.035 97.435 75.035 97.835 71.625 97.835 71.625 97.375 71.32 97.375 71.32 97.835 70.65 97.835 70.65 97.375 70.48 97.375 70.48 97.835 69.81 97.835 69.81 97.375 69.64 97.375 69.64 97.835 68.97 97.835 68.97 97.375 68.8 97.375 68.8 97.835 68.13 97.835 68.13 97.375 67.875 97.375 67.875 97.835 67.535 97.835 67.535 97.11 67.245 97.11 67.245 97.835 64.4 97.835 64.4 98.005 ; RECT 0 97.835 3.68 98.005 ; RECT 91.54 95.115 92 95.285 ; RECT 0 95.115 3.68 95.285 ; RECT 91.54 92.395 92 92.565 ; RECT 0 92.395 3.68 92.565 ; - RECT 90.16 89.675 92 89.845 ; + RECT 91.54 89.675 92 89.845 ; RECT 0 89.675 3.68 89.845 ; - RECT 90.16 86.955 92 87.125 ; + RECT 91.08 86.955 92 87.125 ; RECT 0 86.955 3.68 87.125 ; - RECT 90.16 84.235 92 84.405 ; + RECT 91.08 84.235 92 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 90.16 81.515 92 81.685 ; + RECT 91.54 81.515 92 81.685 ; RECT 0 81.515 3.68 81.685 ; RECT 91.54 78.795 92 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 91.08 76.075 92 76.245 ; + RECT 91.54 76.075 92 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 91.08 73.355 92 73.525 ; + RECT 91.54 73.355 92 73.525 ; RECT 0 73.355 3.68 73.525 ; RECT 91.08 70.635 92 70.805 ; RECT 0 70.635 3.68 70.805 ; RECT 91.08 67.915 92 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 91.08 65.195 92 65.365 ; + RECT 90.16 65.195 92 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 91.08 62.475 92 62.645 ; + RECT 90.16 62.475 92 62.645 ; RECT 0 62.475 3.68 62.645 ; RECT 91.08 59.755 92 59.925 ; RECT 0 59.755 3.68 59.925 ; @@ -1609,9 +1622,9 @@ MACRO sb_0__1_ RECT 0 54.315 3.68 54.485 ; RECT 91.08 51.595 92 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 90.16 48.875 92 49.045 ; + RECT 91.08 48.875 92 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 90.16 46.155 92 46.325 ; + RECT 91.08 46.155 92 46.325 ; RECT 0 46.155 3.68 46.325 ; RECT 91.08 43.435 92 43.605 ; RECT 0 43.435 3.68 43.605 ; @@ -1621,49 +1634,63 @@ MACRO sb_0__1_ RECT 0 37.995 3.68 38.165 ; RECT 91.08 35.275 92 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 91.08 32.555 92 32.725 ; + RECT 91.54 32.555 92 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 91.08 29.835 92 30.005 ; + RECT 91.54 29.835 92 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 91.08 27.115 92 27.285 ; + RECT 91.54 27.115 92 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 91.08 24.395 92 24.565 ; + RECT 91.54 24.395 92 24.565 ; RECT 0 24.395 3.68 24.565 ; RECT 91.08 21.675 92 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 90.16 18.955 92 19.125 ; + RECT 91.08 18.955 92 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 90.16 16.235 92 16.405 ; + RECT 91.54 16.235 92 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 91.08 13.515 92 13.685 ; + RECT 91.54 13.515 92 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 62.56 10.795 92 10.965 ; + POLYGON 89.615 11.69 89.615 10.965 92 10.965 92 10.795 63.02 10.795 63.02 10.965 63.845 10.965 63.845 11.5 64.355 11.5 64.355 10.965 66.315 10.965 66.315 11.365 66.645 11.365 66.645 10.965 67.245 10.965 67.245 11.69 67.535 11.69 67.535 10.965 78.565 10.965 78.565 11.5 79.075 11.5 79.075 10.965 81.035 10.965 81.035 11.365 81.365 11.365 81.365 10.965 81.965 10.965 81.965 11.69 82.255 11.69 82.255 10.965 89.325 10.965 89.325 11.69 ; RECT 0 10.795 3.68 10.965 ; - RECT 62.56 8.075 66.24 8.245 ; + RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 62.56 2.635 66.24 2.805 ; + RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; + POLYGON 53.245 0.885 53.245 0.085 53.755 0.085 53.755 0.565 54.085 0.565 54.085 0.085 54.595 0.085 54.595 0.565 54.925 0.565 54.925 0.085 55.435 0.085 55.435 0.565 55.765 0.565 55.765 0.085 56.275 0.085 56.275 0.565 56.605 0.565 56.605 0.085 57.115 0.085 57.115 0.565 57.445 0.565 57.445 0.085 59.425 0.085 59.425 0.81 59.715 0.81 59.715 0.085 66.24 0.085 66.24 -0.085 0 -0.085 0 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 16.115 0.085 16.115 0.885 16.445 0.885 16.445 0.085 16.955 0.085 16.955 0.565 17.285 0.565 17.285 0.085 17.795 0.085 17.795 0.565 18.125 0.565 18.125 0.085 18.635 0.085 18.635 0.565 18.965 0.565 18.965 0.085 19.475 0.085 19.475 0.565 19.805 0.565 19.805 0.085 20.315 0.085 20.315 0.565 20.645 0.565 20.645 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 23.015 0.085 23.015 0.885 23.345 0.885 23.345 0.085 23.855 0.085 23.855 0.565 24.185 0.565 24.185 0.085 24.695 0.085 24.695 0.565 25.025 0.565 25.025 0.085 25.535 0.085 25.535 0.565 25.865 0.565 25.865 0.085 26.375 0.085 26.375 0.565 26.705 0.565 26.705 0.085 27.215 0.085 27.215 0.565 27.545 0.565 27.545 0.085 32.175 0.085 32.175 0.565 32.345 0.565 32.345 0.085 33.015 0.085 33.015 0.565 33.185 0.565 33.185 0.085 33.775 0.085 33.775 0.565 34.105 0.565 34.105 0.085 34.615 0.085 34.615 0.565 34.945 0.565 34.945 0.085 35.455 0.085 35.455 0.885 35.785 0.885 35.785 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 38.235 0.085 38.235 0.565 38.565 0.565 38.565 0.085 39.075 0.085 39.075 0.565 39.405 0.565 39.405 0.085 39.915 0.085 39.915 0.565 40.245 0.565 40.245 0.085 40.755 0.085 40.755 0.565 41.085 0.565 41.085 0.085 41.595 0.085 41.595 0.565 41.925 0.565 41.925 0.085 42.435 0.085 42.435 0.885 42.765 0.885 42.765 0.085 44.175 0.085 44.175 0.885 44.505 0.885 44.505 0.085 45.015 0.085 45.015 0.565 45.345 0.565 45.345 0.085 45.855 0.085 45.855 0.565 46.185 0.565 46.185 0.085 46.695 0.085 46.695 0.565 47.025 0.565 47.025 0.085 47.535 0.085 47.535 0.565 47.865 0.565 47.865 0.085 48.375 0.085 48.375 0.565 48.705 0.565 48.705 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 52.915 0.085 52.915 0.885 ; POLYGON 66.07 108.63 66.07 97.75 91.83 97.75 91.83 11.05 66.07 11.05 66.07 0.17 0.17 0.17 0.17 108.63 ; LAYER mcon ; - RECT 62.46 98.345 62.63 98.515 ; - RECT 47.065 98.345 47.235 98.515 ; - RECT 48.045 11.305 48.215 11.475 ; - RECT 47.525 10.285 47.695 10.455 ; + RECT 74.665 97.325 74.835 97.495 ; + RECT 62.14 97.325 62.31 97.495 ; + RECT 49.365 97.325 49.535 97.495 ; + RECT 47.47 97.325 47.64 97.495 ; + RECT 81.565 11.305 81.735 11.475 ; + RECT 66.845 11.305 67.015 11.475 ; + RECT 64.94 11.305 65.11 11.475 ; + RECT 57.185 11.305 57.355 11.475 ; + RECT 48.445 11.305 48.615 11.475 ; + RECT 34.275 0.425 34.445 0.595 ; LAYER via ; RECT 55.125 108.725 55.275 108.875 ; RECT 25.685 108.725 25.835 108.875 ; - RECT 58.575 98.355 58.725 98.505 ; RECT 55.125 97.845 55.275 97.995 ; - RECT 49.835 11.315 49.985 11.465 ; + RECT 74.675 97.335 74.825 97.485 ; + RECT 59.035 97.335 59.185 97.485 ; + RECT 49.375 97.335 49.525 97.485 ; + RECT 84.335 11.315 84.485 11.465 ; + RECT 65.015 11.315 65.165 11.465 ; + RECT 54.435 11.315 54.585 11.465 ; RECT 55.125 10.805 55.275 10.955 ; + RECT 63.175 10.295 63.325 10.445 ; + RECT 33.735 0.435 33.885 0.585 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 108.7 55.3 108.9 ; RECT 25.66 108.7 25.86 108.9 ; + RECT 74.65 97.48 74.85 97.68 ; + RECT 90.75 68.92 90.95 69.12 ; RECT 90.75 53.96 90.95 54.16 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__2__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__2__icv_in_design.lef index 40310c3..02b9274 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__2__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_0__2__icv_in_design.lef @@ -1232,23 +1232,36 @@ MACRO sb_0__2_ LAYER met3 ; POLYGON 55.365 98.085 55.365 98.08 55.58 98.08 55.58 97.76 55.365 97.76 55.365 97.755 55.035 97.755 55.035 97.76 54.82 97.76 54.82 98.08 55.035 98.08 55.035 98.085 ; POLYGON 25.925 98.085 25.925 98.08 26.14 98.08 26.14 97.76 25.925 97.76 25.925 97.755 25.595 97.755 25.595 97.76 25.38 97.76 25.38 98.08 25.595 98.08 25.595 98.085 ; - POLYGON 66.175 11.385 66.175 11.055 65.845 11.055 65.845 11.07 57.12 11.07 57.12 11.37 65.845 11.37 65.845 11.385 ; + POLYGON 74.915 11.385 74.915 11.055 74.585 11.055 74.585 11.07 58.04 11.07 58.04 11.37 74.585 11.37 74.585 11.385 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; POLYGON 91.6 97.52 91.6 91.33 90.8 91.33 90.8 90.23 91.6 90.23 91.6 77.05 90.8 77.05 90.8 75.95 91.6 75.95 91.6 75.69 90.8 75.69 90.8 74.59 91.6 74.59 91.6 74.33 90.8 74.33 90.8 73.23 91.6 73.23 91.6 72.97 90.8 72.97 90.8 71.87 91.6 71.87 91.6 71.61 90.8 71.61 90.8 70.51 91.6 70.51 91.6 70.25 90.8 70.25 90.8 69.15 91.6 69.15 91.6 68.89 90.8 68.89 90.8 67.79 91.6 67.79 91.6 67.53 90.8 67.53 90.8 66.43 91.6 66.43 91.6 66.17 90.8 66.17 90.8 65.07 91.6 65.07 91.6 64.81 90.8 64.81 90.8 63.71 91.6 63.71 91.6 63.45 90.8 63.45 90.8 62.35 91.6 62.35 91.6 62.09 90.8 62.09 90.8 60.99 91.6 60.99 91.6 60.73 90.8 60.73 90.8 59.63 91.6 59.63 91.6 59.37 90.8 59.37 90.8 58.27 91.6 58.27 91.6 58.01 90.8 58.01 90.8 56.91 91.6 56.91 91.6 56.65 90.8 56.65 90.8 55.55 91.6 55.55 91.6 55.29 90.8 55.29 90.8 54.19 91.6 54.19 91.6 53.93 90.8 53.93 90.8 52.83 91.6 52.83 91.6 51.89 90.8 51.89 90.8 50.79 91.6 50.79 91.6 50.53 90.8 50.53 90.8 49.43 91.6 49.43 91.6 48.49 90.8 48.49 90.8 47.39 91.6 47.39 91.6 47.13 90.8 47.13 90.8 46.03 91.6 46.03 91.6 45.77 90.8 45.77 90.8 44.67 91.6 44.67 91.6 44.41 90.8 44.41 90.8 43.31 91.6 43.31 91.6 43.05 90.8 43.05 90.8 41.95 91.6 41.95 91.6 41.69 90.8 41.69 90.8 40.59 91.6 40.59 91.6 40.33 90.8 40.33 90.8 39.23 91.6 39.23 91.6 38.97 90.8 38.97 90.8 37.87 91.6 37.87 91.6 37.61 90.8 37.61 90.8 36.51 91.6 36.51 91.6 36.25 90.8 36.25 90.8 35.15 91.6 35.15 91.6 34.21 90.8 34.21 90.8 33.11 91.6 33.11 91.6 32.85 90.8 32.85 90.8 31.75 91.6 31.75 91.6 31.49 90.8 31.49 90.8 30.39 91.6 30.39 91.6 30.13 90.8 30.13 90.8 29.03 91.6 29.03 91.6 28.77 90.8 28.77 90.8 27.67 91.6 27.67 91.6 27.41 90.8 27.41 90.8 26.31 91.6 26.31 91.6 26.05 90.8 26.05 90.8 24.95 91.6 24.95 91.6 24.69 90.8 24.69 90.8 23.59 91.6 23.59 91.6 23.33 90.8 23.33 90.8 22.23 91.6 22.23 91.6 21.29 90.8 21.29 90.8 20.19 91.6 20.19 91.6 19.93 90.8 19.93 90.8 18.83 91.6 18.83 91.6 18.57 90.8 18.57 90.8 17.47 91.6 17.47 91.6 15.17 90.8 15.17 90.8 14.07 91.6 14.07 91.6 11.28 65.84 11.28 65.84 0.4 0.4 0.4 0.4 97.52 ; LAYER met2 ; RECT 55.06 97.735 55.34 98.105 ; RECT 25.62 97.735 25.9 98.105 ; - POLYGON 66.08 12.82 66.08 11.405 66.15 11.405 66.15 11.035 65.87 11.035 65.87 11.405 65.94 11.405 65.94 12.82 ; + POLYGON 39.86 21.32 39.86 0.24 39.9 0.24 39.9 0.1 39.72 0.1 39.72 21.32 ; + POLYGON 74.82 12.14 74.82 11.405 74.89 11.405 74.89 11.035 74.61 11.035 74.61 11.405 74.68 11.405 74.68 12.14 ; + POLYGON 63.32 6.02 63.32 0.24 63.36 0.24 63.36 0.1 63.18 0.1 63.18 6.02 ; + POLYGON 14.56 5.17 14.56 0.1 14.38 0.1 14.38 0.24 14.42 0.24 14.42 5.17 ; + RECT 64.04 0.35 64.3 0.67 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; POLYGON 91.72 97.64 91.72 11.16 87.52 11.16 87.52 11.645 86.82 11.645 86.82 11.16 86.14 11.16 86.14 11.645 85.44 11.645 85.44 11.16 83.38 11.16 83.38 11.645 82.68 11.645 82.68 11.16 82.46 11.16 82.46 11.645 81.76 11.645 81.76 11.16 81.54 11.16 81.54 11.645 80.84 11.645 80.84 11.16 80.62 11.16 80.62 11.645 79.92 11.645 79.92 11.16 79.7 11.16 79.7 11.645 79 11.645 79 11.16 78.78 11.16 78.78 11.645 78.08 11.645 78.08 11.16 69.12 11.16 69.12 11.645 68.42 11.645 68.42 11.16 65.96 11.16 65.96 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 61.3 0.28 61.3 0.765 60.6 0.765 60.6 0.28 60.38 0.28 60.38 0.765 59.68 0.765 59.68 0.28 59.46 0.28 59.46 0.765 58.76 0.765 58.76 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 53.94 0.28 53.94 0.765 53.24 0.765 53.24 0.28 53.02 0.28 53.02 0.765 52.32 0.765 52.32 0.28 52.1 0.28 52.1 0.765 51.4 0.765 51.4 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 50.26 0.28 50.26 0.765 49.56 0.765 49.56 0.28 41.52 0.28 41.52 0.765 40.82 0.765 40.82 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 37.84 0.28 37.84 0.765 37.14 0.765 37.14 0.28 36.92 0.28 36.92 0.765 36.22 0.765 36.22 0.28 36 0.28 36 0.765 35.3 0.765 35.3 0.28 35.08 0.28 35.08 0.765 34.38 0.765 34.38 0.28 34.16 0.28 34.16 0.765 33.46 0.765 33.46 0.28 33.24 0.28 33.24 0.765 32.54 0.765 32.54 0.28 26.8 0.28 26.8 0.765 26.1 0.765 26.1 0.28 21.74 0.28 21.74 0.765 21.04 0.765 21.04 0.28 20.82 0.28 20.82 0.765 20.12 0.765 20.12 0.28 19.9 0.28 19.9 0.765 19.2 0.765 19.2 0.28 18.98 0.28 18.98 0.765 18.28 0.765 18.28 0.28 18.06 0.28 18.06 0.765 17.36 0.765 17.36 0.28 17.14 0.28 17.14 0.765 16.44 0.765 16.44 0.28 16.22 0.28 16.22 0.765 15.52 0.765 15.52 0.28 15.3 0.28 15.3 0.765 14.6 0.765 14.6 0.28 14.38 0.28 14.38 0.765 13.68 0.765 13.68 0.28 13.46 0.28 13.46 0.765 12.76 0.765 12.76 0.28 12.54 0.28 12.54 0.765 11.84 0.765 11.84 0.28 11.62 0.28 11.62 0.765 10.92 0.765 10.92 0.28 10.7 0.28 10.7 0.765 10 0.765 10 0.28 9.78 0.28 9.78 0.765 9.08 0.765 9.08 0.28 8.86 0.28 8.86 0.765 8.16 0.765 8.16 0.28 2.88 0.28 2.88 0.765 2.18 0.765 2.18 0.28 0.28 0.28 0.28 97.64 ; LAYER met1 ; RECT 45.68 97.68 46.32 98.16 ; - POLYGON 61.57 11.52 61.57 11.26 61.25 11.26 61.25 11.32 60.65 11.32 60.65 11.26 60.33 11.26 60.33 11.32 50.975 11.32 50.975 11.275 50.685 11.275 50.685 11.32 50.53 11.32 50.53 11.26 50.21 11.26 50.21 11.32 47.7 11.32 47.7 11.275 47.41 11.275 47.41 11.32 46.39 11.32 46.39 11.26 46.07 11.26 46.07 11.52 46.39 11.52 46.39 11.46 47.41 11.46 47.41 11.505 47.7 11.505 47.7 11.46 50.21 11.46 50.21 11.52 50.53 11.52 50.53 11.46 50.685 11.46 50.685 11.505 50.975 11.505 50.975 11.46 60.33 11.46 60.33 11.52 60.65 11.52 60.65 11.46 61.25 11.46 61.25 11.52 ; - RECT 63.09 10.24 63.41 10.5 ; - POLYGON 58.81 10.5 58.81 10.24 58.49 10.24 58.49 10.3 57.49 10.3 57.49 10.255 57.2 10.255 57.2 10.485 57.49 10.485 57.49 10.44 58.49 10.44 58.49 10.5 ; - POLYGON 56.97 10.5 56.97 10.24 56.65 10.24 56.65 10.3 55.575 10.3 55.575 10.255 55.285 10.255 55.285 10.485 55.575 10.485 55.575 10.44 56.65 10.44 56.65 10.5 ; + POLYGON 82.27 11.52 82.27 11.26 81.95 11.26 81.95 11.32 80.015 11.32 80.015 11.275 79.725 11.275 79.725 11.32 76.29 11.32 76.29 11.26 75.97 11.26 75.97 11.52 76.29 11.52 76.29 11.46 79.725 11.46 79.725 11.505 80.015 11.505 80.015 11.46 81.95 11.46 81.95 11.52 ; + POLYGON 65.71 11.52 65.71 11.26 65.39 11.26 65.39 11.32 62.935 11.32 62.935 11.275 62.645 11.275 62.645 11.505 62.935 11.505 62.935 11.46 65.39 11.46 65.39 11.52 ; + POLYGON 56.97 11.52 56.97 11.505 57.015 11.505 57.015 11.275 56.97 11.275 56.97 11.26 56.65 11.26 56.65 11.52 ; + POLYGON 56.05 11.52 56.05 11.26 55.73 11.26 55.73 11.32 55.115 11.32 55.115 11.275 54.825 11.275 54.825 11.505 55.115 11.505 55.115 11.46 55.73 11.46 55.73 11.52 ; + POLYGON 52.37 11.52 52.37 11.26 52.05 11.26 52.05 11.32 51.435 11.32 51.435 11.275 51.145 11.275 51.145 11.505 51.435 11.505 51.435 11.46 52.05 11.46 52.05 11.52 ; + RECT 55.73 10.24 56.05 10.5 ; + POLYGON 52.37 10.5 52.37 10.24 52.05 10.24 52.05 10.3 51.895 10.3 51.895 10.255 51.605 10.255 51.605 10.485 51.895 10.485 51.895 10.44 52.05 10.44 52.05 10.5 ; + POLYGON 50.99 10.5 50.99 10.24 50.67 10.24 50.67 10.3 49.595 10.3 49.595 10.255 49.305 10.255 49.305 10.485 49.595 10.485 49.595 10.44 50.67 10.44 50.67 10.5 ; + POLYGON 64.33 0.64 64.33 0.38 64.01 0.38 64.01 0.44 59.255 0.44 59.255 0.395 58.965 0.395 58.965 0.625 59.255 0.625 59.255 0.58 64.01 0.58 64.01 0.64 ; + POLYGON 58.35 0.64 58.35 0.38 58.03 0.38 58.03 0.44 56.955 0.44 56.955 0.395 56.665 0.395 56.665 0.625 56.955 0.625 56.955 0.58 58.03 0.58 58.03 0.64 ; + POLYGON 50.99 0.64 50.99 0.38 50.67 0.38 50.67 0.44 49.225 0.44 49.225 0.395 48.935 0.395 48.935 0.625 49.225 0.625 49.225 0.58 50.67 0.58 50.67 0.64 ; + RECT 45.61 0.38 45.93 0.64 ; + POLYGON 38.57 0.64 38.57 0.58 43.325 0.58 43.325 0.625 43.615 0.625 43.615 0.395 43.325 0.395 43.325 0.44 38.57 0.44 38.57 0.38 38.25 0.38 38.25 0.64 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 97.64 46.32 97.4 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 46.32 11.4 46.32 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 45.68 97.4 45.68 97.64 ; LAYER met4 ; @@ -1256,50 +1269,50 @@ MACRO sb_0__2_ LAYER met5 ; POLYGON 90.4 96.32 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 12.48 64.64 12.48 64.64 1.6 1.6 1.6 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; LAYER li1 ; - RECT 0 97.835 92 98.005 ; - RECT 88.32 95.115 92 95.285 ; + POLYGON 92 98.005 92 97.835 89.615 97.835 89.615 97.11 89.325 97.11 89.325 97.835 82.255 97.835 82.255 97.11 81.965 97.11 81.965 97.835 67.535 97.835 67.535 97.11 67.245 97.11 67.245 97.835 52.355 97.835 52.355 97.11 52.065 97.11 52.065 97.835 37.635 97.835 37.635 97.11 37.345 97.11 37.345 97.835 22.455 97.835 22.455 97.11 22.165 97.11 22.165 97.835 7.735 97.835 7.735 97.11 7.445 97.11 7.445 97.835 0 97.835 0 98.005 ; + RECT 91.54 95.115 92 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 88.32 92.395 92 92.565 ; + RECT 91.54 92.395 92 92.565 ; RECT 0 92.395 3.68 92.565 ; - RECT 88.32 89.675 92 89.845 ; + RECT 91.54 89.675 92 89.845 ; RECT 0 89.675 3.68 89.845 ; - RECT 88.32 86.955 92 87.125 ; + RECT 91.54 86.955 92 87.125 ; RECT 0 86.955 3.68 87.125 ; - RECT 88.32 84.235 92 84.405 ; + RECT 91.54 84.235 92 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 91.08 81.515 92 81.685 ; + RECT 91.54 81.515 92 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 91.08 78.795 92 78.965 ; + RECT 91.54 78.795 92 78.965 ; RECT 0 78.795 3.68 78.965 ; RECT 91.08 76.075 92 76.245 ; RECT 0 76.075 3.68 76.245 ; RECT 91.08 73.355 92 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 90.16 70.635 92 70.805 ; + RECT 88.32 70.635 92 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 90.16 67.915 92 68.085 ; + RECT 88.32 67.915 92 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 91.08 65.195 92 65.365 ; + RECT 91.54 65.195 92 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 90.16 62.475 92 62.645 ; + RECT 91.54 62.475 92 62.645 ; RECT 0 62.475 3.68 62.645 ; RECT 90.16 59.755 92 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 91.08 57.035 92 57.205 ; + RECT 90.16 57.035 92 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 91.08 54.315 92 54.485 ; + RECT 91.54 54.315 92 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 91.08 51.595 92 51.765 ; + RECT 91.54 51.595 92 51.765 ; RECT 0 51.595 3.68 51.765 ; RECT 91.08 48.875 92 49.045 ; RECT 0 48.875 3.68 49.045 ; RECT 91.08 46.155 92 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 88.32 43.435 92 43.605 ; + RECT 91.54 43.435 92 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 88.32 40.715 92 40.885 ; + RECT 91.54 40.715 92 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 88.32 37.995 92 38.165 ; + RECT 91.08 37.995 92 38.165 ; RECT 0 37.995 3.68 38.165 ; RECT 91.08 35.275 92 35.445 ; RECT 0 35.275 3.68 35.445 ; @@ -1309,48 +1322,63 @@ MACRO sb_0__2_ RECT 0 29.835 3.68 30.005 ; RECT 91.08 27.115 92 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 91.54 24.395 92 24.565 ; + RECT 91.08 24.395 92 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 88.32 21.675 92 21.845 ; + RECT 91.08 21.675 92 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 88.32 18.955 92 19.125 ; + RECT 91.08 18.955 92 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 88.32 16.235 92 16.405 ; + RECT 91.08 16.235 92 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 88.32 13.515 92 13.685 ; + RECT 91.08 13.515 92 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 63.48 10.795 92 10.965 ; + POLYGON 75.07 11.785 75.07 10.965 78.255 10.965 78.255 11.365 78.585 11.365 78.585 10.965 80.545 10.965 80.545 11.5 81.055 11.5 81.055 10.965 81.965 10.965 81.965 11.69 82.255 11.69 82.255 10.965 84.615 10.965 84.615 11.445 84.785 11.445 84.785 10.965 85.455 10.965 85.455 11.445 85.625 11.445 85.625 10.965 86.215 10.965 86.215 11.445 86.545 11.445 86.545 10.965 87.055 10.965 87.055 11.445 87.385 11.445 87.385 10.965 87.895 10.965 87.895 11.765 88.225 11.765 88.225 10.965 89.325 10.965 89.325 11.69 89.615 11.69 89.615 10.965 92 10.965 92 10.795 63.02 10.795 63.02 10.965 67.245 10.965 67.245 11.69 67.535 11.69 67.535 10.965 69.095 10.965 69.095 11.765 69.425 11.765 69.425 10.965 69.935 10.965 69.935 11.445 70.265 11.445 70.265 10.965 70.775 10.965 70.775 11.445 71.105 11.445 71.105 10.965 71.695 10.965 71.695 11.445 71.865 11.445 71.865 10.965 72.535 10.965 72.535 11.445 72.705 11.445 72.705 10.965 74.84 10.965 74.84 11.785 ; RECT 0 10.795 3.68 10.965 ; RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 62.56 2.635 66.24 2.805 ; + RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; + POLYGON 50.505 0.885 50.505 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 56.025 0.085 56.025 0.62 56.535 0.62 56.535 0.085 58.495 0.085 58.495 0.485 58.825 0.485 58.825 0.085 59.425 0.085 59.425 0.81 59.715 0.81 59.715 0.085 66.24 0.085 66.24 -0.085 0 -0.085 0 0.085 3.315 0.085 3.315 0.885 3.645 0.885 3.645 0.085 4.155 0.085 4.155 0.565 4.485 0.565 4.485 0.085 4.995 0.085 4.995 0.565 5.325 0.565 5.325 0.085 5.915 0.085 5.915 0.565 6.085 0.565 6.085 0.085 6.755 0.085 6.755 0.565 6.925 0.565 6.925 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 13.855 0.085 13.855 0.465 14.185 0.465 14.185 0.085 14.795 0.085 14.795 0.545 15.045 0.545 15.045 0.085 16.74 0.085 16.74 0.585 17.11 0.585 17.11 0.085 18.965 0.085 18.965 0.615 19.135 0.615 19.135 0.085 19.965 0.085 19.965 0.565 20.135 0.565 20.135 0.085 20.835 0.085 20.835 0.56 21.005 0.56 21.005 0.085 21.685 0.085 21.685 0.56 21.855 0.56 21.855 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 22.975 0.085 22.975 0.565 23.145 0.565 23.145 0.085 23.815 0.085 23.815 0.565 23.985 0.565 23.985 0.085 24.575 0.085 24.575 0.565 24.905 0.565 24.905 0.085 25.415 0.085 25.415 0.565 25.745 0.565 25.745 0.085 26.255 0.085 26.255 0.885 26.585 0.885 26.585 0.085 29.875 0.085 29.875 0.565 30.045 0.565 30.045 0.085 30.715 0.085 30.715 0.565 30.885 0.565 30.885 0.085 31.475 0.085 31.475 0.565 31.805 0.565 31.805 0.085 32.315 0.085 32.315 0.565 32.645 0.565 32.645 0.085 33.155 0.085 33.155 0.885 33.485 0.885 33.485 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 38.155 0.085 38.155 0.565 38.325 0.565 38.325 0.085 38.995 0.085 38.995 0.565 39.165 0.565 39.165 0.085 39.755 0.085 39.755 0.565 40.085 0.565 40.085 0.085 40.595 0.085 40.595 0.565 40.925 0.565 40.925 0.085 41.435 0.085 41.435 0.885 41.765 0.885 41.765 0.085 42.685 0.085 42.685 0.62 43.195 0.62 43.195 0.085 45.155 0.085 45.155 0.485 45.485 0.485 45.485 0.085 46.895 0.085 46.895 0.565 47.065 0.565 47.065 0.085 47.735 0.085 47.735 0.565 47.905 0.565 47.905 0.085 48.495 0.085 48.495 0.565 48.825 0.565 48.825 0.085 49.335 0.085 49.335 0.565 49.665 0.565 49.665 0.085 50.175 0.085 50.175 0.885 ; POLYGON 91.83 97.75 91.83 11.05 66.07 11.05 66.07 0.17 0.17 0.17 0.17 97.75 ; LAYER mcon ; - RECT 50.745 11.305 50.915 11.475 ; - RECT 47.47 11.305 47.64 11.475 ; - RECT 63.165 10.285 63.335 10.455 ; - RECT 57.26 10.285 57.43 10.455 ; - RECT 55.345 10.285 55.515 10.455 ; + RECT 79.785 11.305 79.955 11.475 ; + RECT 62.705 11.305 62.875 11.475 ; + RECT 56.785 11.305 56.955 11.475 ; + RECT 54.885 11.305 55.055 11.475 ; + RECT 51.205 11.305 51.375 11.475 ; + RECT 55.805 10.285 55.975 10.455 ; + RECT 51.665 10.285 51.835 10.455 ; + RECT 49.365 10.285 49.535 10.455 ; + RECT 59.025 0.425 59.195 0.595 ; + RECT 56.725 0.425 56.895 0.595 ; + RECT 48.995 0.425 49.165 0.595 ; + RECT 43.385 0.425 43.555 0.595 ; LAYER via ; RECT 55.125 97.845 55.275 97.995 ; RECT 25.685 97.845 25.835 97.995 ; - RECT 61.335 11.315 61.485 11.465 ; - RECT 60.415 11.315 60.565 11.465 ; - RECT 50.295 11.315 50.445 11.465 ; + RECT 82.035 11.315 82.185 11.465 ; + RECT 76.055 11.315 76.205 11.465 ; + RECT 65.475 11.315 65.625 11.465 ; + RECT 56.735 11.315 56.885 11.465 ; + RECT 55.815 11.315 55.965 11.465 ; + RECT 52.135 11.315 52.285 11.465 ; RECT 55.125 10.805 55.275 10.955 ; - RECT 63.175 10.295 63.325 10.445 ; - RECT 58.575 10.295 58.725 10.445 ; - RECT 56.735 10.295 56.885 10.445 ; + RECT 55.815 10.295 55.965 10.445 ; + RECT 52.135 10.295 52.285 10.445 ; + RECT 50.755 10.295 50.905 10.445 ; + RECT 64.095 0.435 64.245 0.585 ; + RECT 58.115 0.435 58.265 0.585 ; + RECT 50.755 0.435 50.905 0.585 ; + RECT 38.335 0.435 38.485 0.585 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 97.82 55.3 98.02 ; RECT 25.66 97.82 25.86 98.02 ; - RECT 65.91 11.12 66.11 11.32 ; + RECT 90.75 64.16 90.95 64.36 ; + RECT 74.65 11.12 74.85 11.32 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__0__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__0__icv_in_design.lef index 43bd84e..3e4ba24 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__0__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__0__icv_in_design.lef @@ -1733,8 +1733,12 @@ MACRO sb_1__0_ LAYER met2 ; RECT 80.82 97.735 81.1 98.105 ; RECT 51.38 97.735 51.66 98.105 ; - POLYGON 91.84 95.78 91.84 74.9 91.7 74.9 91.7 95.64 90.78 95.64 90.78 95.78 ; + POLYGON 88.62 97.82 88.62 94.62 88.48 94.62 88.48 97.68 88.44 97.68 88.44 97.82 ; + POLYGON 74.36 97.82 74.36 76.94 74.22 76.94 74.22 97.68 74.18 97.68 74.18 97.82 ; + POLYGON 73.05 97.765 73.05 97.395 72.98 97.395 72.98 96.32 72.84 96.32 72.84 97.395 72.77 97.395 72.77 97.765 ; RECT 10.9 86.855 11.18 87.225 ; + POLYGON 19.69 86.885 19.69 86.515 19.62 86.515 19.62 84.76 19.48 84.76 19.48 86.515 19.41 86.515 19.41 86.885 ; + RECT 7.46 86.37 7.72 86.69 ; RECT 80.82 -0.185 81.1 0.185 ; RECT 51.38 -0.185 51.66 0.185 ; RECT 10.9 -0.185 11.18 0.185 ; @@ -1742,9 +1746,9 @@ MACRO sb_1__0_ LAYER met3 ; POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; + POLYGON 73.075 97.745 73.075 97.415 72.745 97.415 72.745 97.43 69.395 97.43 69.395 97.415 69.065 97.415 69.065 97.745 69.395 97.745 69.395 97.73 72.745 97.73 72.745 97.745 ; POLYGON 11.205 87.205 11.205 87.2 11.42 87.2 11.42 86.88 11.205 86.88 11.205 86.875 10.875 86.875 10.875 86.88 10.66 86.88 10.66 87.2 10.875 87.2 10.875 87.205 ; - POLYGON 116.56 61.69 116.56 61.67 117.11 61.67 117.11 61.39 104.27 61.39 104.27 61.69 ; - POLYGON 116.56 45.37 116.56 45.35 117.11 45.35 117.11 45.07 87.94 45.07 87.94 45.37 ; + POLYGON 19.715 86.865 19.715 86.85 29.36 86.85 29.36 86.55 19.715 86.55 19.715 86.535 19.385 86.535 19.385 86.865 ; POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; POLYGON 11.205 0.165 11.205 0.16 11.42 0.16 11.42 -0.16 11.205 -0.16 11.205 -0.165 10.875 -0.165 10.875 -0.16 10.66 -0.16 10.66 0.16 10.875 0.16 10.875 0.165 ; @@ -1753,118 +1757,137 @@ MACRO sb_1__0_ POLYGON 90.4 96.32 90.4 85.44 116.16 85.44 116.16 77.32 112.96 77.32 112.96 70.92 116.16 70.92 116.16 56.92 112.96 56.92 112.96 50.52 116.16 50.52 116.16 36.52 112.96 36.52 112.96 30.12 116.16 30.12 116.16 16.12 112.96 16.12 112.96 9.72 116.16 9.72 116.16 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 27.36 85.44 27.36 96.32 ; LAYER met1 ; RECT 45.68 97.68 46.32 98.16 ; - POLYGON 81.26 88.3 81.26 87.48 71.69 87.48 71.69 87.42 71.37 87.42 71.37 87.68 71.69 87.68 71.69 87.62 81.12 87.62 81.12 88.3 ; - POLYGON 88.16 87.96 88.16 87.48 87.33 87.48 87.33 87.42 87.01 87.42 87.01 87.68 87.33 87.68 87.33 87.62 88.02 87.62 88.02 87.96 ; - RECT 62.63 87.42 62.95 87.68 ; - POLYGON 63.87 86.66 63.87 86.4 63.55 86.4 63.55 86.46 62.72 86.46 62.72 86.415 62.43 86.415 62.43 86.645 62.72 86.645 62.72 86.6 63.55 86.6 63.55 86.66 ; - POLYGON 59.27 86.66 59.27 86.645 59.635 86.645 59.635 86.415 59.27 86.415 59.27 86.4 58.95 86.4 58.95 86.66 ; - POLYGON 50.53 86.66 50.53 86.4 50.21 86.4 50.21 86.46 48.69 86.46 48.69 86.4 48.37 86.4 48.37 86.66 48.69 86.66 48.69 86.6 50.21 86.6 50.21 86.66 ; - POLYGON 37.19 86.66 37.19 86.6 37.345 86.6 37.345 86.645 37.635 86.645 37.635 86.415 37.345 86.415 37.345 86.46 37.19 86.46 37.19 86.4 36.87 86.4 36.87 86.66 ; - POLYGON 61.555 86.645 61.555 86.415 61.48 86.415 61.48 85.78 61.34 85.78 61.34 86.415 61.265 86.415 61.265 86.645 ; + POLYGON 79.51 97.54 79.51 97.28 79.42 97.28 79.42 97 79.28 97 79.28 97.28 79.19 97.28 79.19 97.54 ; + POLYGON 71.23 97.54 71.23 97.28 70.91 97.28 70.91 97.34 62.86 97.34 62.86 97 62.72 97 62.72 97.48 70.91 97.48 70.91 97.54 ; + POLYGON 54.67 97.54 54.67 97.48 54.825 97.48 54.825 97.525 55.115 97.525 55.115 97.295 54.825 97.295 54.825 97.34 54.67 97.34 54.67 97.28 54.35 97.28 54.35 97.54 ; + POLYGON 53.2 97.48 53.2 97 53.06 97 53.06 97.34 43.08 97.34 43.08 96.66 42.94 96.66 42.94 97.48 ; + POLYGON 89.17 87.68 89.17 87.42 88.85 87.42 88.85 87.48 88.695 87.48 88.695 87.435 88.405 87.435 88.405 87.665 88.695 87.665 88.695 87.62 88.85 87.62 88.85 87.68 ; + POLYGON 82.73 87.68 82.73 87.62 85.645 87.62 85.645 87.665 85.935 87.665 85.935 87.435 85.645 87.435 85.645 87.48 82.73 87.48 82.73 87.42 82.41 87.42 82.41 87.68 ; + POLYGON 72.15 87.68 72.15 87.62 76.905 87.62 76.905 87.665 77.195 87.665 77.195 87.435 76.905 87.435 76.905 87.48 72.15 87.48 72.15 87.42 71.83 87.42 71.83 87.68 ; + RECT 62.17 87.42 62.49 87.68 ; + POLYGON 44.09 87.68 44.09 87.42 43.77 87.42 43.77 87.48 42.64 87.48 42.64 87.435 42.35 87.435 42.35 87.665 42.64 87.665 42.64 87.62 43.77 87.62 43.77 87.68 ; + POLYGON 115.39 86.66 115.39 86.4 115.07 86.4 115.07 86.46 78.5 86.46 78.5 86.12 78.36 86.12 78.36 86.6 115.07 86.6 115.07 86.66 ; + POLYGON 77.21 86.66 77.21 86.6 77.58 86.6 77.58 86.645 77.87 86.645 77.87 86.415 77.58 86.415 77.58 86.46 77.21 86.46 77.21 86.4 76.89 86.4 76.89 86.66 ; + POLYGON 76.29 86.66 76.29 86.4 75.97 86.4 75.97 86.46 75.14 86.46 75.14 86.415 74.85 86.415 74.85 86.645 75.14 86.645 75.14 86.6 75.97 86.6 75.97 86.66 ; + POLYGON 16.03 86.66 16.03 86.6 67.92 86.6 67.92 86.12 67.78 86.12 67.78 86.46 16.03 86.46 16.03 86.4 15.71 86.4 15.71 86.66 ; + POLYGON 7.75 86.66 7.75 86.6 15.48 86.6 15.48 86.12 15.34 86.12 15.34 86.46 7.75 86.46 7.75 86.4 7.43 86.4 7.43 86.66 ; RECT 45.68 -0.24 96 0.24 ; POLYGON 46.32 97.64 46.32 97.4 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 46.32 87.56 46.32 86.52 95.36 86.52 95.36 86.76 96 86.76 96 86.52 117.48 86.52 117.48 84.84 117 84.84 117 83.8 117.48 83.8 117.48 82.12 117 82.12 117 81.08 117.48 81.08 117.48 79.4 117 79.4 117 78.36 117.48 78.36 117.48 76.68 117 76.68 117 75.64 117.48 75.64 117.48 73.96 117 73.96 117 72.92 117.48 72.92 117.48 71.24 117 71.24 117 70.2 117.48 70.2 117.48 68.52 117 68.52 117 67.48 117.48 67.48 117.48 65.8 117 65.8 117 64.76 117.48 64.76 117.48 63.08 117 63.08 117 62.04 117.48 62.04 117.48 60.36 117 60.36 117 59.32 117.48 59.32 117.48 57.64 117 57.64 117 56.6 117.48 56.6 117.48 54.92 117 54.92 117 53.88 117.48 53.88 117.48 52.2 117 52.2 117 51.16 117.48 51.16 117.48 49.48 117 49.48 117 48.44 117.48 48.44 117.48 46.76 117 46.76 117 45.72 117.48 45.72 117.48 44.04 117 44.04 117 43 117.48 43 117.48 41.32 117 41.32 117 40.28 117.48 40.28 117.48 38.6 117 38.6 117 37.56 117.48 37.56 117.48 35.88 117 35.88 117 34.84 117.48 34.84 117.48 33.16 117 33.16 117 32.12 117.48 32.12 117.48 30.44 117 30.44 117 29.4 117.48 29.4 117.48 27.72 117 27.72 117 26.68 117.48 26.68 117.48 25 117 25 117 23.96 117.48 23.96 117.48 22.28 117 22.28 117 21.24 117.48 21.24 117.48 19.56 117 19.56 117 18.52 117.48 18.52 117.48 16.84 117 16.84 117 15.8 117.48 15.8 117.48 14.12 117 14.12 117 13.08 117.48 13.08 117.48 11.4 117 11.4 117 10.36 117.48 10.36 117.48 8.68 117 8.68 117 7.64 117.48 7.64 117.48 5.96 117 5.96 117 4.92 117.48 4.92 117.48 3.24 117 3.24 117 2.2 117.48 2.2 117.48 0.52 96 0.52 96 0.28 45.68 0.28 45.68 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 45.68 86.52 45.68 87.56 26.04 87.56 26.04 89.24 26.52 89.24 26.52 90.28 26.04 90.28 26.04 91.96 26.52 91.96 26.52 93 26.04 93 26.04 94.68 26.52 94.68 26.52 95.72 26.04 95.72 26.04 97.4 45.68 97.4 45.68 97.64 ; LAYER li1 ; - RECT 25.76 97.835 92 98.005 ; - RECT 88.32 95.115 92 95.285 ; + POLYGON 92 98.005 92 97.835 89.615 97.835 89.615 97.11 89.325 97.11 89.325 97.835 88.92 97.835 88.92 97.015 88.69 97.015 88.69 97.835 87.265 97.835 87.265 97.375 86.96 97.375 86.96 97.835 86.29 97.835 86.29 97.375 86.12 97.375 86.12 97.835 85.45 97.835 85.45 97.375 85.28 97.375 85.28 97.835 84.61 97.835 84.61 97.375 84.44 97.375 84.44 97.835 83.77 97.835 83.77 97.375 83.515 97.375 83.515 97.835 82.255 97.835 82.255 97.11 81.965 97.11 81.965 97.835 81.625 97.835 81.625 97.375 81.37 97.375 81.37 97.835 80.7 97.835 80.7 97.375 80.53 97.375 80.53 97.835 79.86 97.835 79.86 97.375 79.69 97.375 79.69 97.835 79.02 97.835 79.02 97.375 78.85 97.375 78.85 97.835 78.18 97.835 78.18 97.375 77.875 97.375 77.875 97.835 77.605 97.835 77.605 97.375 77.3 97.375 77.3 97.835 76.63 97.835 76.63 97.375 76.46 97.375 76.46 97.835 75.79 97.835 75.79 97.375 75.62 97.375 75.62 97.835 74.95 97.835 74.95 97.375 74.78 97.375 74.78 97.835 74.11 97.835 74.11 97.375 73.855 97.375 73.855 97.835 72.885 97.835 72.885 97.375 72.63 97.375 72.63 97.835 71.96 97.835 71.96 97.375 71.79 97.375 71.79 97.835 71.12 97.835 71.12 97.375 70.95 97.375 70.95 97.835 70.28 97.835 70.28 97.375 70.11 97.375 70.11 97.835 69.44 97.835 69.44 97.375 69.135 97.375 69.135 97.835 67.535 97.835 67.535 97.11 67.245 97.11 67.245 97.835 66.905 97.835 66.905 97.375 66.65 97.375 66.65 97.835 65.98 97.835 65.98 97.375 65.81 97.375 65.81 97.835 65.14 97.835 65.14 97.375 64.97 97.375 64.97 97.835 64.3 97.835 64.3 97.375 64.13 97.375 64.13 97.835 63.46 97.835 63.46 97.375 63.155 97.375 63.155 97.835 62.765 97.835 62.765 97.375 62.51 97.375 62.51 97.835 61.84 97.835 61.84 97.375 61.67 97.375 61.67 97.835 61 97.835 61 97.375 60.83 97.375 60.83 97.835 60.16 97.835 60.16 97.375 59.99 97.375 59.99 97.835 59.32 97.835 59.32 97.375 59.015 97.375 59.015 97.835 57.245 97.835 57.245 97.375 56.99 97.375 56.99 97.835 56.32 97.835 56.32 97.375 56.15 97.375 56.15 97.835 55.48 97.835 55.48 97.375 55.31 97.375 55.31 97.835 54.64 97.835 54.64 97.375 54.47 97.375 54.47 97.835 53.8 97.835 53.8 97.375 53.495 97.375 53.495 97.835 52.355 97.835 52.355 97.11 52.065 97.11 52.065 97.835 50.69 97.835 50.69 97.015 50.46 97.015 50.46 97.835 43.725 97.835 43.725 97.355 43.555 97.355 43.555 97.835 42.885 97.835 42.885 97.355 42.715 97.355 42.715 97.835 42.125 97.835 42.125 97.355 41.795 97.355 41.795 97.835 41.285 97.835 41.285 97.355 40.955 97.355 40.955 97.835 40.445 97.835 40.445 97.035 40.115 97.035 40.115 97.835 37.635 97.835 37.635 97.11 37.345 97.11 37.345 97.835 29.815 97.835 29.815 97.11 29.525 97.11 29.525 97.835 25.76 97.835 25.76 98.005 ; + RECT 91.54 95.115 92 95.285 ; RECT 25.76 95.115 29.44 95.285 ; - RECT 90.16 92.395 92 92.565 ; + RECT 91.08 92.395 92 92.565 ; RECT 25.76 92.395 29.44 92.565 ; RECT 91.08 89.675 92 89.845 ; - RECT 25.76 89.675 27.6 89.845 ; - RECT 88.32 86.955 117.76 87.125 ; - RECT 0 86.955 29.44 87.125 ; - RECT 114.08 84.235 117.76 84.405 ; + RECT 25.76 89.675 29.44 89.845 ; + POLYGON 117.76 87.125 117.76 86.955 112.155 86.955 112.155 86.23 111.865 86.23 111.865 86.955 108.795 86.955 108.795 86.48 108.625 86.48 108.625 86.955 107.945 86.955 107.945 86.48 107.775 86.48 107.775 86.955 107.075 86.955 107.075 86.475 106.905 86.475 106.905 86.955 106.075 86.955 106.075 86.425 105.905 86.425 105.905 86.955 104.05 86.955 104.05 86.455 103.68 86.455 103.68 86.955 101.985 86.955 101.985 86.495 101.735 86.495 101.735 86.955 101.125 86.955 101.125 86.575 100.795 86.575 100.795 86.955 97.435 86.955 97.435 86.23 97.145 86.23 97.145 86.955 96.835 86.955 96.835 86.48 96.665 86.48 96.665 86.955 95.985 86.955 95.985 86.48 95.815 86.48 95.815 86.955 95.115 86.955 95.115 86.475 94.945 86.475 94.945 86.955 94.115 86.955 94.115 86.425 93.945 86.425 93.945 86.955 92.09 86.955 92.09 86.455 91.72 86.455 91.72 86.955 90.025 86.955 90.025 86.495 89.775 86.495 89.775 86.955 89.165 86.955 89.165 86.575 88.835 86.575 88.835 86.955 88.32 86.955 88.32 87.125 ; + POLYGON 33.12 87.125 33.12 86.955 32.895 86.955 32.895 86.48 32.725 86.48 32.725 86.955 32.045 86.955 32.045 86.48 31.875 86.48 31.875 86.955 31.175 86.955 31.175 86.475 31.005 86.475 31.005 86.955 30.175 86.955 30.175 86.425 30.005 86.425 30.005 86.955 28.15 86.955 28.15 86.455 27.78 86.455 27.78 86.955 26.085 86.955 26.085 86.495 25.835 86.495 25.835 86.955 25.225 86.955 25.225 86.575 24.895 86.575 24.895 86.955 22.455 86.955 22.455 86.23 22.165 86.23 22.165 86.955 21.105 86.955 21.105 86.555 20.775 86.555 20.775 86.955 18.815 86.955 18.815 86.42 18.305 86.42 18.305 86.955 17.005 86.955 17.005 86.155 16.675 86.155 16.675 86.955 16.165 86.955 16.165 86.475 15.835 86.475 15.835 86.955 15.325 86.955 15.325 86.475 14.995 86.475 14.995 86.955 14.485 86.955 14.485 86.475 14.155 86.475 14.155 86.955 13.645 86.955 13.645 86.475 13.315 86.475 13.315 86.955 12.805 86.955 12.805 86.475 12.475 86.475 12.475 86.955 11.865 86.955 11.865 86.155 11.535 86.155 11.535 86.955 11.025 86.955 11.025 86.475 10.695 86.475 10.695 86.955 10.185 86.955 10.185 86.475 9.855 86.475 9.855 86.955 9.265 86.955 9.265 86.475 9.095 86.475 9.095 86.955 8.425 86.955 8.425 86.475 8.255 86.475 8.255 86.955 7.735 86.955 7.735 86.23 7.445 86.23 7.445 86.955 0 86.955 0 87.125 ; + RECT 115.92 84.235 117.76 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 116.84 81.515 117.76 81.685 ; + RECT 115.92 81.515 117.76 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 117.3 78.795 117.76 78.965 ; + RECT 115.92 78.795 117.76 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 116.84 76.075 117.76 76.245 ; + RECT 115.92 76.075 117.76 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 116.84 73.355 117.76 73.525 ; + RECT 115.92 73.355 117.76 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 116.84 70.635 117.76 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 117.3 67.915 117.76 68.085 ; + RECT 115.92 70.635 117.76 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 115.92 67.915 117.76 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 116.84 65.195 117.76 65.365 ; + RECT 115.92 65.195 117.76 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 116.84 62.475 117.76 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 116.84 59.755 117.76 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 116.84 57.035 117.76 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 116.84 54.315 117.76 54.485 ; + RECT 115.92 62.475 117.76 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 115.92 59.755 117.76 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 115.92 57.035 117.76 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 115.92 54.315 117.76 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 116.84 51.595 117.76 51.765 ; + RECT 115.92 51.595 117.76 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 116.84 48.875 117.76 49.045 ; + RECT 115.92 48.875 117.76 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 116.84 46.155 117.76 46.325 ; + RECT 115.92 46.155 117.76 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 116.84 43.435 117.76 43.605 ; + RECT 115.92 43.435 117.76 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 114.08 40.715 117.76 40.885 ; + RECT 115.92 40.715 117.76 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 114.08 37.995 117.76 38.165 ; + RECT 115.92 37.995 117.76 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 114.08 35.275 117.76 35.445 ; + RECT 115.92 35.275 117.76 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 114.08 32.555 117.76 32.725 ; + RECT 115.92 32.555 117.76 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 116.84 29.835 117.76 30.005 ; + RECT 115.92 29.835 117.76 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 116.84 27.115 117.76 27.285 ; + RECT 115.92 27.115 117.76 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 116.84 24.395 117.76 24.565 ; + RECT 115.92 24.395 117.76 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 116.84 21.675 117.76 21.845 ; + RECT 115.92 21.675 117.76 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 116.84 18.955 117.76 19.125 ; + RECT 115.92 18.955 117.76 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 116.84 16.235 117.76 16.405 ; + RECT 115.92 16.235 117.76 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 114.08 13.515 117.76 13.685 ; + RECT 115.92 13.515 117.76 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 114.08 10.795 117.76 10.965 ; + RECT 115.92 10.795 117.76 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 114.08 8.075 117.76 8.245 ; + RECT 115.92 8.075 117.76 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 114.08 5.355 117.76 5.525 ; + RECT 115.92 5.355 117.76 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 114.08 2.635 117.76 2.805 ; + RECT 115.92 2.635 117.76 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 117.76 0.085 ; + POLYGON 112.155 0.81 112.155 0.085 117.76 0.085 117.76 -0.085 0 -0.085 0 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 97.145 0.085 97.145 0.81 97.435 0.81 97.435 0.085 111.865 0.085 111.865 0.81 ; POLYGON 91.83 97.75 91.83 86.87 117.59 86.87 117.59 0.17 0.17 0.17 0.17 86.87 25.93 86.87 25.93 97.75 ; LAYER mcon ; - RECT 62.705 87.465 62.875 87.635 ; - RECT 62.49 86.445 62.66 86.615 ; - RECT 61.325 86.445 61.495 86.615 ; - RECT 59.405 86.445 59.575 86.615 ; - RECT 37.405 86.445 37.575 86.615 ; + RECT 54.885 97.325 55.055 97.495 ; + RECT 88.465 87.465 88.635 87.635 ; + RECT 85.705 87.465 85.875 87.635 ; + RECT 76.965 87.465 77.135 87.635 ; + RECT 62.245 87.465 62.415 87.635 ; + RECT 42.41 87.465 42.58 87.635 ; + RECT 77.64 86.445 77.81 86.615 ; + RECT 74.91 86.445 75.08 86.615 ; LAYER via ; RECT 80.885 97.845 81.035 97.995 ; RECT 51.445 97.845 51.595 97.995 ; - RECT 87.095 87.475 87.245 87.625 ; - RECT 71.455 87.475 71.605 87.625 ; - RECT 62.715 87.475 62.865 87.625 ; + RECT 79.275 97.335 79.425 97.485 ; + RECT 70.995 97.335 71.145 97.485 ; + RECT 54.435 97.335 54.585 97.485 ; + RECT 88.935 87.475 89.085 87.625 ; + RECT 82.495 87.475 82.645 87.625 ; + RECT 71.915 87.475 72.065 87.625 ; + RECT 62.255 87.475 62.405 87.625 ; + RECT 43.855 87.475 44.005 87.625 ; RECT 80.885 86.965 81.035 87.115 ; RECT 51.445 86.965 51.595 87.115 ; RECT 10.965 86.965 11.115 87.115 ; - RECT 63.635 86.455 63.785 86.605 ; - RECT 59.035 86.455 59.185 86.605 ; - RECT 50.295 86.455 50.445 86.605 ; - RECT 48.455 86.455 48.605 86.605 ; - RECT 36.955 86.455 37.105 86.605 ; + RECT 115.155 86.455 115.305 86.605 ; + RECT 76.975 86.455 77.125 86.605 ; + RECT 76.055 86.455 76.205 86.605 ; + RECT 15.795 86.455 15.945 86.605 ; + RECT 7.515 86.455 7.665 86.605 ; RECT 80.885 -0.075 81.035 0.075 ; RECT 51.445 -0.075 51.595 0.075 ; RECT 10.965 -0.075 11.115 0.075 ; LAYER via2 ; RECT 80.86 97.82 81.06 98.02 ; RECT 51.42 97.82 51.62 98.02 ; + RECT 72.81 97.48 73.01 97.68 ; + RECT 69.13 97.48 69.33 97.68 ; RECT 10.94 86.94 11.14 87.14 ; - RECT 116.51 28.12 116.71 28.32 ; + RECT 19.45 86.6 19.65 86.8 ; + RECT 116.51 64.16 116.71 64.36 ; + RECT 116.51 58.04 116.71 58.24 ; + RECT 116.51 52.6 116.71 52.8 ; RECT 80.86 -0.1 81.06 0.1 ; RECT 51.42 -0.1 51.62 0.1 ; RECT 10.94 -0.1 11.14 0.1 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__1__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__1__icv_in_design.lef index aaf0267..e215481 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__1__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__1__icv_in_design.lef @@ -2378,23 +2378,45 @@ MACRO sb_1__1_ END VSS OBS LAYER met4 ; - POLYGON 91.69 36.53 91.69 11.385 91.705 11.385 91.705 11.055 91.375 11.055 91.375 11.385 91.39 11.385 91.39 36.53 ; + POLYGON 76.985 108.625 76.985 108.295 76.97 108.295 76.97 62.75 76.67 62.75 76.67 108.295 76.655 108.295 76.655 108.625 ; + POLYGON 73.305 108.625 73.305 108.295 73.29 108.295 73.29 106.27 72.99 106.27 72.99 108.295 72.975 108.295 72.975 108.625 ; + POLYGON 65.025 108.625 65.025 108.295 65.01 108.295 65.01 75.67 64.71 75.67 64.71 108.295 64.695 108.295 64.695 108.625 ; + POLYGON 45.705 108.625 45.705 108.295 45.69 108.295 45.69 107.12 45.39 107.12 45.39 108.295 45.375 108.295 45.375 108.625 ; + POLYGON 43.865 108.625 43.865 108.295 43.85 108.295 43.85 71.59 43.55 71.59 43.55 108.295 43.535 108.295 43.535 108.625 ; + POLYGON 63.39 108.61 63.39 108.31 63.17 108.31 63.17 74.99 62.87 74.99 62.87 108.61 ; + POLYGON 57.87 108.61 57.87 108.31 57.65 108.31 57.65 38.95 57.35 38.95 57.35 108.61 ; + POLYGON 91.69 69.85 91.69 11.385 91.705 11.385 91.705 11.055 91.375 11.055 91.375 11.385 91.39 11.385 91.39 69.85 ; POLYGON 91.6 108.4 91.6 97.52 106.02 97.52 106.02 96.92 107.42 96.92 107.42 97.52 117.36 97.52 117.36 11.28 107.42 11.28 107.42 11.88 106.02 11.88 106.02 11.28 91.6 11.28 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 75.53 0.4 75.53 1.2 74.43 1.2 74.43 0.4 72.77 0.4 72.77 1.2 71.67 1.2 71.67 0.4 70.93 0.4 70.93 1.2 69.83 1.2 69.83 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 53.45 0.4 53.45 1.2 52.35 1.2 52.35 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.29 11.28 9.29 12.08 8.19 12.08 8.19 11.28 7.45 11.28 7.45 12.08 6.35 12.08 6.35 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 26.16 97.52 26.16 108.4 36.1 108.4 36.1 107.8 37.5 107.8 37.5 108.4 50.82 108.4 50.82 107.8 52.22 107.8 52.22 108.4 52.35 108.4 52.35 107.6 53.45 107.6 53.45 108.4 54.19 108.4 54.19 107.6 55.29 107.6 55.29 108.4 56.03 108.4 56.03 107.6 57.13 107.6 57.13 108.4 57.87 108.4 57.87 107.6 58.97 107.6 58.97 108.4 59.71 108.4 59.71 107.6 60.81 107.6 60.81 108.4 61.55 108.4 61.55 107.6 62.65 107.6 62.65 108.4 63.39 108.4 63.39 107.6 64.49 107.6 64.49 108.4 65.54 108.4 65.54 107.8 66.94 107.8 66.94 108.4 67.07 108.4 67.07 107.6 68.17 107.6 68.17 108.4 68.91 108.4 68.91 107.6 70.01 107.6 70.01 108.4 71.67 108.4 71.67 107.6 72.77 107.6 72.77 108.4 73.51 108.4 73.51 107.6 74.61 107.6 74.61 108.4 80.26 108.4 80.26 107.8 81.66 107.8 81.66 108.4 ; LAYER met2 ; RECT 80.82 108.615 81.1 108.985 ; RECT 51.38 108.615 51.66 108.985 ; + POLYGON 73.05 108.645 73.05 108.275 72.98 108.275 72.98 108.245 72.8 108.245 72.8 108.645 ; + POLYGON 61.09 108.645 61.09 108.275 61.02 108.275 61.02 101.76 60.88 101.76 60.88 108.275 60.81 108.275 60.81 108.645 ; + RECT 81.06 107.79 81.32 108.11 ; + POLYGON 91.84 100.54 91.84 77.79 91.7 77.79 91.7 100.4 90.78 100.4 90.78 100.54 ; RECT 10.9 97.735 11.18 98.105 ; + POLYGON 26.13 97.765 26.13 97.395 26.06 97.395 26.06 96.66 25.92 96.66 25.92 97.395 25.85 97.395 25.85 97.765 ; + RECT 12.06 11.23 12.32 11.55 ; RECT 10.9 10.695 11.18 11.065 ; + POLYGON 36.18 6.53 36.18 0.24 36.22 0.24 36.22 0.1 36.04 0.1 36.04 6.53 ; + POLYGON 65.62 4.66 65.62 0.24 65.66 0.24 65.66 0.1 65.48 0.1 65.48 4.66 ; + RECT 61.74 0.69 62 1.01 ; RECT 80.82 -0.185 81.1 0.185 ; RECT 51.38 -0.185 51.66 0.185 ; POLYGON 91.72 108.52 91.72 97.64 117.48 97.64 117.48 11.16 113.28 11.16 113.28 11.645 112.58 11.645 112.58 11.16 111.9 11.16 111.9 11.645 111.2 11.645 111.2 11.16 109.14 11.16 109.14 11.645 108.44 11.645 108.44 11.16 108.22 11.16 108.22 11.645 107.52 11.645 107.52 11.16 107.3 11.16 107.3 11.645 106.6 11.645 106.6 11.16 106.38 11.16 106.38 11.645 105.68 11.645 105.68 11.16 105.46 11.16 105.46 11.645 104.76 11.645 104.76 11.16 104.54 11.16 104.54 11.645 103.84 11.645 103.84 11.16 91.72 11.16 91.72 0.28 89.82 0.28 89.82 0.765 89.12 0.765 89.12 0.28 88.9 0.28 88.9 0.765 88.2 0.765 88.2 0.28 87.98 0.28 87.98 0.765 87.28 0.765 87.28 0.28 86.6 0.28 86.6 0.765 85.9 0.765 85.9 0.28 85.68 0.28 85.68 0.765 84.98 0.765 84.98 0.28 84.76 0.28 84.76 0.765 84.06 0.765 84.06 0.28 83.84 0.28 83.84 0.765 83.14 0.765 83.14 0.28 82.92 0.28 82.92 0.765 82.22 0.765 82.22 0.28 82 0.28 82 0.765 81.3 0.765 81.3 0.28 80.62 0.28 80.62 0.765 79.92 0.765 79.92 0.28 79.7 0.28 79.7 0.765 79 0.765 79 0.28 78.78 0.28 78.78 0.765 78.08 0.765 78.08 0.28 77.4 0.28 77.4 0.765 76.7 0.765 76.7 0.28 76.48 0.28 76.48 0.765 75.78 0.765 75.78 0.28 75.56 0.28 75.56 0.765 74.86 0.765 74.86 0.28 74.64 0.28 74.64 0.765 73.94 0.765 73.94 0.28 73.72 0.28 73.72 0.765 73.02 0.765 73.02 0.28 72.8 0.28 72.8 0.765 72.1 0.765 72.1 0.28 71.42 0.28 71.42 0.765 70.72 0.765 70.72 0.28 70.5 0.28 70.5 0.765 69.8 0.765 69.8 0.28 69.58 0.28 69.58 0.765 68.88 0.765 68.88 0.28 68.2 0.28 68.2 0.765 67.5 0.765 67.5 0.28 67.28 0.28 67.28 0.765 66.58 0.765 66.58 0.28 66.36 0.28 66.36 0.765 65.66 0.765 65.66 0.28 65.44 0.28 65.44 0.765 64.74 0.765 64.74 0.28 64.52 0.28 64.52 0.765 63.82 0.765 63.82 0.28 63.6 0.28 63.6 0.765 62.9 0.765 62.9 0.28 62.68 0.28 62.68 0.765 61.98 0.765 61.98 0.28 61.76 0.28 61.76 0.765 61.06 0.765 61.06 0.28 60.84 0.28 60.84 0.765 60.14 0.765 60.14 0.28 59.92 0.28 59.92 0.765 59.22 0.765 59.22 0.28 59 0.28 59 0.765 58.3 0.765 58.3 0.28 58.08 0.28 58.08 0.765 57.38 0.765 57.38 0.28 57.16 0.28 57.16 0.765 56.46 0.765 56.46 0.28 56.24 0.28 56.24 0.765 55.54 0.765 55.54 0.28 55.32 0.28 55.32 0.765 54.62 0.765 54.62 0.28 54.4 0.28 54.4 0.765 53.7 0.765 53.7 0.28 53.48 0.28 53.48 0.765 52.78 0.765 52.78 0.28 52.56 0.28 52.56 0.765 51.86 0.765 51.86 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 37.84 0.28 37.84 0.765 37.14 0.765 37.14 0.28 36.92 0.28 36.92 0.765 36.22 0.765 36.22 0.28 36 0.28 36 0.765 35.3 0.765 35.3 0.28 35.08 0.28 35.08 0.765 34.38 0.765 34.38 0.28 33.24 0.28 33.24 0.765 32.54 0.765 32.54 0.28 28.64 0.28 28.64 0.765 27.94 0.765 27.94 0.28 26.04 0.28 26.04 11.16 15.76 11.16 15.76 11.645 15.06 11.645 15.06 11.16 14.84 11.16 14.84 11.645 14.14 11.645 14.14 11.16 13.92 11.16 13.92 11.645 13.22 11.645 13.22 11.16 13 11.16 13 11.645 12.3 11.645 12.3 11.16 12.08 11.16 12.08 11.645 11.38 11.645 11.38 11.16 10.7 11.16 10.7 11.645 10 11.645 10 11.16 9.32 11.16 9.32 11.645 8.62 11.645 8.62 11.16 8.4 11.16 8.4 11.645 7.7 11.645 7.7 11.16 7.48 11.16 7.48 11.645 6.78 11.645 6.78 11.16 6.56 11.16 6.56 11.645 5.86 11.645 5.86 11.16 5.64 11.16 5.64 11.645 4.94 11.645 4.94 11.16 4.72 11.16 4.72 11.645 4.02 11.645 4.02 11.16 3.34 11.16 3.34 11.645 2.64 11.645 2.64 11.16 0.28 11.16 0.28 97.64 4.02 97.64 4.02 97.155 4.72 97.155 4.72 97.64 6.78 97.64 6.78 97.155 7.48 97.155 7.48 97.64 8.16 97.64 8.16 97.155 8.86 97.155 8.86 97.64 9.08 97.64 9.08 97.155 9.78 97.155 9.78 97.64 10 97.64 10 97.155 10.7 97.155 10.7 97.64 11.38 97.64 11.38 97.155 12.08 97.155 12.08 97.64 12.3 97.64 12.3 97.155 13 97.155 13 97.64 13.22 97.64 13.22 97.155 13.92 97.155 13.92 97.64 26.04 97.64 26.04 108.52 38.06 108.52 38.06 108.035 38.76 108.035 38.76 108.52 38.98 108.52 38.98 108.035 39.68 108.035 39.68 108.52 50.48 108.52 50.48 108.035 51.18 108.035 51.18 108.52 51.86 108.52 51.86 108.035 52.56 108.035 52.56 108.52 52.78 108.52 52.78 108.035 53.48 108.035 53.48 108.52 54.16 108.52 54.16 108.035 54.86 108.035 54.86 108.52 55.08 108.52 55.08 108.035 55.78 108.035 55.78 108.52 56.46 108.52 56.46 108.035 57.16 108.035 57.16 108.52 57.38 108.52 57.38 108.035 58.08 108.035 58.08 108.52 58.3 108.52 58.3 108.035 59 108.035 59 108.52 59.22 108.52 59.22 108.035 59.92 108.035 59.92 108.52 60.14 108.52 60.14 108.035 60.84 108.035 60.84 108.52 61.06 108.52 61.06 108.035 61.76 108.035 61.76 108.52 61.98 108.52 61.98 108.035 62.68 108.035 62.68 108.52 62.9 108.52 62.9 108.035 63.6 108.035 63.6 108.52 63.82 108.52 63.82 108.035 64.52 108.035 64.52 108.52 64.74 108.52 64.74 108.035 65.44 108.035 65.44 108.52 66.12 108.52 66.12 108.035 66.82 108.035 66.82 108.52 67.04 108.52 67.04 108.035 67.74 108.035 67.74 108.52 67.96 108.52 67.96 108.035 68.66 108.035 68.66 108.52 68.88 108.52 68.88 108.035 69.58 108.035 69.58 108.52 69.8 108.52 69.8 108.035 70.5 108.035 70.5 108.52 70.72 108.52 70.72 108.035 71.42 108.035 71.42 108.52 72.1 108.52 72.1 108.035 72.8 108.035 72.8 108.52 73.48 108.52 73.48 108.035 74.18 108.035 74.18 108.52 74.4 108.52 74.4 108.035 75.1 108.035 75.1 108.52 75.32 108.52 75.32 108.035 76.02 108.035 76.02 108.52 76.24 108.52 76.24 108.035 76.94 108.035 76.94 108.52 77.16 108.52 77.16 108.035 77.86 108.035 77.86 108.52 78.08 108.52 78.08 108.035 78.78 108.035 78.78 108.52 79 108.52 79 108.035 79.7 108.035 79.7 108.52 79.92 108.52 79.92 108.035 80.62 108.035 80.62 108.52 81.3 108.52 81.3 108.035 82 108.035 82 108.52 82.22 108.52 82.22 108.035 82.92 108.035 82.92 108.52 83.14 108.52 83.14 108.035 83.84 108.035 83.84 108.52 84.06 108.52 84.06 108.035 84.76 108.035 84.76 108.52 84.98 108.52 84.98 108.035 85.68 108.035 85.68 108.52 85.9 108.52 85.9 108.035 86.6 108.035 86.6 108.52 86.82 108.52 86.82 108.035 87.52 108.035 87.52 108.52 87.74 108.52 87.74 108.035 88.44 108.035 88.44 108.52 88.66 108.52 88.66 108.035 89.36 108.035 89.36 108.52 ; LAYER met3 ; POLYGON 81.125 108.965 81.125 108.96 81.34 108.96 81.34 108.64 81.125 108.64 81.125 108.635 80.795 108.635 80.795 108.64 80.58 108.64 80.58 108.96 80.795 108.96 80.795 108.965 ; POLYGON 51.685 108.965 51.685 108.96 51.9 108.96 51.9 108.64 51.685 108.64 51.685 108.635 51.355 108.635 51.355 108.64 51.14 108.64 51.14 108.96 51.355 108.96 51.355 108.965 ; + POLYGON 76.755 108.625 76.755 108.62 77.01 108.62 77.01 108.3 76.755 108.3 76.755 108.295 76.425 108.295 76.425 108.3 76.055 108.3 76.055 108.62 76.425 108.62 76.425 108.625 ; + POLYGON 73.075 108.625 73.075 108.62 73.33 108.62 73.33 108.3 73.075 108.3 73.075 108.295 72.745 108.295 72.745 108.31 65.05 108.31 65.05 108.3 64.67 108.3 64.67 108.62 65.05 108.62 65.05 108.61 72.745 108.61 72.745 108.625 ; + POLYGON 61.115 108.625 61.115 108.295 60.785 108.295 60.785 108.31 60.45 108.31 60.45 108.3 60.07 108.3 60.07 108.62 60.45 108.62 60.45 108.61 60.785 108.61 60.785 108.625 ; + POLYGON 45.73 108.62 45.73 108.3 45.35 108.3 45.35 108.31 43.89 108.31 43.89 108.3 43.51 108.3 43.51 108.62 43.89 108.62 43.89 108.61 45.35 108.61 45.35 108.62 ; POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; - POLYGON 26.37 12.05 26.37 11.37 34.88 11.37 34.88 11.07 26.07 11.07 26.07 12.05 ; + POLYGON 26.155 97.745 26.155 97.415 25.825 97.415 25.825 97.43 13.735 97.43 13.735 97.415 13.405 97.415 13.405 97.745 13.735 97.745 13.735 97.73 25.825 97.73 25.825 97.745 ; + POLYGON 55.12 50.81 55.12 50.51 1.2 50.51 1.2 50.53 0.65 50.53 0.65 50.81 ; POLYGON 91.73 11.38 91.73 11.06 91.35 11.06 91.35 11.07 89.32 11.07 89.32 11.37 91.35 11.37 91.35 11.38 ; POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; + POLYGON 53.05 1.17 53.05 0.5 53.09 0.5 53.09 0.18 52.71 0.18 52.71 0.5 52.75 0.5 52.75 1.17 ; POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; POLYGON 91.6 108.4 91.6 97.52 117.36 97.52 117.36 89.97 116.56 89.97 116.56 88.87 117.36 88.87 117.36 88.61 116.56 88.61 116.56 87.51 117.36 87.51 117.36 87.25 116.56 87.25 116.56 86.15 117.36 86.15 117.36 85.89 116.56 85.89 116.56 84.79 117.36 84.79 117.36 84.53 116.56 84.53 116.56 83.43 117.36 83.43 117.36 83.17 116.56 83.17 116.56 82.07 117.36 82.07 117.36 81.81 116.56 81.81 116.56 80.71 117.36 80.71 117.36 80.45 116.56 80.45 116.56 79.35 117.36 79.35 117.36 79.09 116.56 79.09 116.56 77.99 117.36 77.99 117.36 77.73 116.56 77.73 116.56 76.63 117.36 76.63 117.36 76.37 116.56 76.37 116.56 75.27 117.36 75.27 117.36 75.01 116.56 75.01 116.56 73.91 117.36 73.91 117.36 73.65 116.56 73.65 116.56 72.55 117.36 72.55 117.36 72.29 116.56 72.29 116.56 71.19 117.36 71.19 117.36 70.93 116.56 70.93 116.56 69.83 117.36 69.83 117.36 69.57 116.56 69.57 116.56 68.47 117.36 68.47 117.36 68.21 116.56 68.21 116.56 67.11 117.36 67.11 117.36 66.85 116.56 66.85 116.56 65.75 117.36 65.75 117.36 65.49 116.56 65.49 116.56 64.39 117.36 64.39 117.36 64.13 116.56 64.13 116.56 63.03 117.36 63.03 117.36 62.77 116.56 62.77 116.56 61.67 117.36 61.67 117.36 61.41 116.56 61.41 116.56 60.31 117.36 60.31 117.36 60.05 116.56 60.05 116.56 58.95 117.36 58.95 117.36 58.69 116.56 58.69 116.56 57.59 117.36 57.59 117.36 57.33 116.56 57.33 116.56 56.23 117.36 56.23 117.36 55.97 116.56 55.97 116.56 54.87 117.36 54.87 117.36 54.61 116.56 54.61 116.56 53.51 117.36 53.51 117.36 53.25 116.56 53.25 116.56 52.15 117.36 52.15 117.36 51.89 116.56 51.89 116.56 50.79 117.36 50.79 117.36 50.53 116.56 50.53 116.56 49.43 117.36 49.43 117.36 49.17 116.56 49.17 116.56 48.07 117.36 48.07 117.36 47.81 116.56 47.81 116.56 46.71 117.36 46.71 117.36 46.45 116.56 46.45 116.56 45.35 117.36 45.35 117.36 45.09 116.56 45.09 116.56 43.99 117.36 43.99 117.36 43.73 116.56 43.73 116.56 42.63 117.36 42.63 117.36 42.37 116.56 42.37 116.56 41.27 117.36 41.27 117.36 39.65 116.56 39.65 116.56 38.55 117.36 38.55 117.36 38.29 116.56 38.29 116.56 37.19 117.36 37.19 117.36 36.93 116.56 36.93 116.56 35.83 117.36 35.83 117.36 35.57 116.56 35.57 116.56 34.47 117.36 34.47 117.36 34.21 116.56 34.21 116.56 33.11 117.36 33.11 117.36 32.85 116.56 32.85 116.56 31.75 117.36 31.75 117.36 31.49 116.56 31.49 116.56 30.39 117.36 30.39 117.36 30.13 116.56 30.13 116.56 29.03 117.36 29.03 117.36 28.77 116.56 28.77 116.56 27.67 117.36 27.67 117.36 27.41 116.56 27.41 116.56 26.31 117.36 26.31 117.36 26.05 116.56 26.05 116.56 24.95 117.36 24.95 117.36 24.69 116.56 24.69 116.56 23.59 117.36 23.59 117.36 23.33 116.56 23.33 116.56 22.23 117.36 22.23 117.36 16.53 116.56 16.53 116.56 15.43 117.36 15.43 117.36 15.17 116.56 15.17 116.56 14.07 117.36 14.07 117.36 11.28 91.6 11.28 91.6 0.4 26.16 0.4 26.16 11.28 0.4 11.28 0.4 14.07 1.2 14.07 1.2 15.17 0.4 15.17 0.4 15.43 1.2 15.43 1.2 16.53 0.4 16.53 0.4 16.79 1.2 16.79 1.2 17.89 0.4 17.89 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 23.59 1.2 23.59 1.2 24.69 0.4 24.69 0.4 24.95 1.2 24.95 1.2 26.05 0.4 26.05 0.4 26.31 1.2 26.31 1.2 27.41 0.4 27.41 0.4 27.67 1.2 27.67 1.2 28.77 0.4 28.77 0.4 29.03 1.2 29.03 1.2 30.13 0.4 30.13 0.4 30.39 1.2 30.39 1.2 31.49 0.4 31.49 0.4 31.75 1.2 31.75 1.2 32.85 0.4 32.85 0.4 33.11 1.2 33.11 1.2 34.21 0.4 34.21 0.4 34.47 1.2 34.47 1.2 35.57 0.4 35.57 0.4 35.83 1.2 35.83 1.2 36.93 0.4 36.93 0.4 37.19 1.2 37.19 1.2 38.29 0.4 38.29 0.4 38.55 1.2 38.55 1.2 39.65 0.4 39.65 0.4 39.91 1.2 39.91 1.2 41.01 0.4 41.01 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 50.79 1.2 50.79 1.2 51.89 0.4 51.89 0.4 52.15 1.2 52.15 1.2 53.25 0.4 53.25 0.4 53.51 1.2 53.51 1.2 54.61 0.4 54.61 0.4 54.87 1.2 54.87 1.2 55.97 0.4 55.97 0.4 56.23 1.2 56.23 1.2 57.33 0.4 57.33 0.4 57.59 1.2 57.59 1.2 58.69 0.4 58.69 0.4 58.95 1.2 58.95 1.2 60.05 0.4 60.05 0.4 60.31 1.2 60.31 1.2 61.41 0.4 61.41 0.4 61.67 1.2 61.67 1.2 62.77 0.4 62.77 0.4 63.03 1.2 63.03 1.2 64.13 0.4 64.13 0.4 64.39 1.2 64.39 1.2 65.49 0.4 65.49 0.4 66.43 1.2 66.43 1.2 67.53 0.4 67.53 0.4 67.79 1.2 67.79 1.2 68.89 0.4 68.89 0.4 69.15 1.2 69.15 1.2 70.25 0.4 70.25 0.4 70.51 1.2 70.51 1.2 71.61 0.4 71.61 0.4 71.87 1.2 71.87 1.2 72.97 0.4 72.97 0.4 73.23 1.2 73.23 1.2 74.33 0.4 74.33 0.4 74.59 1.2 74.59 1.2 75.69 0.4 75.69 0.4 75.95 1.2 75.95 1.2 77.05 0.4 77.05 0.4 77.31 1.2 77.31 1.2 78.41 0.4 78.41 0.4 78.67 1.2 78.67 1.2 79.77 0.4 79.77 0.4 80.03 1.2 80.03 1.2 81.13 0.4 81.13 0.4 81.39 1.2 81.39 1.2 82.49 0.4 82.49 0.4 83.43 1.2 83.43 1.2 84.53 0.4 84.53 0.4 84.79 1.2 84.79 1.2 85.89 0.4 85.89 0.4 86.15 1.2 86.15 1.2 87.25 0.4 87.25 0.4 87.51 1.2 87.51 1.2 88.61 0.4 88.61 0.4 97.52 26.16 97.52 26.16 108.4 ; @@ -2402,168 +2424,201 @@ MACRO sb_1__1_ POLYGON 90.4 107.2 90.4 96.32 116.16 96.32 116.16 88.2 112.96 88.2 112.96 81.8 116.16 81.8 116.16 67.8 112.96 67.8 112.96 61.4 116.16 61.4 116.16 47.4 112.96 47.4 112.96 41 116.16 41 116.16 27 112.96 27 112.96 20.6 116.16 20.6 116.16 12.48 90.4 12.48 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 27.36 96.32 27.36 107.2 ; LAYER met1 ; RECT 45.68 108.56 46.32 109.04 ; - POLYGON 90.92 108.36 90.92 107.2 90.78 107.2 90.78 108.22 68.38 108.22 68.38 106.86 68.24 106.86 68.24 108.36 ; - POLYGON 39.95 98.56 39.95 98.5 40.545 98.5 40.545 98.545 40.835 98.545 40.835 98.315 40.545 98.315 40.545 98.36 39.95 98.36 39.95 98.3 39.63 98.3 39.63 98.56 ; - POLYGON 75.83 97.54 75.83 97.28 75.51 97.28 75.51 97.34 74.895 97.34 74.895 97.295 74.605 97.295 74.605 97.525 74.895 97.525 74.895 97.48 75.51 97.48 75.51 97.54 ; - POLYGON 71.69 97.54 71.69 97.48 72.305 97.48 72.305 97.525 72.595 97.525 72.595 97.295 72.305 97.295 72.305 97.34 71.69 97.34 71.69 97.28 71.37 97.28 71.37 97.54 ; - POLYGON 62.03 97.54 62.03 97.28 61.71 97.28 61.71 97.34 27.07 97.34 27.07 97.28 26.75 97.28 26.75 97.54 27.07 97.54 27.07 97.48 61.71 97.48 61.71 97.54 ; - POLYGON 26.15 97.54 26.15 97.28 25.83 97.28 25.83 97.34 20.54 97.34 20.54 95.98 20.4 95.98 20.4 97.48 25.83 97.48 25.83 97.54 ; - POLYGON 12.26 12.48 12.26 11.46 30.43 11.46 30.43 11.52 30.52 11.52 30.52 11.8 30.66 11.8 30.66 11.52 30.75 11.52 30.75 11.26 30.43 11.26 30.43 11.32 12.12 11.32 12.12 12.48 ; - POLYGON 53.66 11.8 53.66 11.46 64.47 11.46 64.47 11.52 64.79 11.52 64.79 11.26 64.47 11.26 64.47 11.32 53.52 11.32 53.52 11.8 ; - POLYGON 79.05 11.52 79.05 11.26 78.73 11.26 78.73 11.32 76.275 11.32 76.275 11.275 75.985 11.275 75.985 11.32 75.37 11.32 75.37 11.26 75.05 11.26 75.05 11.52 75.37 11.52 75.37 11.46 75.985 11.46 75.985 11.505 76.275 11.505 76.275 11.46 78.73 11.46 78.73 11.52 ; - POLYGON 52.37 11.52 52.37 11.26 52.05 11.26 52.05 11.32 51.435 11.32 51.435 11.275 51.145 11.275 51.145 11.505 51.435 11.505 51.435 11.46 52.05 11.46 52.05 11.52 ; - RECT 50.67 11.26 50.99 11.52 ; - POLYGON 40.41 11.52 40.41 11.26 40.09 11.26 40.09 11.32 34.875 11.32 34.875 11.275 34.585 11.275 34.585 11.505 34.875 11.505 34.875 11.46 40.09 11.46 40.09 11.52 ; - POLYGON 33.97 11.52 33.97 11.26 33.65 11.26 33.65 11.32 32.575 11.32 32.575 11.275 32.285 11.275 32.285 11.505 32.575 11.505 32.575 11.46 33.65 11.46 33.65 11.52 ; - POLYGON 46.39 10.5 46.39 10.44 47.005 10.44 47.005 10.485 47.295 10.485 47.295 10.255 47.005 10.255 47.005 10.3 46.39 10.3 46.39 10.24 46.07 10.24 46.07 10.3 44.135 10.3 44.135 10.255 44.09 10.255 44.09 10.24 43.77 10.24 43.77 10.5 44.09 10.5 44.09 10.485 44.135 10.485 44.135 10.44 46.07 10.44 46.07 10.5 ; - POLYGON 37.65 10.5 37.65 10.44 37.805 10.44 37.805 10.485 38.095 10.485 38.095 10.255 37.805 10.255 37.805 10.3 37.65 10.3 37.65 10.24 37.33 10.24 37.33 10.5 ; - POLYGON 34.89 10.5 34.89 10.44 35.965 10.44 35.965 10.485 36.255 10.485 36.255 10.255 35.965 10.255 35.965 10.3 34.89 10.3 34.89 10.24 34.57 10.24 34.57 10.5 ; - RECT 33.65 10.24 33.97 10.5 ; - POLYGON 42.235 10.485 42.235 10.255 41.945 10.255 41.945 10.3 39.995 10.3 39.995 10.255 39.705 10.255 39.705 10.485 39.995 10.485 39.995 10.44 41.945 10.44 41.945 10.485 ; + POLYGON 74.91 108.42 74.91 108.16 74.59 108.16 74.59 108.22 67 108.22 67 107.88 66.86 107.88 66.86 108.36 74.59 108.36 74.59 108.42 ; + RECT 33.205 98.315 33.495 98.9 ; + POLYGON 68.93 98.56 68.93 98.3 68.61 98.3 68.61 98.36 65.235 98.36 65.235 98.315 64.945 98.315 64.945 98.545 65.235 98.545 65.235 98.5 68.61 98.5 68.61 98.56 ; + RECT 62.63 98.3 62.95 98.56 ; + POLYGON 49.61 98.56 49.61 98.3 49.29 98.3 49.29 98.36 41.33 98.36 41.33 98.3 41.01 98.3 41.01 98.56 41.33 98.56 41.33 98.5 49.29 98.5 49.29 98.56 ; + POLYGON 78.59 97.54 78.59 97.48 81.26 97.48 81.26 97 81.12 97 81.12 97.34 78.59 97.34 78.59 97.28 78.27 97.28 78.27 97.54 ; + POLYGON 58.81 97.54 58.81 97.28 58.49 97.28 58.49 97.34 57.8 97.34 57.8 96.32 57.66 96.32 57.66 97.48 58.49 97.48 58.49 97.54 ; + RECT 36.41 97.28 36.73 97.54 ; + RECT 34.11 97.28 34.43 97.54 ; + POLYGON 11.89 97.54 11.89 97.48 24.74 97.48 24.74 97 24.6 97 24.6 97.34 11.89 97.34 11.89 97.28 11.57 97.28 11.57 97.54 ; + POLYGON 49.595 97.525 49.595 97.295 49.305 97.295 49.305 97.34 47.755 97.34 47.755 97.295 47.465 97.295 47.465 97.525 47.755 97.525 47.755 97.48 49.305 97.48 49.305 97.525 ; + RECT 82.41 11.26 82.73 11.52 ; + POLYGON 74.91 11.52 74.91 11.46 80.125 11.46 80.125 11.505 80.415 11.505 80.415 11.275 80.125 11.275 80.125 11.32 74.91 11.32 74.91 11.26 74.59 11.26 74.59 11.52 ; + POLYGON 62.49 11.52 62.49 11.26 62.17 11.26 62.17 11.32 59.805 11.32 59.805 11.275 59.515 11.275 59.515 11.505 59.805 11.505 59.805 11.46 62.17 11.46 62.17 11.52 ; + POLYGON 57.43 11.52 57.43 11.46 57.585 11.46 57.585 11.505 57.875 11.505 57.875 11.275 57.585 11.275 57.585 11.32 57.43 11.32 57.43 11.26 57.11 11.26 57.11 11.52 ; + POLYGON 43.17 11.52 43.17 11.505 43.215 11.505 43.215 11.275 43.17 11.275 43.17 11.26 42.85 11.26 42.85 11.32 24.31 11.32 24.31 11.26 23.99 11.26 23.99 11.52 24.31 11.52 24.31 11.46 42.85 11.46 42.85 11.52 ; + POLYGON 21.55 11.52 21.55 11.26 21.23 11.26 21.23 11.32 20.15 11.32 20.15 11.275 19.86 11.275 19.86 11.505 20.15 11.505 20.15 11.46 21.23 11.46 21.23 11.52 ; + RECT 19.39 11.26 19.71 11.52 ; + POLYGON 12.35 11.52 12.35 11.26 12.03 11.26 12.03 11.32 10.955 11.32 10.955 11.275 10.665 11.275 10.665 11.505 10.955 11.505 10.955 11.46 12.03 11.46 12.03 11.52 ; + POLYGON 72.135 11.505 72.135 11.275 71.845 11.275 71.845 11.32 64.835 11.32 64.835 11.275 64.545 11.275 64.545 11.505 64.835 11.505 64.835 11.46 71.845 11.46 71.845 11.505 ; + POLYGON 77.21 10.5 77.21 10.24 76.89 10.24 76.89 10.3 46.85 10.3 46.85 10.24 46.53 10.24 46.53 10.5 46.85 10.5 46.85 10.44 76.89 10.44 76.89 10.5 ; + POLYGON 44.55 10.5 44.55 10.44 46.085 10.44 46.085 10.485 46.375 10.485 46.375 10.255 46.085 10.255 46.085 10.3 44.55 10.3 44.55 10.24 44.23 10.24 44.23 10.5 ; + POLYGON 40.87 10.5 40.87 10.44 41.085 10.44 41.085 10.485 41.375 10.485 41.375 10.255 41.085 10.255 41.085 10.3 40.87 10.3 40.87 10.24 40.55 10.24 40.55 10.5 ; + POLYGON 38.11 10.5 38.11 10.24 37.79 10.24 37.79 10.3 37.635 10.3 37.635 10.255 37.345 10.255 37.345 10.485 37.635 10.485 37.635 10.44 37.79 10.44 37.79 10.5 ; + POLYGON 49.06 1.26 49.06 0.58 60.33 0.58 60.33 0.64 60.65 0.64 60.65 0.38 60.33 0.38 60.33 0.44 48.92 0.44 48.92 1.26 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 108.52 46.32 108.28 91.72 108.28 91.72 106.6 91.24 106.6 91.24 105.56 91.72 105.56 91.72 103.88 91.24 103.88 91.24 102.84 91.72 102.84 91.72 101.16 91.24 101.16 91.24 100.12 91.72 100.12 91.72 98.44 46.32 98.44 46.32 97.4 95.36 97.4 95.36 97.64 96 97.64 96 97.4 117.48 97.4 117.48 95.72 117 95.72 117 94.68 117.48 94.68 117.48 93 117 93 117 91.96 117.48 91.96 117.48 90.28 117 90.28 117 89.24 117.48 89.24 117.48 87.56 117 87.56 117 86.52 117.48 86.52 117.48 84.84 117 84.84 117 83.8 117.48 83.8 117.48 82.12 117 82.12 117 81.08 117.48 81.08 117.48 79.4 117 79.4 117 78.36 117.48 78.36 117.48 76.68 117 76.68 117 75.64 117.48 75.64 117.48 73.96 117 73.96 117 72.92 117.48 72.92 117.48 71.24 117 71.24 117 70.2 117.48 70.2 117.48 68.52 117 68.52 117 67.48 117.48 67.48 117.48 65.8 117 65.8 117 64.76 117.48 64.76 117.48 63.08 117 63.08 117 62.04 117.48 62.04 117.48 60.36 117 60.36 117 59.32 117.48 59.32 117.48 57.64 117 57.64 117 56.6 117.48 56.6 117.48 54.92 117 54.92 117 53.88 117.48 53.88 117.48 52.2 117 52.2 117 51.16 117.48 51.16 117.48 49.48 117 49.48 117 48.44 117.48 48.44 117.48 46.76 117 46.76 117 45.72 117.48 45.72 117.48 44.04 117 44.04 117 43 117.48 43 117.48 41.32 117 41.32 117 40.28 117.48 40.28 117.48 38.6 117 38.6 117 37.56 117.48 37.56 117.48 35.88 117 35.88 117 34.84 117.48 34.84 117.48 33.16 117 33.16 117 32.12 117.48 32.12 117.48 30.44 117 30.44 117 29.4 117.48 29.4 117.48 27.72 117 27.72 117 26.68 117.48 26.68 117.48 25 117 25 117 23.96 117.48 23.96 117.48 22.28 117 22.28 117 21.24 117.48 21.24 117.48 19.56 117 19.56 117 18.52 117.48 18.52 117.48 16.84 117 16.84 117 15.8 117.48 15.8 117.48 14.12 117 14.12 117 13.08 117.48 13.08 117.48 11.4 96 11.4 96 11.16 95.36 11.16 95.36 11.4 46.32 11.4 46.32 10.36 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 45.68 10.36 45.68 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 45.68 97.4 45.68 98.44 26.04 98.44 26.04 100.12 26.52 100.12 26.52 101.16 26.04 101.16 26.04 102.84 26.52 102.84 26.52 103.88 26.04 103.88 26.04 105.56 26.52 105.56 26.52 106.6 26.04 106.6 26.04 108.28 45.68 108.28 45.68 108.52 ; LAYER li1 ; - RECT 25.76 108.715 92 108.885 ; - RECT 88.32 105.995 92 106.165 ; + POLYGON 92 108.885 92 108.715 89.615 108.715 89.615 107.99 89.325 107.99 89.325 108.715 87.385 108.715 87.385 107.915 87.055 107.915 87.055 108.715 86.545 108.715 86.545 108.235 86.215 108.235 86.215 108.715 85.705 108.715 85.705 108.235 85.375 108.235 85.375 108.715 84.865 108.715 84.865 108.235 84.535 108.235 84.535 108.715 84.025 108.715 84.025 108.235 83.695 108.235 83.695 108.715 83.185 108.715 83.185 108.235 82.855 108.235 82.855 108.715 82.255 108.715 82.255 107.99 81.965 107.99 81.965 108.715 73.045 108.715 73.045 107.915 72.715 107.915 72.715 108.715 72.205 108.715 72.205 108.235 71.875 108.235 71.875 108.715 71.365 108.715 71.365 108.235 71.035 108.235 71.035 108.715 70.445 108.715 70.445 108.235 70.275 108.235 70.275 108.715 69.605 108.715 69.605 108.235 69.435 108.235 69.435 108.715 67.535 108.715 67.535 107.99 67.245 107.99 67.245 108.715 66.905 108.715 66.905 108.255 66.65 108.255 66.65 108.715 65.98 108.715 65.98 108.255 65.81 108.255 65.81 108.715 65.14 108.715 65.14 108.255 64.97 108.255 64.97 108.715 64.3 108.715 64.3 108.255 64.13 108.255 64.13 108.715 63.46 108.715 63.46 108.255 63.155 108.255 63.155 108.715 58.405 108.715 58.405 107.915 58.075 107.915 58.075 108.715 57.565 108.715 57.565 108.235 57.235 108.235 57.235 108.715 56.725 108.715 56.725 108.235 56.395 108.235 56.395 108.715 55.885 108.715 55.885 108.235 55.555 108.235 55.555 108.715 55.045 108.715 55.045 108.235 54.715 108.235 54.715 108.715 54.205 108.715 54.205 108.235 53.875 108.235 53.875 108.715 52.355 108.715 52.355 107.99 52.065 107.99 52.065 108.715 51.465 108.715 51.465 108.235 51.135 108.235 51.135 108.715 50.625 108.715 50.625 108.235 50.295 108.235 50.295 108.715 49.785 108.715 49.785 108.235 49.455 108.235 49.455 108.715 48.945 108.715 48.945 108.235 48.615 108.235 48.615 108.715 48.105 108.715 48.105 108.235 47.775 108.235 47.775 108.715 47.265 108.715 47.265 107.915 46.935 107.915 46.935 108.715 45.945 108.715 45.945 108.235 45.615 108.235 45.615 108.715 45.105 108.715 45.105 108.235 44.775 108.235 44.775 108.715 44.265 108.715 44.265 108.235 43.935 108.235 43.935 108.715 43.425 108.715 43.425 108.235 43.095 108.235 43.095 108.715 42.585 108.715 42.585 108.235 42.255 108.235 42.255 108.715 41.745 108.715 41.745 107.915 41.415 107.915 41.415 108.715 37.635 108.715 37.635 107.99 37.345 107.99 37.345 108.715 35.165 108.715 35.165 108.255 34.91 108.255 34.91 108.715 34.24 108.715 34.24 108.255 34.07 108.255 34.07 108.715 33.4 108.715 33.4 108.255 33.23 108.255 33.23 108.715 32.56 108.715 32.56 108.255 32.39 108.255 32.39 108.715 31.72 108.715 31.72 108.255 31.415 108.255 31.415 108.715 29.815 108.715 29.815 107.99 29.525 107.99 29.525 108.715 25.76 108.715 25.76 108.885 ; + RECT 91.54 105.995 92 106.165 ; RECT 25.76 105.995 29.44 106.165 ; RECT 91.54 103.275 92 103.445 ; RECT 25.76 103.275 29.44 103.445 ; - RECT 91.08 100.555 92 100.725 ; + RECT 91.54 100.555 92 100.725 ; RECT 25.76 100.555 29.44 100.725 ; - RECT 89.24 97.835 117.76 98.005 ; - RECT 0 97.835 29.44 98.005 ; - RECT 116.84 95.115 117.76 95.285 ; + POLYGON 117.76 98.005 117.76 97.835 112.155 97.835 112.155 97.11 111.865 97.11 111.865 97.835 97.435 97.835 97.435 97.11 97.145 97.11 97.145 97.835 96.585 97.835 96.585 97.035 96.255 97.035 96.255 97.835 95.745 97.835 95.745 97.355 95.415 97.355 95.415 97.835 94.905 97.835 94.905 97.355 94.575 97.355 94.575 97.835 94.065 97.835 94.065 97.355 93.735 97.355 93.735 97.835 93.225 97.835 93.225 97.355 92.895 97.355 92.895 97.835 92.385 97.835 92.385 97.355 92.055 97.355 92.055 97.835 91.54 97.835 91.54 98.005 ; + POLYGON 29.44 98.005 29.44 97.835 25.855 97.835 25.855 97.3 25.345 97.3 25.345 97.835 23.385 97.835 23.385 97.435 23.055 97.435 23.055 97.835 22.455 97.835 22.455 97.11 22.165 97.11 22.165 97.835 21.255 97.835 21.255 97.3 20.745 97.3 20.745 97.835 18.785 97.835 18.785 97.435 18.455 97.435 18.455 97.835 16.655 97.835 16.655 97.3 16.145 97.3 16.145 97.835 14.185 97.835 14.185 97.435 13.855 97.435 13.855 97.835 7.735 97.835 7.735 97.11 7.445 97.11 7.445 97.835 0 97.835 0 98.005 ; + RECT 115.92 95.115 117.76 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 116.84 92.395 117.76 92.565 ; + RECT 115.92 92.395 117.76 92.565 ; RECT 0 92.395 3.68 92.565 ; - RECT 116.84 89.675 117.76 89.845 ; + RECT 115.92 89.675 117.76 89.845 ; RECT 0 89.675 3.68 89.845 ; - RECT 116.84 86.955 117.76 87.125 ; + RECT 115.92 86.955 117.76 87.125 ; RECT 0 86.955 3.68 87.125 ; - RECT 116.84 84.235 117.76 84.405 ; + RECT 115.92 84.235 117.76 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 116.84 81.515 117.76 81.685 ; + RECT 115.92 81.515 117.76 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 114.08 78.795 117.76 78.965 ; - RECT 0 78.795 1.84 78.965 ; - RECT 114.08 76.075 117.76 76.245 ; + RECT 115.92 78.795 117.76 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 115.92 76.075 117.76 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 116.84 73.355 117.76 73.525 ; + RECT 115.92 73.355 117.76 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 116.84 70.635 117.76 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 116.84 67.915 117.76 68.085 ; - RECT 0 67.915 1.84 68.085 ; + RECT 115.92 70.635 117.76 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 115.92 67.915 117.76 68.085 ; + RECT 0 67.915 3.68 68.085 ; RECT 116.84 65.195 117.76 65.365 ; RECT 0 65.195 3.68 65.365 ; RECT 116.84 62.475 117.76 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 116.84 59.755 117.76 59.925 ; + RECT 115.92 59.755 117.76 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 116.84 57.035 117.76 57.205 ; + RECT 115.92 57.035 117.76 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 114.08 54.315 117.76 54.485 ; + RECT 116.84 54.315 117.76 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 114.08 51.595 117.76 51.765 ; + RECT 116.84 51.595 117.76 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 116.84 48.875 117.76 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 116.84 46.155 117.76 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 116.84 43.435 117.76 43.605 ; + RECT 115.92 48.875 117.76 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 115.92 46.155 117.76 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 115.92 43.435 117.76 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 114.08 40.715 117.76 40.885 ; + RECT 115.92 40.715 117.76 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 114.08 37.995 117.76 38.165 ; + RECT 115.92 37.995 117.76 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 116.84 35.275 117.76 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 114.08 32.555 117.76 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 114.08 29.835 117.76 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 116.84 27.115 117.76 27.285 ; + RECT 115.92 35.275 117.76 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 115.92 32.555 117.76 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 115.92 29.835 117.76 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 115.92 27.115 117.76 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 116.84 24.395 117.76 24.565 ; + RECT 115.92 24.395 117.76 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 114.08 21.675 117.76 21.845 ; + RECT 115.92 21.675 117.76 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 114.08 18.955 117.76 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 117.3 16.235 117.76 16.405 ; + RECT 115.92 18.955 117.76 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 115.92 16.235 117.76 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 117.3 13.515 117.76 13.685 ; + RECT 115.92 13.515 117.76 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 88.78 10.795 117.76 10.965 ; - RECT 0 10.795 29.44 10.965 ; - RECT 90.16 8.075 92 8.245 ; + POLYGON 28.885 11.765 28.885 10.965 29.44 10.965 29.44 10.795 0 10.795 0 10.965 3.315 10.965 3.315 11.765 3.645 11.765 3.645 10.965 4.155 10.965 4.155 11.445 4.485 11.445 4.485 10.965 4.995 10.965 4.995 11.445 5.325 11.445 5.325 10.965 5.915 10.965 5.915 11.445 6.085 11.445 6.085 10.965 6.755 10.965 6.755 11.445 6.925 11.445 6.925 10.965 7.445 10.965 7.445 11.69 7.735 11.69 7.735 10.965 10.025 10.965 10.025 11.5 10.535 11.5 10.535 10.965 12.495 10.965 12.495 11.365 12.825 11.365 12.825 10.965 14.625 10.965 14.625 11.5 15.135 11.5 15.135 10.965 17.095 10.965 17.095 11.365 17.425 11.365 17.425 10.965 18.765 10.965 18.765 11.5 19.275 11.5 19.275 10.965 21.235 10.965 21.235 11.365 21.565 11.365 21.565 10.965 22.165 10.965 22.165 11.69 22.455 11.69 22.455 10.965 25.275 10.965 25.275 11.445 25.445 11.445 25.445 10.965 26.115 10.965 26.115 11.445 26.285 11.445 26.285 10.965 26.875 10.965 26.875 11.445 27.205 11.445 27.205 10.965 27.715 10.965 27.715 11.445 28.045 11.445 28.045 10.965 28.555 10.965 28.555 11.765 ; + POLYGON 112.155 11.69 112.155 10.965 117.76 10.965 117.76 10.795 84.18 10.795 84.18 10.965 84.695 10.965 84.695 11.345 85.025 11.345 85.025 10.965 85.635 10.965 85.635 11.425 85.885 11.425 85.885 10.965 87.58 10.965 87.58 11.465 87.95 11.465 87.95 10.965 89.805 10.965 89.805 11.495 89.975 11.495 89.975 10.965 90.805 10.965 90.805 11.445 90.975 11.445 90.975 10.965 91.675 10.965 91.675 11.44 91.845 11.44 91.845 10.965 92.525 10.965 92.525 11.44 92.695 11.44 92.695 10.965 97.145 10.965 97.145 11.69 97.435 11.69 97.435 10.965 98.505 10.965 98.505 11.345 98.835 11.345 98.835 10.965 103.555 10.965 103.555 11.345 103.885 11.345 103.885 10.965 104.495 10.965 104.495 11.425 104.745 11.425 104.745 10.965 106.44 10.965 106.44 11.465 106.81 11.465 106.81 10.965 108.665 10.965 108.665 11.495 108.835 11.495 108.835 10.965 109.665 10.965 109.665 11.445 109.835 11.445 109.835 10.965 110.535 10.965 110.535 11.44 110.705 11.44 110.705 10.965 111.385 10.965 111.385 11.44 111.555 11.44 111.555 10.965 111.865 10.965 111.865 11.69 ; + RECT 91.54 8.075 92 8.245 ; RECT 25.76 8.075 29.44 8.245 ; RECT 91.54 5.355 92 5.525 ; RECT 25.76 5.355 29.44 5.525 ; - RECT 88.32 2.635 92 2.805 ; + RECT 91.54 2.635 92 2.805 ; RECT 25.76 2.635 29.44 2.805 ; - RECT 25.76 -0.085 92 0.085 ; + POLYGON 84.065 0.885 84.065 0.085 84.575 0.085 84.575 0.565 84.905 0.565 84.905 0.085 85.415 0.085 85.415 0.565 85.745 0.565 85.745 0.085 86.255 0.085 86.255 0.565 86.585 0.565 86.585 0.085 87.095 0.085 87.095 0.565 87.425 0.565 87.425 0.085 87.935 0.085 87.935 0.565 88.265 0.565 88.265 0.085 89.325 0.085 89.325 0.81 89.615 0.81 89.615 0.085 92 0.085 92 -0.085 25.76 -0.085 25.76 0.085 29.525 0.085 29.525 0.81 29.815 0.81 29.815 0.085 30.375 0.085 30.375 0.885 30.705 0.885 30.705 0.085 31.215 0.085 31.215 0.565 31.545 0.565 31.545 0.085 32.055 0.085 32.055 0.565 32.385 0.565 32.385 0.085 32.895 0.085 32.895 0.565 33.225 0.565 33.225 0.085 33.735 0.085 33.735 0.565 34.065 0.565 34.065 0.085 34.575 0.085 34.575 0.565 34.905 0.565 34.905 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 40.995 0.085 40.995 0.565 41.325 0.565 41.325 0.085 41.835 0.085 41.835 0.565 42.165 0.565 42.165 0.085 42.675 0.085 42.675 0.565 43.005 0.565 43.005 0.085 43.515 0.085 43.515 0.565 43.845 0.565 43.845 0.085 44.355 0.085 44.355 0.565 44.685 0.565 44.685 0.085 45.195 0.085 45.195 0.885 45.525 0.885 45.525 0.085 46.435 0.085 46.435 0.565 46.605 0.565 46.605 0.085 47.275 0.085 47.275 0.565 47.445 0.565 47.445 0.085 48.035 0.085 48.035 0.565 48.365 0.565 48.365 0.085 48.875 0.085 48.875 0.565 49.205 0.565 49.205 0.085 49.715 0.085 49.715 0.885 50.045 0.885 50.045 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 52.915 0.085 52.915 0.885 53.245 0.885 53.245 0.085 53.755 0.085 53.755 0.565 54.085 0.565 54.085 0.085 54.595 0.085 54.595 0.565 54.925 0.565 54.925 0.085 55.435 0.085 55.435 0.565 55.765 0.565 55.765 0.085 56.275 0.085 56.275 0.565 56.605 0.565 56.605 0.085 57.115 0.085 57.115 0.565 57.445 0.565 57.445 0.085 63.115 0.085 63.115 0.885 63.445 0.885 63.445 0.085 63.955 0.085 63.955 0.565 64.285 0.565 64.285 0.085 64.795 0.085 64.795 0.565 65.125 0.565 65.125 0.085 65.715 0.085 65.715 0.565 65.885 0.565 65.885 0.085 66.555 0.085 66.555 0.565 66.725 0.565 66.725 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 71.315 0.085 71.315 0.885 71.645 0.885 71.645 0.085 72.155 0.085 72.155 0.565 72.485 0.565 72.485 0.085 72.995 0.085 72.995 0.565 73.325 0.565 73.325 0.085 73.835 0.085 73.835 0.565 74.165 0.565 74.165 0.085 74.675 0.085 74.675 0.565 75.005 0.565 75.005 0.085 75.515 0.085 75.515 0.565 75.845 0.565 75.845 0.085 76.835 0.085 76.835 0.885 77.165 0.885 77.165 0.085 77.675 0.085 77.675 0.565 78.005 0.565 78.005 0.085 78.515 0.085 78.515 0.565 78.845 0.565 78.845 0.085 79.355 0.085 79.355 0.565 79.685 0.565 79.685 0.085 80.195 0.085 80.195 0.565 80.525 0.565 80.525 0.085 81.035 0.085 81.035 0.565 81.365 0.565 81.365 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 83.735 0.085 83.735 0.885 ; POLYGON 91.83 108.63 91.83 97.75 117.59 97.75 117.59 11.05 91.83 11.05 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 25.93 97.75 25.93 108.63 ; LAYER mcon ; - RECT 40.605 98.345 40.775 98.515 ; - RECT 74.665 97.325 74.835 97.495 ; - RECT 72.365 97.325 72.535 97.495 ; - RECT 76.045 11.305 76.215 11.475 ; - RECT 51.205 11.305 51.375 11.475 ; - RECT 50.755 11.305 50.925 11.475 ; - RECT 34.645 11.305 34.815 11.475 ; - RECT 32.345 11.305 32.515 11.475 ; - RECT 47.065 10.285 47.235 10.455 ; - RECT 43.905 10.285 44.075 10.455 ; - RECT 42.005 10.285 42.175 10.455 ; - RECT 39.765 10.285 39.935 10.455 ; - RECT 37.865 10.285 38.035 10.455 ; - RECT 36.025 10.285 36.195 10.455 ; - RECT 33.725 10.285 33.895 10.455 ; + RECT 65.005 98.345 65.175 98.515 ; + RECT 62.705 98.345 62.875 98.515 ; + RECT 33.265 98.345 33.435 98.515 ; + RECT 49.365 97.325 49.535 97.495 ; + RECT 47.525 97.325 47.695 97.495 ; + RECT 36.485 97.325 36.655 97.495 ; + RECT 34.185 97.325 34.355 97.495 ; + RECT 82.485 11.305 82.655 11.475 ; + RECT 80.185 11.305 80.355 11.475 ; + RECT 71.905 11.305 72.075 11.475 ; + RECT 64.605 11.305 64.775 11.475 ; + RECT 59.575 11.305 59.745 11.475 ; + RECT 57.645 11.305 57.815 11.475 ; + RECT 42.985 11.305 43.155 11.475 ; + RECT 19.92 11.305 20.09 11.475 ; + RECT 19.465 11.305 19.635 11.475 ; + RECT 10.725 11.305 10.895 11.475 ; + RECT 41.145 10.285 41.315 10.455 ; + RECT 37.405 10.285 37.575 10.455 ; LAYER via ; RECT 80.885 108.725 81.035 108.875 ; RECT 51.445 108.725 51.595 108.875 ; - RECT 39.715 98.355 39.865 98.505 ; + RECT 74.675 108.215 74.825 108.365 ; + RECT 68.695 98.355 68.845 98.505 ; + RECT 62.715 98.355 62.865 98.505 ; + RECT 49.375 98.355 49.525 98.505 ; + RECT 41.095 98.355 41.245 98.505 ; RECT 80.885 97.845 81.035 97.995 ; RECT 51.445 97.845 51.595 97.995 ; RECT 10.965 97.845 11.115 97.995 ; - RECT 75.595 97.335 75.745 97.485 ; - RECT 71.455 97.335 71.605 97.485 ; - RECT 61.795 97.335 61.945 97.485 ; - RECT 26.835 97.335 26.985 97.485 ; - RECT 25.915 97.335 26.065 97.485 ; - RECT 78.815 11.315 78.965 11.465 ; - RECT 75.135 11.315 75.285 11.465 ; - RECT 64.555 11.315 64.705 11.465 ; - RECT 52.135 11.315 52.285 11.465 ; - RECT 50.755 11.315 50.905 11.465 ; - RECT 40.175 11.315 40.325 11.465 ; - RECT 33.735 11.315 33.885 11.465 ; - RECT 30.515 11.315 30.665 11.465 ; + RECT 78.355 97.335 78.505 97.485 ; + RECT 58.575 97.335 58.725 97.485 ; + RECT 36.495 97.335 36.645 97.485 ; + RECT 34.195 97.335 34.345 97.485 ; + RECT 11.655 97.335 11.805 97.485 ; + RECT 82.495 11.315 82.645 11.465 ; + RECT 74.675 11.315 74.825 11.465 ; + RECT 62.255 11.315 62.405 11.465 ; + RECT 57.195 11.315 57.345 11.465 ; + RECT 42.935 11.315 43.085 11.465 ; + RECT 24.075 11.315 24.225 11.465 ; + RECT 21.315 11.315 21.465 11.465 ; + RECT 19.475 11.315 19.625 11.465 ; + RECT 12.115 11.315 12.265 11.465 ; RECT 80.885 10.805 81.035 10.955 ; RECT 51.445 10.805 51.595 10.955 ; RECT 10.965 10.805 11.115 10.955 ; - RECT 43.855 10.295 44.005 10.445 ; - RECT 37.415 10.295 37.565 10.445 ; - RECT 34.655 10.295 34.805 10.445 ; - RECT 33.735 10.295 33.885 10.445 ; + RECT 76.975 10.295 77.125 10.445 ; + RECT 46.615 10.295 46.765 10.445 ; + RECT 44.315 10.295 44.465 10.445 ; + RECT 40.635 10.295 40.785 10.445 ; + RECT 37.875 10.295 38.025 10.445 ; + RECT 60.415 0.435 60.565 0.585 ; RECT 80.885 -0.075 81.035 0.075 ; RECT 51.445 -0.075 51.595 0.075 ; LAYER via2 ; RECT 80.86 108.7 81.06 108.9 ; RECT 51.42 108.7 51.62 108.9 ; + RECT 76.49 108.36 76.69 108.56 ; + RECT 72.81 108.36 73.01 108.56 ; + RECT 60.85 108.36 61.05 108.56 ; RECT 10.94 97.82 11.14 98.02 ; - RECT 1.05 72.32 1.25 72.52 ; - RECT 116.51 44.44 116.71 44.64 ; + RECT 25.89 97.48 26.09 97.68 ; + RECT 13.47 97.48 13.67 97.68 ; + RECT 116.51 63.48 116.71 63.68 ; + RECT 1.05 34.92 1.25 35.12 ; RECT 10.94 10.78 11.14 10.98 ; RECT 80.86 -0.1 81.06 0.1 ; RECT 51.42 -0.1 51.62 0.1 ; LAYER via3 ; RECT 80.86 108.7 81.06 108.9 ; RECT 51.42 108.7 51.62 108.9 ; + RECT 76.72 108.36 76.92 108.56 ; + RECT 73.04 108.36 73.24 108.56 ; + RECT 64.76 108.36 64.96 108.56 ; + RECT 60.16 108.36 60.36 108.56 ; + RECT 45.44 108.36 45.64 108.56 ; + RECT 43.6 108.36 43.8 108.56 ; + RECT 54.64 107.68 54.84 107.88 ; + RECT 52.8 107.68 53 107.88 ; RECT 10.94 97.82 11.14 98.02 ; RECT 91.44 11.12 91.64 11.32 ; RECT 10.94 10.78 11.14 10.98 ; + RECT 70.28 0.92 70.48 1.12 ; + RECT 52.8 0.24 53 0.44 ; RECT 80.86 -0.1 81.06 0.1 ; RECT 51.42 -0.1 51.62 0.1 ; LAYER OVERLAP ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__2__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__2__icv_in_design.lef index dc65317..29303d3 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__2__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_1__2__icv_in_design.lef @@ -1684,7 +1684,7 @@ MACRO sb_1__2_ POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; - POLYGON 108.94 12.73 108.94 11.07 90.47 11.07 90.47 11.37 108.64 11.37 108.64 12.73 ; + POLYGON 108.955 11.385 108.955 11.055 108.625 11.055 108.625 11.07 90.7 11.07 90.7 11.37 108.625 11.37 108.625 11.385 ; POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; @@ -1693,7 +1693,11 @@ MACRO sb_1__2_ RECT 80.82 97.735 81.1 98.105 ; RECT 51.38 97.735 51.66 98.105 ; RECT 10.9 97.735 11.18 98.105 ; + POLYGON 58.26 21.32 58.26 0.1 58.08 0.1 58.08 0.24 58.12 0.24 58.12 21.32 ; + RECT 5.62 11.23 5.88 11.55 ; RECT 10.9 10.695 11.18 11.065 ; + POLYGON 36.18 5.85 36.18 0.24 36.22 0.24 36.22 0.1 36.04 0.1 36.04 5.85 ; + RECT 40.58 0.69 40.84 1.01 ; RECT 80.82 -0.185 81.1 0.185 ; RECT 51.38 -0.185 51.66 0.185 ; POLYGON 117.48 97.64 117.48 11.16 113.28 11.16 113.28 11.645 112.58 11.645 112.58 11.16 111.9 11.16 111.9 11.645 111.2 11.645 111.2 11.16 109.14 11.16 109.14 11.645 108.44 11.645 108.44 11.16 108.22 11.16 108.22 11.645 107.52 11.645 107.52 11.16 107.3 11.16 107.3 11.645 106.6 11.645 106.6 11.16 106.38 11.16 106.38 11.645 105.68 11.645 105.68 11.16 105.46 11.16 105.46 11.645 104.76 11.645 104.76 11.16 104.54 11.16 104.54 11.645 103.84 11.645 103.84 11.16 91.72 11.16 91.72 0.28 89.82 0.28 89.82 0.765 89.12 0.765 89.12 0.28 86.6 0.28 86.6 0.765 85.9 0.765 85.9 0.28 85.68 0.28 85.68 0.765 84.98 0.765 84.98 0.28 84.76 0.28 84.76 0.765 84.06 0.765 84.06 0.28 83.84 0.28 83.84 0.765 83.14 0.765 83.14 0.28 82.92 0.28 82.92 0.765 82.22 0.765 82.22 0.28 82 0.28 82 0.765 81.3 0.765 81.3 0.28 80.62 0.28 80.62 0.765 79.92 0.765 79.92 0.28 79.7 0.28 79.7 0.765 79 0.765 79 0.28 77.4 0.28 77.4 0.765 76.7 0.765 76.7 0.28 76.48 0.28 76.48 0.765 75.78 0.765 75.78 0.28 75.56 0.28 75.56 0.765 74.86 0.765 74.86 0.28 74.64 0.28 74.64 0.765 73.94 0.765 73.94 0.28 73.72 0.28 73.72 0.765 73.02 0.765 73.02 0.28 68.2 0.28 68.2 0.765 67.5 0.765 67.5 0.28 67.28 0.28 67.28 0.765 66.58 0.765 66.58 0.28 66.36 0.28 66.36 0.765 65.66 0.765 65.66 0.28 65.44 0.28 65.44 0.765 64.74 0.765 64.74 0.28 64.52 0.28 64.52 0.765 63.82 0.765 63.82 0.28 63.6 0.28 63.6 0.765 62.9 0.765 62.9 0.28 62.68 0.28 62.68 0.765 61.98 0.765 61.98 0.28 60.84 0.28 60.84 0.765 60.14 0.765 60.14 0.28 59.92 0.28 59.92 0.765 59.22 0.765 59.22 0.28 59 0.28 59 0.765 58.3 0.765 58.3 0.28 58.08 0.28 58.08 0.765 57.38 0.765 57.38 0.28 56.24 0.28 56.24 0.765 55.54 0.765 55.54 0.28 55.32 0.28 55.32 0.765 54.62 0.765 54.62 0.28 54.4 0.28 54.4 0.765 53.7 0.765 53.7 0.28 53.48 0.28 53.48 0.765 52.78 0.765 52.78 0.28 52.56 0.28 52.56 0.765 51.86 0.765 51.86 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 37.84 0.28 37.84 0.765 37.14 0.765 37.14 0.28 36.92 0.28 36.92 0.765 36.22 0.765 36.22 0.28 36 0.28 36 0.765 35.3 0.765 35.3 0.28 35.08 0.28 35.08 0.765 34.38 0.765 34.38 0.28 34.16 0.28 34.16 0.765 33.46 0.765 33.46 0.28 33.24 0.28 33.24 0.765 32.54 0.765 32.54 0.28 28.64 0.28 28.64 0.765 27.94 0.765 27.94 0.28 26.04 0.28 26.04 11.16 15.76 11.16 15.76 11.645 15.06 11.645 15.06 11.16 14.84 11.16 14.84 11.645 14.14 11.645 14.14 11.16 13.92 11.16 13.92 11.645 13.22 11.645 13.22 11.16 13 11.16 13 11.645 12.3 11.645 12.3 11.16 12.08 11.16 12.08 11.645 11.38 11.645 11.38 11.16 10.7 11.16 10.7 11.645 10 11.645 10 11.16 9.32 11.16 9.32 11.645 8.62 11.645 8.62 11.16 8.4 11.16 8.4 11.645 7.7 11.645 7.7 11.16 7.48 11.16 7.48 11.645 6.78 11.645 6.78 11.16 6.56 11.16 6.56 11.645 5.86 11.645 5.86 11.16 5.64 11.16 5.64 11.645 4.94 11.645 4.94 11.16 4.72 11.16 4.72 11.645 4.02 11.645 4.02 11.16 3.34 11.16 3.34 11.645 2.64 11.645 2.64 11.16 0.28 11.16 0.28 97.64 ; @@ -1703,147 +1707,174 @@ MACRO sb_1__2_ POLYGON 116.16 96.32 116.16 88.2 112.96 88.2 112.96 81.8 116.16 81.8 116.16 67.8 112.96 67.8 112.96 61.4 116.16 61.4 116.16 47.4 112.96 47.4 112.96 41 116.16 41 116.16 27 112.96 27 112.96 20.6 116.16 20.6 116.16 12.48 90.4 12.48 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; LAYER met1 ; RECT 45.68 97.68 96 98.16 ; - POLYGON 14.56 12.48 14.56 11.46 28.59 11.46 28.59 11.52 28.91 11.52 28.91 11.26 28.59 11.26 28.59 11.32 14.42 11.32 14.42 12.48 ; - POLYGON 63.32 11.8 63.32 11.32 62.49 11.32 62.49 11.26 62.17 11.26 62.17 11.52 62.49 11.52 62.49 11.46 63.18 11.46 63.18 11.8 ; - POLYGON 49.06 11.8 49.06 11.52 49.15 11.52 49.15 11.26 48.83 11.26 48.83 11.32 39.49 11.32 39.49 11.26 39.17 11.26 39.17 11.52 39.49 11.52 39.49 11.46 48.83 11.46 48.83 11.52 48.92 11.52 48.92 11.8 ; - POLYGON 91.93 11.52 91.93 11.26 91.61 11.26 91.61 11.32 87.79 11.32 87.79 11.26 87.47 11.26 87.47 11.52 87.79 11.52 87.79 11.46 91.61 11.46 91.61 11.52 ; - POLYGON 85.95 11.52 85.95 11.26 85.63 11.26 85.63 11.32 79.955 11.32 79.955 11.275 79.665 11.275 79.665 11.32 77.67 11.32 77.67 11.26 77.35 11.26 77.35 11.52 77.67 11.52 77.67 11.46 79.665 11.46 79.665 11.505 79.955 11.505 79.955 11.46 85.63 11.46 85.63 11.52 ; - POLYGON 71.69 11.52 71.69 11.26 71.37 11.26 71.37 11.275 71.015 11.275 71.015 11.505 71.37 11.505 71.37 11.52 ; - POLYGON 57.89 11.52 57.89 11.26 57.57 11.26 57.57 11.32 54.655 11.32 54.655 11.275 54.365 11.275 54.365 11.505 54.655 11.505 54.655 11.46 57.57 11.46 57.57 11.52 ; - POLYGON 53.75 11.52 53.75 11.46 53.905 11.46 53.905 11.505 54.195 11.505 54.195 11.275 53.905 11.275 53.905 11.32 53.75 11.32 53.75 11.26 53.43 11.26 53.43 11.52 ; - POLYGON 89.17 10.5 89.17 10.24 88.85 10.24 88.85 10.3 87.315 10.3 87.315 10.255 87.025 10.255 87.025 10.485 87.315 10.485 87.315 10.44 88.85 10.44 88.85 10.5 ; - POLYGON 86.41 10.5 86.41 10.24 86.09 10.24 86.09 10.3 85.015 10.3 85.015 10.255 84.725 10.255 84.725 10.485 85.015 10.485 85.015 10.44 86.09 10.44 86.09 10.5 ; - POLYGON 82.73 10.5 82.73 10.485 82.775 10.485 82.775 10.255 82.73 10.255 82.73 10.24 82.41 10.24 82.41 10.5 ; - POLYGON 76.75 10.5 76.75 10.44 77.365 10.44 77.365 10.485 77.655 10.485 77.655 10.255 77.365 10.255 77.365 10.3 76.75 10.3 76.75 10.24 76.43 10.24 76.43 10.5 ; - POLYGON 69.39 10.5 69.39 10.24 69.07 10.24 69.07 10.3 55.04 10.3 55.04 9.96 54.9 9.96 54.9 10.44 69.07 10.44 69.07 10.5 ; - POLYGON 48.69 10.5 48.69 10.44 49.305 10.44 49.305 10.485 49.595 10.485 49.595 10.255 49.305 10.255 49.305 10.3 48.69 10.3 48.69 10.24 48.37 10.24 48.37 10.5 ; - POLYGON 39.95 10.5 39.95 10.24 39.63 10.24 39.63 10.3 38.555 10.3 38.555 10.255 38.265 10.255 38.265 10.485 38.555 10.485 38.555 10.44 39.63 10.44 39.63 10.5 ; - POLYGON 80.875 10.485 80.875 10.255 80.585 10.255 80.585 10.3 78.085 10.3 78.085 10.255 77.795 10.255 77.795 10.485 78.085 10.485 78.085 10.44 80.585 10.44 80.585 10.485 ; - POLYGON 53.735 10.485 53.735 10.255 53.445 10.255 53.445 10.3 51.535 10.3 51.535 10.255 51.245 10.255 51.245 10.485 51.535 10.485 51.535 10.44 53.445 10.44 53.445 10.485 ; - POLYGON 36.68 10.485 36.68 10.255 36.39 10.255 36.39 10.3 35.72 10.3 35.72 9.96 35.58 9.96 35.58 10.44 36.39 10.44 36.39 10.485 ; + POLYGON 88.62 11.8 88.62 11.505 88.695 11.505 88.695 11.275 88.405 11.275 88.405 11.505 88.48 11.505 88.48 11.8 ; + RECT 98.51 11.26 98.83 11.52 ; + POLYGON 86.87 11.52 86.87 11.26 86.55 11.26 86.55 11.275 86.51 11.275 86.51 11.505 86.55 11.505 86.55 11.52 ; + POLYGON 77.67 11.52 77.67 11.505 78.06 11.505 78.06 11.275 77.67 11.275 77.67 11.26 77.35 11.26 77.35 11.52 ; + POLYGON 73.53 11.52 73.53 11.26 73.21 11.26 73.21 11.32 72.685 11.32 72.685 11.275 72.395 11.275 72.395 11.505 72.685 11.505 72.685 11.46 73.21 11.46 73.21 11.52 ; + POLYGON 68.01 11.52 68.01 11.26 67.69 11.26 67.69 11.32 65.295 11.32 65.295 11.275 65.005 11.275 65.005 11.505 65.295 11.505 65.295 11.46 67.69 11.46 67.69 11.52 ; + POLYGON 55.13 11.52 55.13 11.46 63.105 11.46 63.105 11.505 63.395 11.505 63.395 11.275 63.105 11.275 63.105 11.32 55.13 11.32 55.13 11.26 54.81 11.26 54.81 11.52 ; + POLYGON 45.01 11.52 45.01 11.46 48.845 11.46 48.845 11.505 49.135 11.505 49.135 11.275 48.845 11.275 48.845 11.32 45.01 11.32 45.01 11.26 44.69 11.26 44.69 11.52 ; + POLYGON 39.03 11.52 39.03 11.26 38.71 11.26 38.71 11.32 36.255 11.32 36.255 11.275 35.965 11.275 35.965 11.505 36.255 11.505 36.255 11.46 38.71 11.46 38.71 11.52 ; + POLYGON 35.81 11.52 35.81 11.26 35.49 11.26 35.49 11.32 33.955 11.32 33.955 11.275 33.665 11.275 33.665 11.505 33.955 11.505 33.955 11.46 35.49 11.46 35.49 11.52 ; + POLYGON 32.13 11.52 32.13 11.26 31.81 11.26 31.81 11.32 31.195 11.32 31.195 11.275 30.905 11.275 30.905 11.505 31.195 11.505 31.195 11.46 31.81 11.46 31.81 11.52 ; + POLYGON 28.45 11.52 28.45 11.46 28.605 11.46 28.605 11.505 28.895 11.505 28.895 11.275 28.605 11.275 28.605 11.32 28.45 11.32 28.45 11.26 28.13 11.26 28.13 11.52 ; + POLYGON 27.07 11.52 27.07 11.26 26.75 11.26 26.75 11.32 24.295 11.32 24.295 11.275 24.005 11.275 24.005 11.32 22.01 11.32 22.01 11.26 21.69 11.26 21.69 11.52 22.01 11.52 22.01 11.46 24.005 11.46 24.005 11.505 24.295 11.505 24.295 11.46 26.75 11.46 26.75 11.52 ; + POLYGON 5.91 11.52 5.91 11.46 9.285 11.46 9.285 11.505 9.575 11.505 9.575 11.275 9.285 11.275 9.285 11.32 5.91 11.32 5.91 11.26 5.59 11.26 5.59 11.52 ; + POLYGON 104.795 11.505 104.795 11.275 104.505 11.275 104.505 11.32 101.115 11.32 101.115 11.275 100.825 11.275 100.825 11.505 101.115 11.505 101.115 11.46 104.505 11.46 104.505 11.505 ; + POLYGON 84.57 10.5 84.57 10.24 84.25 10.24 84.25 10.255 84.19 10.255 84.19 10.485 84.25 10.485 84.25 10.5 ; + POLYGON 75.83 10.5 75.83 10.24 75.51 10.24 75.51 10.3 73.975 10.3 73.975 10.255 73.685 10.255 73.685 10.3 70.755 10.3 70.755 10.255 70.465 10.255 70.465 10.485 70.755 10.485 70.755 10.44 73.685 10.44 73.685 10.485 73.975 10.485 73.975 10.44 75.51 10.44 75.51 10.5 ; + POLYGON 64.33 10.5 64.33 10.44 64.485 10.44 64.485 10.485 64.775 10.485 64.775 10.255 64.485 10.255 64.485 10.3 64.33 10.3 64.33 10.24 64.01 10.24 64.01 10.5 ; + POLYGON 48.23 10.5 48.23 10.24 47.91 10.24 47.91 10.3 45.76 10.3 45.76 10.44 47.91 10.44 47.91 10.5 ; + RECT 43.77 10.24 44.09 10.5 ; + POLYGON 39.03 10.5 39.03 10.485 39.075 10.485 39.075 10.255 39.03 10.255 39.03 10.24 38.71 10.24 38.71 10.5 ; + RECT 36.87 10.24 37.19 10.5 ; + RECT 32.27 10.24 32.59 10.5 ; + POLYGON 34.875 10.485 34.875 10.255 34.8 10.255 34.8 9.96 34.66 9.96 34.66 10.255 34.585 10.255 34.585 10.485 ; + POLYGON 56.42 0.92 56.42 0.58 60.33 0.58 60.33 0.64 60.65 0.64 60.65 0.38 60.33 0.38 60.33 0.44 56.28 0.44 56.28 0.92 ; + POLYGON 74.45 0.64 74.45 0.38 74.13 0.38 74.13 0.44 64.685 0.44 64.685 0.395 64.395 0.395 64.395 0.625 64.685 0.625 64.685 0.58 74.13 0.58 74.13 0.64 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 96 97.64 96 97.4 117.48 97.4 117.48 95.72 117 95.72 117 94.68 117.48 94.68 117.48 93 117 93 117 91.96 117.48 91.96 117.48 90.28 117 90.28 117 89.24 117.48 89.24 117.48 87.56 117 87.56 117 86.52 117.48 86.52 117.48 84.84 117 84.84 117 83.8 117.48 83.8 117.48 82.12 117 82.12 117 81.08 117.48 81.08 117.48 79.4 117 79.4 117 78.36 117.48 78.36 117.48 76.68 117 76.68 117 75.64 117.48 75.64 117.48 73.96 117 73.96 117 72.92 117.48 72.92 117.48 71.24 117 71.24 117 70.2 117.48 70.2 117.48 68.52 117 68.52 117 67.48 117.48 67.48 117.48 65.8 117 65.8 117 64.76 117.48 64.76 117.48 63.08 117 63.08 117 62.04 117.48 62.04 117.48 60.36 117 60.36 117 59.32 117.48 59.32 117.48 57.64 117 57.64 117 56.6 117.48 56.6 117.48 54.92 117 54.92 117 53.88 117.48 53.88 117.48 52.2 117 52.2 117 51.16 117.48 51.16 117.48 49.48 117 49.48 117 48.44 117.48 48.44 117.48 46.76 117 46.76 117 45.72 117.48 45.72 117.48 44.04 117 44.04 117 43 117.48 43 117.48 41.32 117 41.32 117 40.28 117.48 40.28 117.48 38.6 117 38.6 117 37.56 117.48 37.56 117.48 35.88 117 35.88 117 34.84 117.48 34.84 117.48 33.16 117 33.16 117 32.12 117.48 32.12 117.48 30.44 117 30.44 117 29.4 117.48 29.4 117.48 27.72 117 27.72 117 26.68 117.48 26.68 117.48 25 117 25 117 23.96 117.48 23.96 117.48 22.28 117 22.28 117 21.24 117.48 21.24 117.48 19.56 117 19.56 117 18.52 117.48 18.52 117.48 16.84 117 16.84 117 15.8 117.48 15.8 117.48 14.12 117 14.12 117 13.08 117.48 13.08 117.48 11.4 96 11.4 96 11.16 95.36 11.16 95.36 11.4 46.32 11.4 46.32 10.36 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 45.68 10.36 45.68 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 45.68 97.4 45.68 97.64 ; LAYER li1 ; - RECT 0 97.835 117.76 98.005 ; - RECT 114.08 95.115 117.76 95.285 ; + POLYGON 117.76 98.005 117.76 97.835 112.155 97.835 112.155 97.11 111.865 97.11 111.865 97.835 97.435 97.835 97.435 97.11 97.145 97.11 97.145 97.835 82.255 97.835 82.255 97.11 81.965 97.11 81.965 97.835 67.535 97.835 67.535 97.11 67.245 97.11 67.245 97.835 52.355 97.835 52.355 97.11 52.065 97.11 52.065 97.835 37.635 97.835 37.635 97.11 37.345 97.11 37.345 97.835 22.455 97.835 22.455 97.11 22.165 97.11 22.165 97.835 7.735 97.835 7.735 97.11 7.445 97.11 7.445 97.835 0 97.835 0 98.005 ; + RECT 115.92 95.115 117.76 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 114.08 92.395 117.76 92.565 ; + RECT 115.92 92.395 117.76 92.565 ; RECT 0 92.395 3.68 92.565 ; RECT 115.92 89.675 117.76 89.845 ; RECT 0 89.675 3.68 89.845 ; RECT 115.92 86.955 117.76 87.125 ; RECT 0 86.955 3.68 87.125 ; - RECT 117.3 84.235 117.76 84.405 ; + RECT 115.92 84.235 117.76 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 116.84 81.515 117.76 81.685 ; + RECT 115.92 81.515 117.76 81.685 ; RECT 0 81.515 3.68 81.685 ; RECT 115.92 78.795 117.76 78.965 ; RECT 0 78.795 3.68 78.965 ; RECT 115.92 76.075 117.76 76.245 ; - RECT 0 76.075 1.84 76.245 ; - RECT 114.08 73.355 117.76 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 114.08 70.635 117.76 70.805 ; + RECT 0 76.075 3.68 76.245 ; + RECT 115.92 73.355 117.76 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 115.92 70.635 117.76 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 116.84 67.915 117.76 68.085 ; + RECT 115.92 67.915 117.76 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 116.84 65.195 117.76 65.365 ; + RECT 115.92 65.195 117.76 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 116.84 62.475 117.76 62.645 ; + RECT 115.92 62.475 117.76 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 116.84 59.755 117.76 59.925 ; + RECT 115.92 59.755 117.76 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 114.08 57.035 117.76 57.205 ; + RECT 115.92 57.035 117.76 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 114.08 54.315 117.76 54.485 ; - RECT 0 54.315 1.84 54.485 ; + RECT 115.92 54.315 117.76 54.485 ; + RECT 0 54.315 3.68 54.485 ; RECT 115.92 51.595 117.76 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 116.84 48.875 117.76 49.045 ; + RECT 115.92 48.875 117.76 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 116.84 46.155 117.76 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 116.84 43.435 117.76 43.605 ; + RECT 115.92 46.155 117.76 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 115.92 43.435 117.76 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 116.84 40.715 117.76 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 114.08 37.995 117.76 38.165 ; + RECT 115.92 40.715 117.76 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 115.92 37.995 117.76 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 114.08 35.275 117.76 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 116.84 32.555 117.76 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 117.3 29.835 117.76 30.005 ; + RECT 115.92 35.275 117.76 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 115.92 32.555 117.76 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 115.92 29.835 117.76 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 116.84 27.115 117.76 27.285 ; + RECT 115.92 27.115 117.76 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 116.84 24.395 117.76 24.565 ; + RECT 115.92 24.395 117.76 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 116.84 21.675 117.76 21.845 ; + RECT 115.92 21.675 117.76 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 116.84 18.955 117.76 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 116.84 16.235 117.76 16.405 ; - RECT 0 16.235 3.68 16.405 ; + RECT 115.92 18.955 117.76 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 115.92 16.235 117.76 16.405 ; + RECT 0 16.235 1.84 16.405 ; RECT 115.92 13.515 117.76 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 90.16 10.795 117.76 10.965 ; - RECT 0 10.795 29.44 10.965 ; - RECT 91.08 8.075 92 8.245 ; + RECT 0 13.515 1.84 13.685 ; + POLYGON 3.645 11.765 3.645 10.965 4.155 10.965 4.155 11.445 4.485 11.445 4.485 10.965 4.995 10.965 4.995 11.445 5.325 11.445 5.325 10.965 5.915 10.965 5.915 11.445 6.085 11.445 6.085 10.965 6.755 10.965 6.755 11.445 6.925 11.445 6.925 10.965 7.445 10.965 7.445 11.69 7.735 11.69 7.735 10.965 9.975 10.965 9.975 11.625 10.315 11.625 10.315 10.965 12.475 10.965 12.475 11.345 12.805 11.345 12.805 10.965 13.415 10.965 13.415 11.425 13.665 11.425 13.665 10.965 15.36 10.965 15.36 11.465 15.73 11.465 15.73 10.965 17.585 10.965 17.585 11.495 17.755 11.495 17.755 10.965 18.585 10.965 18.585 11.445 18.755 11.445 18.755 10.965 19.455 10.965 19.455 11.44 19.625 11.44 19.625 10.965 20.305 10.965 20.305 11.44 20.475 11.44 20.475 10.965 22.165 10.965 22.165 11.69 22.455 11.69 22.455 10.965 23.365 10.965 23.365 11.5 23.875 11.5 23.875 10.965 25.835 10.965 25.835 11.365 26.165 11.365 26.165 10.965 29.44 10.965 29.44 10.795 0 10.795 0 10.965 3.315 10.965 3.315 11.765 ; + POLYGON 112.155 11.69 112.155 10.965 117.76 10.965 117.76 10.795 88.78 10.795 88.78 10.965 93.745 10.965 93.745 11.5 94.255 11.5 94.255 10.965 96.215 10.965 96.215 11.365 96.545 11.365 96.545 10.965 97.145 10.965 97.145 11.69 97.435 11.69 97.435 10.965 98.955 10.965 98.955 11.365 99.285 11.365 99.285 10.965 101.245 10.965 101.245 11.5 101.755 11.5 101.755 10.965 104.935 10.965 104.935 11.365 105.265 11.365 105.265 10.965 107.225 10.965 107.225 11.5 107.735 11.5 107.735 10.965 111.865 10.965 111.865 11.69 ; + RECT 91.54 8.075 92 8.245 ; RECT 25.76 8.075 29.44 8.245 ; - RECT 91.08 5.355 92 5.525 ; + RECT 91.54 5.355 92 5.525 ; RECT 25.76 5.355 29.44 5.525 ; - RECT 88.32 2.635 92 2.805 ; + RECT 91.54 2.635 92 2.805 ; RECT 25.76 2.635 29.44 2.805 ; - RECT 25.76 -0.085 92 0.085 ; + POLYGON 48.39 0.905 48.39 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 52.575 0.085 52.575 0.545 52.88 0.545 52.88 0.085 53.55 0.085 53.55 0.545 53.72 0.545 53.72 0.085 54.39 0.085 54.39 0.545 54.56 0.545 54.56 0.085 55.23 0.085 55.23 0.545 55.4 0.545 55.4 0.085 56.07 0.085 56.07 0.545 56.325 0.545 56.325 0.085 57.015 0.085 57.015 0.565 57.185 0.565 57.185 0.085 57.855 0.085 57.855 0.565 58.025 0.565 58.025 0.085 58.615 0.085 58.615 0.565 58.945 0.565 58.945 0.085 59.455 0.085 59.455 0.565 59.785 0.565 59.785 0.085 60.295 0.085 60.295 0.885 60.625 0.885 60.625 0.085 63.115 0.085 63.115 0.885 63.445 0.885 63.445 0.085 63.955 0.085 63.955 0.565 64.285 0.565 64.285 0.085 64.795 0.085 64.795 0.565 65.125 0.565 65.125 0.085 65.715 0.085 65.715 0.565 65.885 0.565 65.885 0.085 66.555 0.085 66.555 0.565 66.725 0.565 66.725 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 70.815 0.085 70.815 0.565 70.985 0.565 70.985 0.085 71.655 0.085 71.655 0.565 71.825 0.565 71.825 0.085 72.415 0.085 72.415 0.565 72.745 0.565 72.745 0.085 73.255 0.085 73.255 0.565 73.585 0.565 73.585 0.085 74.095 0.085 74.095 0.885 74.425 0.885 74.425 0.085 76.335 0.085 76.335 0.565 76.505 0.565 76.505 0.085 77.175 0.085 77.175 0.565 77.345 0.565 77.345 0.085 77.935 0.085 77.935 0.565 78.265 0.565 78.265 0.085 78.775 0.085 78.775 0.565 79.105 0.565 79.105 0.085 79.615 0.085 79.615 0.885 79.945 0.885 79.945 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 82.775 0.085 82.775 0.565 82.945 0.565 82.945 0.085 83.615 0.085 83.615 0.565 83.785 0.565 83.785 0.085 84.375 0.085 84.375 0.565 84.705 0.565 84.705 0.085 85.215 0.085 85.215 0.565 85.545 0.565 85.545 0.085 86.055 0.085 86.055 0.885 86.385 0.885 86.385 0.085 89.325 0.085 89.325 0.81 89.615 0.81 89.615 0.085 92 0.085 92 -0.085 25.76 -0.085 25.76 0.085 29.525 0.085 29.525 0.81 29.815 0.81 29.815 0.085 30.335 0.085 30.335 0.565 30.505 0.565 30.505 0.085 31.175 0.085 31.175 0.565 31.345 0.565 31.345 0.085 31.935 0.085 31.935 0.565 32.265 0.565 32.265 0.085 32.775 0.085 32.775 0.565 33.105 0.565 33.105 0.085 33.615 0.085 33.615 0.885 33.945 0.885 33.945 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 41.075 0.085 41.075 0.545 41.38 0.545 41.38 0.085 42.05 0.085 42.05 0.545 42.22 0.545 42.22 0.085 42.89 0.085 42.89 0.545 43.06 0.545 43.06 0.085 43.73 0.085 43.73 0.545 43.9 0.545 43.9 0.085 44.57 0.085 44.57 0.545 44.825 0.545 44.825 0.085 48.16 0.085 48.16 0.905 ; POLYGON 117.59 97.75 117.59 11.05 91.83 11.05 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 ; LAYER mcon ; - RECT 79.725 11.305 79.895 11.475 ; - RECT 71.075 11.305 71.245 11.475 ; - RECT 54.425 11.305 54.595 11.475 ; - RECT 53.965 11.305 54.135 11.475 ; - RECT 87.085 10.285 87.255 10.455 ; - RECT 84.785 10.285 84.955 10.455 ; - RECT 82.545 10.285 82.715 10.455 ; - RECT 80.645 10.285 80.815 10.455 ; - RECT 77.855 10.285 78.025 10.455 ; - RECT 77.425 10.285 77.595 10.455 ; - RECT 53.505 10.285 53.675 10.455 ; - RECT 51.305 10.285 51.475 10.455 ; - RECT 49.365 10.285 49.535 10.455 ; - RECT 38.325 10.285 38.495 10.455 ; - RECT 36.45 10.285 36.62 10.455 ; + RECT 104.565 11.305 104.735 11.475 ; + RECT 100.885 11.305 101.055 11.475 ; + RECT 98.585 11.305 98.755 11.475 ; + RECT 88.465 11.305 88.635 11.475 ; + RECT 86.57 11.305 86.74 11.475 ; + RECT 77.83 11.305 78 11.475 ; + RECT 72.455 11.305 72.625 11.475 ; + RECT 65.065 11.305 65.235 11.475 ; + RECT 63.165 11.305 63.335 11.475 ; + RECT 48.905 11.305 49.075 11.475 ; + RECT 36.025 11.305 36.195 11.475 ; + RECT 33.725 11.305 33.895 11.475 ; + RECT 30.965 11.305 31.135 11.475 ; + RECT 28.665 11.305 28.835 11.475 ; + RECT 24.065 11.305 24.235 11.475 ; + RECT 9.345 11.305 9.515 11.475 ; + RECT 84.25 10.285 84.42 10.455 ; + RECT 73.745 10.285 73.915 10.455 ; + RECT 70.525 10.285 70.695 10.455 ; + RECT 64.545 10.285 64.715 10.455 ; + RECT 43.845 10.285 44.015 10.455 ; + RECT 38.845 10.285 39.015 10.455 ; + RECT 36.945 10.285 37.115 10.455 ; + RECT 34.645 10.285 34.815 10.455 ; + RECT 32.345 10.285 32.515 10.455 ; + RECT 64.455 0.425 64.625 0.595 ; LAYER via ; RECT 80.885 97.845 81.035 97.995 ; RECT 51.445 97.845 51.595 97.995 ; RECT 10.965 97.845 11.115 97.995 ; - RECT 91.695 11.315 91.845 11.465 ; - RECT 87.555 11.315 87.705 11.465 ; - RECT 85.715 11.315 85.865 11.465 ; + RECT 98.595 11.315 98.745 11.465 ; + RECT 86.635 11.315 86.785 11.465 ; RECT 77.435 11.315 77.585 11.465 ; - RECT 71.455 11.315 71.605 11.465 ; - RECT 62.255 11.315 62.405 11.465 ; - RECT 57.655 11.315 57.805 11.465 ; - RECT 53.515 11.315 53.665 11.465 ; - RECT 48.915 11.315 49.065 11.465 ; - RECT 39.255 11.315 39.405 11.465 ; - RECT 28.675 11.315 28.825 11.465 ; + RECT 73.295 11.315 73.445 11.465 ; + RECT 67.775 11.315 67.925 11.465 ; + RECT 54.895 11.315 55.045 11.465 ; + RECT 44.775 11.315 44.925 11.465 ; + RECT 38.795 11.315 38.945 11.465 ; + RECT 35.575 11.315 35.725 11.465 ; + RECT 31.895 11.315 32.045 11.465 ; + RECT 28.215 11.315 28.365 11.465 ; + RECT 26.835 11.315 26.985 11.465 ; + RECT 21.775 11.315 21.925 11.465 ; + RECT 5.675 11.315 5.825 11.465 ; RECT 80.885 10.805 81.035 10.955 ; RECT 51.445 10.805 51.595 10.955 ; RECT 10.965 10.805 11.115 10.955 ; - RECT 88.935 10.295 89.085 10.445 ; - RECT 86.175 10.295 86.325 10.445 ; - RECT 82.495 10.295 82.645 10.445 ; - RECT 76.515 10.295 76.665 10.445 ; - RECT 69.155 10.295 69.305 10.445 ; - RECT 48.455 10.295 48.605 10.445 ; - RECT 39.715 10.295 39.865 10.445 ; + RECT 84.335 10.295 84.485 10.445 ; + RECT 75.595 10.295 75.745 10.445 ; + RECT 64.095 10.295 64.245 10.445 ; + RECT 47.995 10.295 48.145 10.445 ; + RECT 43.855 10.295 44.005 10.445 ; + RECT 38.795 10.295 38.945 10.445 ; + RECT 36.955 10.295 37.105 10.445 ; + RECT 32.355 10.295 32.505 10.445 ; + RECT 74.215 0.435 74.365 0.585 ; + RECT 60.415 0.435 60.565 0.585 ; RECT 80.885 -0.075 81.035 0.075 ; RECT 51.445 -0.075 51.595 0.075 ; LAYER via2 ; RECT 80.86 97.82 81.06 98.02 ; RECT 51.42 97.82 51.62 98.02 ; RECT 10.94 97.82 11.14 98.02 ; + RECT 1.05 31.52 1.25 31.72 ; + RECT 108.69 11.12 108.89 11.32 ; RECT 10.94 10.78 11.14 10.98 ; RECT 80.86 -0.1 81.06 0.1 ; RECT 51.42 -0.1 51.62 0.1 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__0__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__0__icv_in_design.lef index fe760eb..97c9c6d 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__0__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__0__icv_in_design.lef @@ -1280,6 +1280,9 @@ MACRO sb_2__0_ LAYER met2 ; RECT 80.82 97.735 81.1 98.105 ; RECT 51.38 97.735 51.66 98.105 ; + POLYGON 65.66 97.82 65.66 97.68 65.62 97.68 65.62 33.76 65.48 33.76 65.48 97.82 ; + POLYGON 44.46 97.82 44.46 88.16 44.32 88.16 44.32 97.68 44.28 97.68 44.28 97.82 ; + RECT 59.44 96.91 59.7 97.23 ; RECT 10.9 86.855 11.18 87.225 ; RECT 80.82 -0.185 81.1 0.185 ; RECT 51.38 -0.185 51.66 0.185 ; @@ -1288,6 +1291,7 @@ MACRO sb_2__0_ LAYER met3 ; POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; + POLYGON 64.335 97.745 64.335 97.415 64.005 97.415 64.005 97.42 63.595 97.42 63.595 97.74 64.005 97.74 64.005 97.745 ; POLYGON 11.205 87.205 11.205 87.2 11.42 87.2 11.42 86.88 11.205 86.88 11.205 86.875 10.875 86.875 10.875 86.88 10.66 86.88 10.66 87.2 10.875 87.2 10.875 87.205 ; POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; @@ -1295,114 +1299,126 @@ MACRO sb_2__0_ POLYGON 91.6 97.52 91.6 0.4 0.4 0.4 0.4 11.35 1.2 11.35 1.2 12.45 0.4 12.45 0.4 12.71 1.2 12.71 1.2 13.81 0.4 13.81 0.4 14.07 1.2 14.07 1.2 15.17 0.4 15.17 0.4 15.43 1.2 15.43 1.2 16.53 0.4 16.53 0.4 16.79 1.2 16.79 1.2 17.89 0.4 17.89 0.4 18.15 1.2 18.15 1.2 19.25 0.4 19.25 0.4 19.51 1.2 19.51 1.2 20.61 0.4 20.61 0.4 20.87 1.2 20.87 1.2 21.97 0.4 21.97 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 23.59 1.2 23.59 1.2 24.69 0.4 24.69 0.4 24.95 1.2 24.95 1.2 26.05 0.4 26.05 0.4 26.31 1.2 26.31 1.2 27.41 0.4 27.41 0.4 27.67 1.2 27.67 1.2 28.77 0.4 28.77 0.4 29.03 1.2 29.03 1.2 30.13 0.4 30.13 0.4 31.07 1.2 31.07 1.2 32.17 0.4 32.17 0.4 32.43 1.2 32.43 1.2 33.53 0.4 33.53 0.4 33.79 1.2 33.79 1.2 34.89 0.4 34.89 0.4 35.15 1.2 35.15 1.2 36.25 0.4 36.25 0.4 36.51 1.2 36.51 1.2 37.61 0.4 37.61 0.4 37.87 1.2 37.87 1.2 38.97 0.4 38.97 0.4 39.23 1.2 39.23 1.2 40.33 0.4 40.33 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 50.79 1.2 50.79 1.2 51.89 0.4 51.89 0.4 52.83 1.2 52.83 1.2 53.93 0.4 53.93 0.4 54.19 1.2 54.19 1.2 55.29 0.4 55.29 0.4 55.55 1.2 55.55 1.2 56.65 0.4 56.65 0.4 56.91 1.2 56.91 1.2 58.01 0.4 58.01 0.4 58.95 1.2 58.95 1.2 60.05 0.4 60.05 0.4 60.31 1.2 60.31 1.2 61.41 0.4 61.41 0.4 61.67 1.2 61.67 1.2 62.77 0.4 62.77 0.4 63.03 1.2 63.03 1.2 64.13 0.4 64.13 0.4 64.39 1.2 64.39 1.2 65.49 0.4 65.49 0.4 66.43 1.2 66.43 1.2 67.53 0.4 67.53 0.4 67.79 1.2 67.79 1.2 68.89 0.4 68.89 0.4 69.15 1.2 69.15 1.2 70.25 0.4 70.25 0.4 70.51 1.2 70.51 1.2 71.61 0.4 71.61 0.4 71.87 1.2 71.87 1.2 72.97 0.4 72.97 0.4 73.23 1.2 73.23 1.2 74.33 0.4 74.33 0.4 74.59 1.2 74.59 1.2 75.69 0.4 75.69 0.4 76.63 1.2 76.63 1.2 77.73 0.4 77.73 0.4 77.99 1.2 77.99 1.2 79.09 0.4 79.09 0.4 79.35 1.2 79.35 1.2 80.45 0.4 80.45 0.4 80.71 1.2 80.71 1.2 81.81 0.4 81.81 0.4 82.75 1.2 82.75 1.2 83.85 0.4 83.85 0.4 86.64 26.16 86.64 26.16 97.52 ; LAYER met1 ; RECT 45.68 97.68 46.32 98.16 ; - RECT 41.01 87.42 41.33 87.68 ; - POLYGON 32.59 86.66 32.59 86.4 32.27 86.4 32.27 86.46 32.115 86.46 32.115 86.415 31.825 86.415 31.825 86.645 32.115 86.645 32.115 86.6 32.27 86.6 32.27 86.66 ; - POLYGON 43.155 86.645 43.155 86.6 43.54 86.6 43.54 86.12 43.4 86.12 43.4 86.46 43.155 86.46 43.155 86.415 42.865 86.415 42.865 86.645 ; + POLYGON 75.83 97.54 75.83 97.48 76.66 97.48 76.66 97 76.52 97 76.52 97.34 75.83 97.34 75.83 97.28 75.51 97.28 75.51 97.54 ; + POLYGON 67.09 97.54 67.09 97.28 66.77 97.28 66.77 97.34 63.78 97.34 63.78 97 63.64 97 63.64 97.48 66.77 97.48 66.77 97.54 ; + POLYGON 39.03 87.68 39.03 87.62 39.59 87.62 39.59 87.665 39.88 87.665 39.88 87.435 39.59 87.435 39.59 87.48 39.03 87.48 39.03 87.42 38.71 87.42 38.71 87.68 ; + POLYGON 40.41 86.66 40.41 86.4 40.09 86.4 40.09 86.46 39.72 86.46 39.72 86.415 39.43 86.415 39.43 86.645 39.72 86.645 39.72 86.6 40.09 86.6 40.09 86.66 ; + POLYGON 34.89 86.66 34.89 86.4 34.57 86.4 34.57 86.46 33.025 86.46 33.025 86.415 32.735 86.415 32.735 86.645 33.025 86.645 33.025 86.6 34.57 86.6 34.57 86.66 ; + POLYGON 25.23 86.66 25.23 86.6 28.55 86.6 28.55 86.645 28.84 86.645 28.84 86.415 28.55 86.415 28.55 86.46 25.23 86.46 25.23 86.4 24.91 86.4 24.91 86.66 ; + POLYGON 20.615 86.645 20.615 86.6 24.68 86.6 24.68 86.12 24.54 86.12 24.54 86.46 20.615 86.46 20.615 86.415 20.325 86.415 20.325 86.645 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 97.64 46.32 97.4 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 91.24 11.4 91.24 10.36 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 45.68 86.52 45.68 87.56 26.04 87.56 26.04 89.24 26.52 89.24 26.52 90.28 26.04 90.28 26.04 91.96 26.52 91.96 26.52 93 26.04 93 26.04 94.68 26.52 94.68 26.52 95.72 26.04 95.72 26.04 97.4 45.68 97.4 45.68 97.64 ; LAYER met4 ; + POLYGON 64.105 97.745 64.105 97.415 64.09 97.415 64.09 39.63 63.79 39.63 63.79 97.415 63.775 97.415 63.775 97.745 ; POLYGON 91.6 97.52 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 86.64 10.34 86.64 10.34 86.04 11.74 86.04 11.74 86.64 26.16 86.64 26.16 97.52 36.1 97.52 36.1 96.92 37.5 96.92 37.5 97.52 50.82 97.52 50.82 96.92 52.22 96.92 52.22 97.52 65.54 97.52 65.54 96.92 66.94 96.92 66.94 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 ; LAYER met5 ; POLYGON 90.4 96.32 90.4 77.32 87.2 77.32 87.2 70.92 90.4 70.92 90.4 56.92 87.2 56.92 87.2 50.52 90.4 50.52 90.4 36.52 87.2 36.52 87.2 30.12 90.4 30.12 90.4 16.12 87.2 16.12 87.2 9.72 90.4 9.72 90.4 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 27.36 85.44 27.36 96.32 ; LAYER li1 ; - RECT 25.76 97.835 92 98.005 ; - RECT 88.32 95.115 92 95.285 ; + POLYGON 92 98.005 92 97.835 89.615 97.835 89.615 97.11 89.325 97.11 89.325 97.835 82.255 97.835 82.255 97.11 81.965 97.11 81.965 97.835 81.625 97.835 81.625 97.375 81.37 97.375 81.37 97.835 80.7 97.835 80.7 97.375 80.53 97.375 80.53 97.835 79.86 97.835 79.86 97.375 79.69 97.375 79.69 97.835 79.02 97.835 79.02 97.375 78.85 97.375 78.85 97.835 78.18 97.835 78.18 97.375 77.875 97.375 77.875 97.835 77.485 97.835 77.485 97.375 77.23 97.375 77.23 97.835 76.56 97.835 76.56 97.375 76.39 97.375 76.39 97.835 75.72 97.835 75.72 97.375 75.55 97.375 75.55 97.835 74.88 97.835 74.88 97.375 74.71 97.375 74.71 97.835 74.04 97.835 74.04 97.375 73.735 97.375 73.735 97.835 67.535 97.835 67.535 97.11 67.245 97.11 67.245 97.835 67.025 97.835 67.025 97.375 66.72 97.375 66.72 97.835 66.05 97.835 66.05 97.375 65.88 97.375 65.88 97.835 65.21 97.835 65.21 97.375 65.04 97.375 65.04 97.835 64.37 97.835 64.37 97.375 64.2 97.375 64.2 97.835 63.53 97.835 63.53 97.375 63.275 97.375 63.275 97.835 60.165 97.835 60.165 97.035 59.835 97.035 59.835 97.835 59.325 97.835 59.325 97.355 58.995 97.355 58.995 97.835 58.485 97.835 58.485 97.355 58.155 97.355 58.155 97.835 57.565 97.835 57.565 97.355 57.395 97.355 57.395 97.835 56.725 97.835 56.725 97.355 56.555 97.355 56.555 97.835 55.475 97.835 55.475 97.37 55.225 97.37 55.225 97.835 54.635 97.835 54.635 97.375 54.465 97.375 54.465 97.835 53.795 97.835 53.795 97.375 53.625 97.375 53.625 97.835 52.835 97.835 52.835 97.375 52.57 97.375 52.57 97.835 52.355 97.835 52.355 97.11 52.065 97.11 52.065 97.835 45.82 97.835 45.82 97.375 45.495 97.375 45.495 97.835 43.705 97.835 43.705 97.375 43.435 97.375 43.435 97.835 42.14 97.835 42.14 97.375 41.815 97.375 41.815 97.835 40.025 97.835 40.025 97.375 39.755 97.375 39.755 97.835 38.575 97.835 38.575 97.455 38.245 97.455 38.245 97.835 37.635 97.835 37.635 97.11 37.345 97.11 37.345 97.835 36.62 97.835 36.62 97.375 36.295 97.375 36.295 97.835 34.505 97.835 34.505 97.375 34.235 97.375 34.235 97.835 32.94 97.835 32.94 97.375 32.615 97.375 32.615 97.835 30.825 97.835 30.825 97.375 30.555 97.375 30.555 97.835 29.815 97.835 29.815 97.11 29.525 97.11 29.525 97.835 25.76 97.835 25.76 98.005 ; + RECT 91.54 95.115 92 95.285 ; RECT 25.76 95.115 29.44 95.285 ; RECT 91.54 92.395 92 92.565 ; - RECT 25.76 92.395 27.6 92.565 ; - RECT 91.08 89.675 92 89.845 ; - RECT 25.76 89.675 27.6 89.845 ; - RECT 88.32 86.955 92 87.125 ; - RECT 0 86.955 27.6 87.125 ; - RECT 88.32 84.235 92 84.405 ; + RECT 25.76 92.395 29.44 92.565 ; + RECT 91.54 89.675 92 89.845 ; + RECT 25.76 89.675 29.44 89.845 ; + RECT 91.54 86.955 92 87.125 ; + POLYGON 29.44 87.125 29.44 86.955 26.545 86.955 26.545 86.495 26.24 86.495 26.24 86.955 25.57 86.955 25.57 86.495 25.4 86.495 25.4 86.955 24.73 86.955 24.73 86.495 24.56 86.495 24.56 86.955 23.89 86.955 23.89 86.495 23.72 86.495 23.72 86.955 23.05 86.955 23.05 86.495 22.795 86.495 22.795 86.955 22.455 86.955 22.455 86.23 22.165 86.23 22.165 86.955 20.185 86.955 20.185 86.555 19.855 86.555 19.855 86.955 17.895 86.955 17.895 86.42 17.385 86.42 17.385 86.955 16.335 86.955 16.335 86.48 16.165 86.48 16.165 86.955 15.485 86.955 15.485 86.48 15.315 86.48 15.315 86.955 14.615 86.955 14.615 86.475 14.445 86.475 14.445 86.955 13.615 86.955 13.615 86.425 13.445 86.425 13.445 86.955 11.59 86.955 11.59 86.455 11.22 86.455 11.22 86.955 9.525 86.955 9.525 86.495 9.275 86.495 9.275 86.955 8.665 86.955 8.665 86.575 8.335 86.575 8.335 86.955 7.735 86.955 7.735 86.23 7.445 86.23 7.445 86.955 0 86.955 0 87.125 ; + RECT 91.54 84.235 92 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 91.08 81.515 92 81.685 ; + RECT 91.54 81.515 92 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 91.08 78.795 92 78.965 ; + RECT 91.54 78.795 92 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 88.32 76.075 92 76.245 ; - RECT 0 76.075 3.68 76.245 ; - RECT 88.32 73.355 92 73.525 ; + RECT 91.54 76.075 92 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 91.54 73.355 92 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 90.16 70.635 92 70.805 ; + RECT 91.54 70.635 92 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 90.16 67.915 92 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 91.08 65.195 92 65.365 ; - RECT 0 65.195 1.84 65.365 ; + RECT 91.54 67.915 92 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 91.54 65.195 92 65.365 ; + RECT 0 65.195 3.68 65.365 ; RECT 91.54 62.475 92 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 91.08 59.755 92 59.925 ; + RECT 91.54 59.755 92 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 91.08 57.035 92 57.205 ; + RECT 91.54 57.035 92 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 88.32 54.315 92 54.485 ; - RECT 0 54.315 3.68 54.485 ; - RECT 88.32 51.595 92 51.765 ; + RECT 90.16 54.315 92 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 90.16 51.595 92 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 91.08 48.875 92 49.045 ; + RECT 91.54 48.875 92 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 91.08 46.155 92 46.325 ; + RECT 91.54 46.155 92 46.325 ; RECT 0 46.155 1.84 46.325 ; RECT 91.54 43.435 92 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 91.08 40.715 92 40.885 ; + RECT 91.54 40.715 92 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 91.08 37.995 92 38.165 ; + RECT 91.54 37.995 92 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 90.16 35.275 92 35.445 ; + RECT 91.54 35.275 92 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 90.16 32.555 92 32.725 ; + RECT 91.54 32.555 92 32.725 ; RECT 0 32.555 3.68 32.725 ; RECT 91.54 29.835 92 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 91.08 27.115 92 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 91.08 24.395 92 24.565 ; + RECT 91.54 27.115 92 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 91.54 24.395 92 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 91.08 21.675 92 21.845 ; + RECT 91.54 21.675 92 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 91.08 18.955 92 19.125 ; + RECT 91.54 18.955 92 19.125 ; RECT 0 18.955 3.68 19.125 ; RECT 91.54 16.235 92 16.405 ; RECT 0 16.235 3.68 16.405 ; RECT 91.54 13.515 92 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 88.32 10.795 92 10.965 ; + RECT 91.54 10.795 92 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 88.32 8.075 92 8.245 ; + RECT 91.54 8.075 92 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 88.32 5.355 92 5.525 ; + RECT 91.54 5.355 92 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 88.32 2.635 92 2.805 ; + RECT 91.54 2.635 92 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 92 0.085 ; + POLYGON 89.615 0.81 89.615 0.085 92 0.085 92 -0.085 0 -0.085 0 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 89.325 0.085 89.325 0.81 ; POLYGON 91.83 97.75 91.83 0.17 0.17 0.17 0.17 86.87 25.93 86.87 25.93 97.75 ; LAYER mcon ; - RECT 41.085 87.465 41.255 87.635 ; - RECT 42.925 86.445 43.095 86.615 ; - RECT 31.885 86.445 32.055 86.615 ; + RECT 39.65 87.465 39.82 87.635 ; + RECT 39.49 86.445 39.66 86.615 ; + RECT 32.795 86.445 32.965 86.615 ; + RECT 28.61 86.445 28.78 86.615 ; + RECT 20.385 86.445 20.555 86.615 ; LAYER via ; RECT 80.885 97.845 81.035 97.995 ; RECT 51.445 97.845 51.595 97.995 ; - RECT 41.095 87.475 41.245 87.625 ; + RECT 75.595 97.335 75.745 97.485 ; + RECT 66.855 97.335 67.005 97.485 ; + RECT 38.795 87.475 38.945 87.625 ; RECT 10.965 86.965 11.115 87.115 ; - RECT 32.355 86.455 32.505 86.605 ; + RECT 40.175 86.455 40.325 86.605 ; + RECT 34.655 86.455 34.805 86.605 ; + RECT 24.995 86.455 25.145 86.605 ; RECT 80.885 -0.075 81.035 0.075 ; RECT 51.445 -0.075 51.595 0.075 ; RECT 10.965 -0.075 11.115 0.075 ; LAYER via2 ; RECT 80.86 97.82 81.06 98.02 ; RECT 51.42 97.82 51.62 98.02 ; + RECT 64.07 97.48 64.27 97.68 ; RECT 10.94 86.94 11.14 87.14 ; RECT 1.05 68.24 1.25 68.44 ; - RECT 1.05 54.64 1.25 54.84 ; RECT 80.86 -0.1 81.06 0.1 ; RECT 51.42 -0.1 51.62 0.1 ; RECT 10.94 -0.1 11.14 0.1 ; LAYER via3 ; RECT 80.86 97.82 81.06 98.02 ; RECT 51.42 97.82 51.62 98.02 ; + RECT 63.84 97.48 64.04 97.68 ; RECT 10.94 86.94 11.14 87.14 ; RECT 80.86 -0.1 81.06 0.1 ; RECT 51.42 -0.1 51.62 0.1 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__1__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__1__icv_in_design.lef index 2232c97..d4cb78e 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__1__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__1__icv_in_design.lef @@ -1672,162 +1672,172 @@ MACRO sb_2__1_ LAYER met2 ; RECT 80.82 108.615 81.1 108.985 ; RECT 51.38 108.615 51.66 108.985 ; + POLYGON 75.28 108.7 75.28 70.14 75.14 70.14 75.14 108.56 75.1 108.56 75.1 108.7 ; + RECT 63.58 107.79 63.84 108.11 ; RECT 10.9 97.735 11.18 98.105 ; + RECT 9.76 96.91 10.02 97.23 ; + POLYGON 20.08 23.02 20.08 11.405 20.15 11.405 20.15 11.035 19.87 11.035 19.87 11.405 19.94 11.405 19.94 23.02 ; RECT 10.9 10.695 11.18 11.065 ; + RECT 64.96 0.69 65.22 1.01 ; RECT 80.82 -0.185 81.1 0.185 ; RECT 51.38 -0.185 51.66 0.185 ; POLYGON 91.72 108.52 91.72 0.28 82.92 0.28 82.92 0.765 82.22 0.765 82.22 0.28 82 0.28 82 0.765 81.3 0.765 81.3 0.28 80.62 0.28 80.62 0.765 79.92 0.765 79.92 0.28 79.7 0.28 79.7 0.765 79 0.765 79 0.28 78.78 0.28 78.78 0.765 78.08 0.765 78.08 0.28 77.86 0.28 77.86 0.765 77.16 0.765 77.16 0.28 76.94 0.28 76.94 0.765 76.24 0.765 76.24 0.28 76.02 0.28 76.02 0.765 75.32 0.765 75.32 0.28 75.1 0.28 75.1 0.765 74.4 0.765 74.4 0.28 74.18 0.28 74.18 0.765 73.48 0.765 73.48 0.28 73.26 0.28 73.26 0.765 72.56 0.765 72.56 0.28 72.34 0.28 72.34 0.765 71.64 0.765 71.64 0.28 71.42 0.28 71.42 0.765 70.72 0.765 70.72 0.28 70.5 0.28 70.5 0.765 69.8 0.765 69.8 0.28 69.58 0.28 69.58 0.765 68.88 0.765 68.88 0.28 68.66 0.28 68.66 0.765 67.96 0.765 67.96 0.28 67.74 0.28 67.74 0.765 67.04 0.765 67.04 0.28 66.82 0.28 66.82 0.765 66.12 0.765 66.12 0.28 65.9 0.28 65.9 0.765 65.2 0.765 65.2 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 62.68 0.28 62.68 0.765 61.98 0.765 61.98 0.28 61.76 0.28 61.76 0.765 61.06 0.765 61.06 0.28 60.38 0.28 60.38 0.765 59.68 0.765 59.68 0.28 59.46 0.28 59.46 0.765 58.76 0.765 58.76 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 55.78 0.28 55.78 0.765 55.08 0.765 55.08 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 53.48 0.28 53.48 0.765 52.78 0.765 52.78 0.28 52.56 0.28 52.56 0.765 51.86 0.765 51.86 0.28 50.72 0.28 50.72 0.765 50.02 0.765 50.02 0.28 49.8 0.28 49.8 0.765 49.1 0.765 49.1 0.28 48.42 0.28 48.42 0.765 47.72 0.765 47.72 0.28 47.5 0.28 47.5 0.765 46.8 0.765 46.8 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 35.54 0.28 35.54 0.765 34.84 0.765 34.84 0.28 34.16 0.28 34.16 0.765 33.46 0.765 33.46 0.28 32.78 0.28 32.78 0.765 32.08 0.765 32.08 0.28 31.86 0.28 31.86 0.765 31.16 0.765 31.16 0.28 26.04 0.28 26.04 11.16 18.98 11.16 18.98 11.645 18.28 11.645 18.28 11.16 15.76 11.16 15.76 11.645 15.06 11.645 15.06 11.16 14.84 11.16 14.84 11.645 14.14 11.645 14.14 11.16 13.92 11.16 13.92 11.645 13.22 11.645 13.22 11.16 13 11.16 13 11.645 12.3 11.645 12.3 11.16 12.08 11.16 12.08 11.645 11.38 11.645 11.38 11.16 10.7 11.16 10.7 11.645 10 11.645 10 11.16 9.32 11.16 9.32 11.645 8.62 11.645 8.62 11.16 8.4 11.16 8.4 11.645 7.7 11.645 7.7 11.16 7.48 11.16 7.48 11.645 6.78 11.645 6.78 11.16 6.56 11.16 6.56 11.645 5.86 11.645 5.86 11.16 5.64 11.16 5.64 11.645 4.94 11.645 4.94 11.16 4.72 11.16 4.72 11.645 4.02 11.645 4.02 11.16 3.34 11.16 3.34 11.645 2.64 11.645 2.64 11.16 0.28 11.16 0.28 97.64 4.02 97.64 4.02 97.155 4.72 97.155 4.72 97.64 6.78 97.64 6.78 97.155 7.48 97.155 7.48 97.64 8.16 97.64 8.16 97.155 8.86 97.155 8.86 97.64 9.08 97.64 9.08 97.155 9.78 97.155 9.78 97.64 10 97.64 10 97.155 10.7 97.155 10.7 97.64 11.38 97.64 11.38 97.155 12.08 97.155 12.08 97.64 12.3 97.64 12.3 97.155 13 97.155 13 97.64 13.22 97.64 13.22 97.155 13.92 97.155 13.92 97.64 26.04 97.64 26.04 108.52 30.24 108.52 30.24 108.035 30.94 108.035 30.94 108.52 31.16 108.52 31.16 108.035 31.86 108.035 31.86 108.52 32.08 108.52 32.08 108.035 32.78 108.035 32.78 108.52 33 108.52 33 108.035 33.7 108.035 33.7 108.52 37.14 108.52 37.14 108.035 37.84 108.035 37.84 108.52 38.06 108.52 38.06 108.035 38.76 108.035 38.76 108.52 43.58 108.52 43.58 108.035 44.28 108.035 44.28 108.52 44.5 108.52 44.5 108.035 45.2 108.035 45.2 108.52 45.42 108.52 45.42 108.035 46.12 108.035 46.12 108.52 46.34 108.52 46.34 108.035 47.04 108.035 47.04 108.52 47.26 108.52 47.26 108.035 47.96 108.035 47.96 108.52 48.18 108.52 48.18 108.035 48.88 108.035 48.88 108.52 49.56 108.52 49.56 108.035 50.26 108.035 50.26 108.52 50.48 108.52 50.48 108.035 51.18 108.035 51.18 108.52 51.86 108.52 51.86 108.035 52.56 108.035 52.56 108.52 52.78 108.52 52.78 108.035 53.48 108.035 53.48 108.52 53.7 108.52 53.7 108.035 54.4 108.035 54.4 108.52 54.62 108.52 54.62 108.035 55.32 108.035 55.32 108.52 55.54 108.52 55.54 108.035 56.24 108.035 56.24 108.52 56.46 108.52 56.46 108.035 57.16 108.035 57.16 108.52 57.84 108.52 57.84 108.035 58.54 108.035 58.54 108.52 58.76 108.52 58.76 108.035 59.46 108.035 59.46 108.52 59.68 108.52 59.68 108.035 60.38 108.035 60.38 108.52 61.06 108.52 61.06 108.035 61.76 108.035 61.76 108.52 61.98 108.52 61.98 108.035 62.68 108.035 62.68 108.52 62.9 108.52 62.9 108.035 63.6 108.035 63.6 108.52 63.82 108.52 63.82 108.035 64.52 108.035 64.52 108.52 64.74 108.52 64.74 108.035 65.44 108.035 65.44 108.52 65.66 108.52 65.66 108.035 66.36 108.035 66.36 108.52 66.58 108.52 66.58 108.035 67.28 108.035 67.28 108.52 67.5 108.52 67.5 108.035 68.2 108.035 68.2 108.52 68.88 108.52 68.88 108.035 69.58 108.035 69.58 108.52 69.8 108.52 69.8 108.035 70.5 108.035 70.5 108.52 70.72 108.52 70.72 108.035 71.42 108.035 71.42 108.52 71.64 108.52 71.64 108.035 72.34 108.035 72.34 108.52 72.56 108.52 72.56 108.035 73.26 108.035 73.26 108.52 73.48 108.52 73.48 108.035 74.18 108.035 74.18 108.52 74.4 108.52 74.4 108.035 75.1 108.035 75.1 108.52 75.32 108.52 75.32 108.035 76.02 108.035 76.02 108.52 76.24 108.52 76.24 108.035 76.94 108.035 76.94 108.52 77.16 108.52 77.16 108.035 77.86 108.035 77.86 108.52 78.08 108.52 78.08 108.035 78.78 108.035 78.78 108.52 79 108.52 79 108.035 79.7 108.035 79.7 108.52 ; LAYER met3 ; POLYGON 81.125 108.965 81.125 108.96 81.34 108.96 81.34 108.64 81.125 108.64 81.125 108.635 80.795 108.635 80.795 108.64 80.58 108.64 80.58 108.96 80.795 108.96 80.795 108.965 ; POLYGON 51.685 108.965 51.685 108.96 51.9 108.96 51.9 108.64 51.685 108.64 51.685 108.635 51.355 108.635 51.355 108.64 51.14 108.64 51.14 108.96 51.355 108.96 51.355 108.965 ; + POLYGON 55.135 108.625 55.135 108.295 54.805 108.295 54.805 108.3 54.395 108.3 54.395 108.62 54.805 108.62 54.805 108.625 ; POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; - POLYGON 17.86 71.89 17.86 71.59 1.2 71.59 1.2 71.61 0.65 71.61 0.65 71.89 ; - POLYGON 11.88 53.53 11.88 53.23 0.65 53.23 0.65 53.51 1.2 53.51 1.2 53.53 ; + POLYGON 8.89 13.41 8.89 11.38 8.93 11.38 8.93 11.06 8.55 11.06 8.55 11.38 8.59 11.38 8.59 13.41 ; + POLYGON 20.175 11.385 20.175 11.055 19.845 11.055 19.845 11.07 15.575 11.07 15.575 11.055 15.245 11.055 15.245 11.385 15.575 11.385 15.575 11.37 19.845 11.37 19.845 11.385 ; POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; POLYGON 91.6 108.4 91.6 0.4 26.16 0.4 26.16 11.28 0.4 11.28 0.4 14.07 1.2 14.07 1.2 15.17 0.4 15.17 0.4 15.43 1.2 15.43 1.2 16.53 0.4 16.53 0.4 16.79 1.2 16.79 1.2 17.89 0.4 17.89 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 23.59 1.2 23.59 1.2 24.69 0.4 24.69 0.4 24.95 1.2 24.95 1.2 26.05 0.4 26.05 0.4 26.31 1.2 26.31 1.2 27.41 0.4 27.41 0.4 27.67 1.2 27.67 1.2 28.77 0.4 28.77 0.4 29.03 1.2 29.03 1.2 30.13 0.4 30.13 0.4 30.39 1.2 30.39 1.2 31.49 0.4 31.49 0.4 31.75 1.2 31.75 1.2 32.85 0.4 32.85 0.4 33.11 1.2 33.11 1.2 34.21 0.4 34.21 0.4 34.47 1.2 34.47 1.2 35.57 0.4 35.57 0.4 35.83 1.2 35.83 1.2 36.93 0.4 36.93 0.4 37.19 1.2 37.19 1.2 38.29 0.4 38.29 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 50.79 1.2 50.79 1.2 51.89 0.4 51.89 0.4 52.15 1.2 52.15 1.2 53.25 0.4 53.25 0.4 53.51 1.2 53.51 1.2 54.61 0.4 54.61 0.4 54.87 1.2 54.87 1.2 55.97 0.4 55.97 0.4 56.23 1.2 56.23 1.2 57.33 0.4 57.33 0.4 57.59 1.2 57.59 1.2 58.69 0.4 58.69 0.4 58.95 1.2 58.95 1.2 60.05 0.4 60.05 0.4 60.31 1.2 60.31 1.2 61.41 0.4 61.41 0.4 61.67 1.2 61.67 1.2 62.77 0.4 62.77 0.4 63.03 1.2 63.03 1.2 64.13 0.4 64.13 0.4 64.39 1.2 64.39 1.2 65.49 0.4 65.49 0.4 66.43 1.2 66.43 1.2 67.53 0.4 67.53 0.4 67.79 1.2 67.79 1.2 68.89 0.4 68.89 0.4 69.15 1.2 69.15 1.2 70.25 0.4 70.25 0.4 70.51 1.2 70.51 1.2 71.61 0.4 71.61 0.4 71.87 1.2 71.87 1.2 72.97 0.4 72.97 0.4 84.79 1.2 84.79 1.2 85.89 0.4 85.89 0.4 86.15 1.2 86.15 1.2 87.25 0.4 87.25 0.4 87.51 1.2 87.51 1.2 88.61 0.4 88.61 0.4 97.52 26.16 97.52 26.16 108.4 ; LAYER met4 ; + POLYGON 54.905 108.625 54.905 108.295 54.89 108.295 54.89 77.03 54.59 77.03 54.59 108.295 54.575 108.295 54.575 108.625 ; POLYGON 91.6 108.4 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.29 11.28 9.29 12.08 8.19 12.08 8.19 11.28 7.45 11.28 7.45 12.08 6.35 12.08 6.35 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 26.16 97.52 26.16 108.4 36.1 108.4 36.1 107.8 37.5 107.8 37.5 108.4 50.82 108.4 50.82 107.8 52.22 107.8 52.22 108.4 65.54 108.4 65.54 107.8 66.94 107.8 66.94 108.4 80.26 108.4 80.26 107.8 81.66 107.8 81.66 108.4 ; LAYER met5 ; POLYGON 90.4 107.2 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 27.36 96.32 27.36 107.2 ; LAYER met1 ; RECT 45.68 108.56 46.32 109.04 ; - POLYGON 42.71 98.56 42.71 98.5 45.9 98.5 45.9 98.36 42.71 98.36 42.71 98.3 42.39 98.3 42.39 98.56 ; - POLYGON 34.43 98.56 34.43 98.5 35.505 98.5 35.505 98.545 35.795 98.545 35.795 98.315 35.505 98.315 35.505 98.36 34.43 98.36 34.43 98.3 34.11 98.3 34.11 98.56 ; - POLYGON 39.95 97.54 39.95 97.28 39.63 97.28 39.63 97.34 36.18 97.34 36.18 96.66 36.04 96.66 36.04 97.48 39.63 97.48 39.63 97.54 ; - POLYGON 29.83 97.54 29.83 97.28 29.51 97.28 29.51 97.34 21 97.34 21 95.98 20.86 95.98 20.86 97.48 29.51 97.48 29.51 97.54 ; - POLYGON 44.995 97.525 44.995 97.295 44.92 97.295 44.92 97 44.78 97 44.78 97.295 44.705 97.295 44.705 97.525 ; - POLYGON 43.08 12.14 43.08 11.505 43.155 11.505 43.155 11.275 42.865 11.275 42.865 11.505 42.94 11.505 42.94 12.14 ; - POLYGON 38.94 11.8 38.94 11.505 39.015 11.505 39.015 11.275 38.725 11.275 38.725 11.505 38.8 11.505 38.8 11.8 ; - POLYGON 40.87 11.52 40.87 11.505 40.915 11.505 40.915 11.275 40.87 11.275 40.87 11.26 40.55 11.26 40.55 11.52 ; - POLYGON 38.11 11.52 38.11 11.26 37.79 11.26 37.79 11.32 36.315 11.32 36.315 11.275 36.025 11.275 36.025 11.505 36.315 11.505 36.315 11.46 37.79 11.46 37.79 11.52 ; - POLYGON 31.21 11.52 31.21 11.505 31.285 11.505 31.285 11.275 31.21 11.275 31.21 11.26 30.89 11.26 30.89 11.52 ; - POLYGON 45.055 11.505 45.055 11.46 46.3 11.46 46.3 11.32 45.055 11.32 45.055 11.275 44.765 11.275 44.765 11.505 ; - POLYGON 32.13 10.5 32.13 10.24 31.81 10.24 31.81 10.3 31.195 10.3 31.195 10.255 30.905 10.255 30.905 10.485 31.195 10.485 31.195 10.44 31.81 10.44 31.81 10.5 ; - RECT 28.59 10.24 28.91 10.5 ; + POLYGON 36.64 98.84 36.64 98.5 40.105 98.5 40.105 98.545 40.395 98.545 40.395 98.315 40.105 98.315 40.105 98.36 36.5 98.36 36.5 98.84 ; + POLYGON 34.34 98.84 34.34 98.545 34.415 98.545 34.415 98.315 34.125 98.315 34.125 98.545 34.2 98.545 34.2 98.84 ; + RECT 42.39 98.3 42.71 98.56 ; + RECT 35.49 98.3 35.81 98.56 ; + RECT 31.81 98.3 32.13 98.56 ; + POLYGON 34.43 97.54 34.43 97.48 59.18 97.48 59.18 97.34 34.43 97.34 34.43 97.28 34.11 97.28 34.11 97.54 ; + POLYGON 28.45 97.54 28.45 97.28 28.13 97.28 28.13 97.34 12.81 97.34 12.81 97.28 12.49 97.28 12.49 97.54 12.81 97.54 12.81 97.48 28.13 97.48 28.13 97.54 ; + POLYGON 9.5 11.8 9.5 11.32 1.31 11.32 1.31 11.26 0.99 11.26 0.99 11.52 1.31 11.52 1.31 11.46 9.36 11.46 9.36 11.8 ; + POLYGON 34.43 11.52 34.43 11.46 44.705 11.46 44.705 11.505 44.995 11.505 44.995 11.275 44.705 11.275 44.705 11.32 34.43 11.32 34.43 11.26 34.11 11.26 34.11 11.52 ; + POLYGON 28.45 11.52 28.45 11.26 28.13 11.26 28.13 11.275 27.775 11.275 27.775 11.505 28.13 11.505 28.13 11.52 ; + POLYGON 76.2 1.26 76.2 0.58 77.35 0.58 77.35 0.64 77.67 0.64 77.67 0.38 77.35 0.38 77.35 0.44 76.06 0.44 76.06 1.26 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 108.52 46.32 108.28 91.72 108.28 91.72 106.6 91.24 106.6 91.24 105.56 91.72 105.56 91.72 103.88 91.24 103.88 91.24 102.84 91.72 102.84 91.72 101.16 91.24 101.16 91.24 100.12 91.72 100.12 91.72 98.44 91.24 98.44 91.24 97.4 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 91.24 11.4 91.24 10.36 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 45.68 10.36 45.68 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 45.68 97.4 45.68 98.44 26.04 98.44 26.04 100.12 26.52 100.12 26.52 101.16 26.04 101.16 26.04 102.84 26.52 102.84 26.52 103.88 26.04 103.88 26.04 105.56 26.52 105.56 26.52 106.6 26.04 106.6 26.04 108.28 45.68 108.28 45.68 108.52 ; LAYER li1 ; - RECT 25.76 108.715 92 108.885 ; - RECT 88.32 105.995 92 106.165 ; + POLYGON 92 108.885 92 108.715 89.615 108.715 89.615 107.99 89.325 107.99 89.325 108.715 82.255 108.715 82.255 107.99 81.965 107.99 81.965 108.715 74.005 108.715 74.005 108.235 73.675 108.235 73.675 108.715 73.165 108.715 73.165 108.235 72.835 108.235 72.835 108.715 72.325 108.715 72.325 108.235 71.995 108.235 71.995 108.715 71.485 108.715 71.485 108.235 71.155 108.235 71.155 108.715 70.645 108.715 70.645 108.235 70.315 108.235 70.315 108.715 69.805 108.715 69.805 107.915 69.475 107.915 69.475 108.715 67.535 108.715 67.535 107.99 67.245 107.99 67.245 108.715 65.725 108.715 65.725 108.235 65.395 108.235 65.395 108.715 64.885 108.715 64.885 108.235 64.555 108.235 64.555 108.715 64.045 108.715 64.045 108.235 63.715 108.235 63.715 108.715 63.205 108.715 63.205 108.235 62.875 108.235 62.875 108.715 62.365 108.715 62.365 108.235 62.035 108.235 62.035 108.715 61.525 108.715 61.525 107.915 61.195 107.915 61.195 108.715 57.485 108.715 57.485 107.915 57.155 107.915 57.155 108.715 56.645 108.715 56.645 108.235 56.315 108.235 56.315 108.715 55.805 108.715 55.805 108.235 55.475 108.235 55.475 108.715 54.965 108.715 54.965 108.235 54.635 108.235 54.635 108.715 54.125 108.715 54.125 108.235 53.795 108.235 53.795 108.715 53.285 108.715 53.285 108.235 52.955 108.235 52.955 108.715 52.355 108.715 52.355 107.99 52.065 107.99 52.065 108.715 48.205 108.715 48.205 107.915 47.875 107.915 47.875 108.715 47.365 108.715 47.365 108.235 47.035 108.235 47.035 108.715 46.525 108.715 46.525 108.235 46.195 108.235 46.195 108.715 45.605 108.715 45.605 108.235 45.435 108.235 45.435 108.715 44.765 108.715 44.765 108.235 44.595 108.235 44.595 108.715 37.635 108.715 37.635 107.99 37.345 107.99 37.345 108.715 36.625 108.715 36.625 108.105 36.455 108.105 36.455 108.715 35.695 108.715 35.695 108.185 35.485 108.185 35.485 108.715 33.67 108.715 33.67 108.215 33.3 108.215 33.3 108.715 31.605 108.715 31.605 108.255 31.355 108.255 31.355 108.715 30.745 108.715 30.745 108.335 30.415 108.335 30.415 108.715 29.815 108.715 29.815 107.99 29.525 107.99 29.525 108.715 25.76 108.715 25.76 108.885 ; + RECT 91.54 105.995 92 106.165 ; RECT 25.76 105.995 29.44 106.165 ; RECT 91.54 103.275 92 103.445 ; - RECT 25.76 103.275 27.6 103.445 ; - RECT 91.08 100.555 92 100.725 ; - RECT 25.76 100.555 27.6 100.725 ; - RECT 91.08 97.835 92 98.005 ; - RECT 0 97.835 27.6 98.005 ; - RECT 90.16 95.115 92 95.285 ; + RECT 25.76 103.275 29.44 103.445 ; + RECT 91.54 100.555 92 100.725 ; + RECT 25.76 100.555 29.44 100.725 ; + RECT 91.54 97.835 92 98.005 ; + POLYGON 29.44 98.005 29.44 97.835 26.155 97.835 26.155 97.455 25.825 97.455 25.825 97.835 22.455 97.835 22.455 97.11 22.165 97.11 22.165 97.835 20.645 97.835 20.645 97.435 20.315 97.435 20.315 97.835 18.355 97.835 18.355 97.3 17.845 97.3 17.845 97.835 14.545 97.835 14.545 97.225 14.375 97.225 14.375 97.835 13.615 97.835 13.615 97.305 13.405 97.305 13.405 97.835 11.59 97.835 11.59 97.335 11.22 97.335 11.22 97.835 9.525 97.835 9.525 97.375 9.275 97.375 9.275 97.835 8.665 97.835 8.665 97.455 8.335 97.455 8.335 97.835 7.735 97.835 7.735 97.11 7.445 97.11 7.445 97.835 0 97.835 0 98.005 ; + RECT 91.54 95.115 92 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 90.16 92.395 92 92.565 ; - RECT 0 92.395 3.68 92.565 ; - RECT 88.32 89.675 92 89.845 ; - RECT 0 89.675 3.68 89.845 ; - RECT 88.32 86.955 92 87.125 ; + RECT 91.54 92.395 92 92.565 ; + RECT 0 92.395 1.84 92.565 ; + RECT 91.54 89.675 92 89.845 ; + RECT 0 89.675 1.84 89.845 ; + RECT 91.54 86.955 92 87.125 ; RECT 0 86.955 1.84 87.125 ; RECT 91.54 84.235 92 84.405 ; - RECT 0 84.235 3.68 84.405 ; + RECT 0 84.235 1.84 84.405 ; RECT 91.54 81.515 92 81.685 ; - RECT 0 81.515 3.68 81.685 ; - RECT 91.08 78.795 92 78.965 ; - RECT 0 78.795 3.68 78.965 ; - RECT 91.08 76.075 92 76.245 ; + RECT 0 81.515 1.84 81.685 ; + RECT 91.54 78.795 92 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 91.54 76.075 92 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 91.08 73.355 92 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 91.08 70.635 92 70.805 ; + RECT 91.54 73.355 92 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 91.54 70.635 92 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 91.08 67.915 92 68.085 ; + RECT 91.54 67.915 92 68.085 ; RECT 0 67.915 3.68 68.085 ; RECT 91.08 65.195 92 65.365 ; - RECT 0 65.195 3.68 65.365 ; + RECT 0 65.195 1.84 65.365 ; RECT 91.08 62.475 92 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 91.08 59.755 92 59.925 ; + RECT 0 62.475 1.84 62.645 ; + RECT 91.54 59.755 92 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 90.16 57.035 92 57.205 ; + RECT 91.54 57.035 92 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 90.16 54.315 92 54.485 ; - RECT 0 54.315 3.68 54.485 ; - RECT 91.08 51.595 92 51.765 ; - RECT 0 51.595 3.68 51.765 ; - RECT 91.08 48.875 92 49.045 ; + RECT 91.54 54.315 92 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 91.54 51.595 92 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 91.54 48.875 92 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 91.08 46.155 92 46.325 ; + RECT 91.54 46.155 92 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 88.32 43.435 92 43.605 ; + RECT 90.16 43.435 92 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 88.32 40.715 92 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 91.08 37.995 92 38.165 ; + RECT 90.16 40.715 92 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 91.54 37.995 92 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 91.08 35.275 92 35.445 ; + RECT 91.54 35.275 92 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 91.08 32.555 92 32.725 ; + RECT 91.54 32.555 92 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 91.08 29.835 92 30.005 ; + RECT 91.54 29.835 92 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 91.08 27.115 92 27.285 ; + RECT 91.54 27.115 92 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 91.08 24.395 92 24.565 ; + RECT 91.54 24.395 92 24.565 ; RECT 0 24.395 1.84 24.565 ; RECT 91.54 21.675 92 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 91.08 18.955 92 19.125 ; + RECT 91.54 18.955 92 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 91.08 16.235 92 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 91.08 13.515 92 13.685 ; + RECT 91.54 16.235 92 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 91.54 13.515 92 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 91.08 10.795 92 10.965 ; - RECT 0 10.795 27.6 10.965 ; - RECT 91.08 8.075 92 8.245 ; + POLYGON 5.66 11.785 5.66 10.965 7.445 10.965 7.445 11.69 7.735 11.69 7.735 10.965 8.835 10.965 8.835 11.765 9.165 11.765 9.165 10.965 9.675 10.965 9.675 11.445 10.005 11.445 10.005 10.965 10.515 10.965 10.515 11.445 10.845 11.445 10.845 10.965 11.435 10.965 11.435 11.445 11.605 11.445 11.605 10.965 12.275 10.965 12.275 11.445 12.445 11.445 12.445 10.965 15.235 10.965 15.235 11.345 15.565 11.345 15.565 10.965 16.175 10.965 16.175 11.425 16.425 11.425 16.425 10.965 18.12 10.965 18.12 11.465 18.49 11.465 18.49 10.965 20.305 10.965 20.305 11.495 20.515 11.495 20.515 10.965 21.275 10.965 21.275 11.575 21.445 11.575 21.445 10.965 22.165 10.965 22.165 11.69 22.455 11.69 22.455 10.965 25.735 10.965 25.735 11.445 25.905 11.445 25.905 10.965 26.575 10.965 26.575 11.445 26.745 11.445 26.745 10.965 27.335 10.965 27.335 11.445 27.665 11.445 27.665 10.965 28.175 10.965 28.175 11.445 28.505 11.445 28.505 10.965 29.015 10.965 29.015 11.765 29.345 11.765 29.345 10.965 29.44 10.965 29.44 10.795 0 10.795 0 10.965 5.43 10.965 5.43 11.785 ; + RECT 88.32 10.795 92 10.965 ; + RECT 88.32 8.075 92 8.245 ; RECT 25.76 8.075 29.44 8.245 ; - RECT 91.08 5.355 92 5.525 ; + RECT 91.54 5.355 92 5.525 ; RECT 25.76 5.355 29.44 5.525 ; - RECT 88.32 2.635 92 2.805 ; + RECT 91.54 2.635 92 2.805 ; RECT 25.76 2.635 29.44 2.805 ; - RECT 25.76 -0.085 92 0.085 ; + POLYGON 87.845 0.885 87.845 0.085 89.325 0.085 89.325 0.81 89.615 0.81 89.615 0.085 92 0.085 92 -0.085 25.76 -0.085 25.76 0.085 29.525 0.085 29.525 0.81 29.815 0.81 29.815 0.085 30.335 0.085 30.335 0.565 30.505 0.565 30.505 0.085 31.175 0.085 31.175 0.565 31.345 0.565 31.345 0.085 31.935 0.085 31.935 0.565 32.265 0.565 32.265 0.085 32.775 0.085 32.775 0.565 33.105 0.565 33.105 0.085 33.615 0.085 33.615 0.885 33.945 0.885 33.945 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 41.415 0.085 41.415 0.885 41.745 0.885 41.745 0.085 42.255 0.085 42.255 0.565 42.585 0.565 42.585 0.085 43.095 0.085 43.095 0.565 43.425 0.565 43.425 0.085 43.935 0.085 43.935 0.565 44.265 0.565 44.265 0.085 44.775 0.085 44.775 0.565 45.105 0.565 45.105 0.085 45.615 0.085 45.615 0.565 45.945 0.565 45.945 0.085 46.935 0.085 46.935 0.885 47.265 0.885 47.265 0.085 47.775 0.085 47.775 0.565 48.105 0.565 48.105 0.085 48.615 0.085 48.615 0.565 48.945 0.565 48.945 0.085 49.455 0.085 49.455 0.565 49.785 0.565 49.785 0.085 50.295 0.085 50.295 0.565 50.625 0.565 50.625 0.085 51.135 0.085 51.135 0.565 51.465 0.565 51.465 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 53.875 0.085 53.875 0.565 54.205 0.565 54.205 0.085 54.715 0.085 54.715 0.565 55.045 0.565 55.045 0.085 55.555 0.085 55.555 0.565 55.885 0.565 55.885 0.085 56.395 0.085 56.395 0.565 56.725 0.565 56.725 0.085 57.235 0.085 57.235 0.565 57.565 0.565 57.565 0.085 58.075 0.085 58.075 0.885 58.405 0.885 58.405 0.085 60.735 0.085 60.735 0.885 61.065 0.885 61.065 0.085 61.575 0.085 61.575 0.565 61.905 0.565 61.905 0.085 62.415 0.085 62.415 0.565 62.745 0.565 62.745 0.085 63.255 0.085 63.255 0.565 63.585 0.565 63.585 0.085 64.095 0.085 64.095 0.565 64.425 0.565 64.425 0.085 64.935 0.085 64.935 0.565 65.265 0.565 65.265 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 71.315 0.085 71.315 0.885 71.645 0.885 71.645 0.085 72.155 0.085 72.155 0.565 72.485 0.565 72.485 0.085 72.995 0.085 72.995 0.565 73.325 0.565 73.325 0.085 73.835 0.085 73.835 0.565 74.165 0.565 74.165 0.085 74.675 0.085 74.675 0.565 75.005 0.565 75.005 0.085 75.515 0.085 75.515 0.565 75.845 0.565 75.845 0.085 76.875 0.085 76.875 0.565 77.205 0.565 77.205 0.085 77.715 0.085 77.715 0.565 78.045 0.565 78.045 0.085 78.555 0.085 78.555 0.565 78.885 0.565 78.885 0.085 79.395 0.085 79.395 0.565 79.725 0.565 79.725 0.085 80.235 0.085 80.235 0.565 80.565 0.565 80.565 0.085 81.075 0.085 81.075 0.885 81.405 0.885 81.405 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 83.315 0.085 83.315 0.565 83.645 0.565 83.645 0.085 84.155 0.085 84.155 0.565 84.485 0.565 84.485 0.085 84.995 0.085 84.995 0.565 85.325 0.565 85.325 0.085 85.835 0.085 85.835 0.565 86.165 0.565 86.165 0.085 86.675 0.085 86.675 0.565 87.005 0.565 87.005 0.085 87.515 0.085 87.515 0.885 ; POLYGON 91.83 108.63 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 25.93 97.75 25.93 108.63 ; LAYER mcon ; + RECT 42.465 98.345 42.635 98.515 ; + RECT 40.165 98.345 40.335 98.515 ; RECT 35.565 98.345 35.735 98.515 ; - RECT 44.765 97.325 44.935 97.495 ; - RECT 44.825 11.305 44.995 11.475 ; - RECT 42.925 11.305 43.095 11.475 ; - RECT 40.685 11.305 40.855 11.475 ; - RECT 38.785 11.305 38.955 11.475 ; - RECT 36.085 11.305 36.255 11.475 ; - RECT 31.055 11.305 31.225 11.475 ; - RECT 30.965 10.285 31.135 10.455 ; - RECT 28.665 10.285 28.835 10.455 ; + RECT 34.185 98.345 34.355 98.515 ; + RECT 31.885 98.345 32.055 98.515 ; + RECT 44.765 11.305 44.935 11.475 ; + RECT 27.835 11.305 28.005 11.475 ; LAYER via ; RECT 80.885 108.725 81.035 108.875 ; RECT 51.445 108.725 51.595 108.875 ; RECT 42.475 98.355 42.625 98.505 ; - RECT 34.195 98.355 34.345 98.505 ; + RECT 35.575 98.355 35.725 98.505 ; + RECT 31.895 98.355 32.045 98.505 ; RECT 10.965 97.845 11.115 97.995 ; - RECT 39.715 97.335 39.865 97.485 ; - RECT 29.595 97.335 29.745 97.485 ; - RECT 40.635 11.315 40.785 11.465 ; - RECT 37.875 11.315 38.025 11.465 ; - RECT 30.975 11.315 31.125 11.465 ; + RECT 34.195 97.335 34.345 97.485 ; + RECT 28.215 97.335 28.365 97.485 ; + RECT 12.575 97.335 12.725 97.485 ; + RECT 34.195 11.315 34.345 11.465 ; + RECT 28.215 11.315 28.365 11.465 ; + RECT 1.075 11.315 1.225 11.465 ; RECT 10.965 10.805 11.115 10.955 ; - RECT 31.895 10.295 32.045 10.445 ; - RECT 28.675 10.295 28.825 10.445 ; + RECT 77.435 0.435 77.585 0.585 ; RECT 80.885 -0.075 81.035 0.075 ; RECT 51.445 -0.075 51.595 0.075 ; LAYER via2 ; RECT 80.86 108.7 81.06 108.9 ; RECT 51.42 108.7 51.62 108.9 ; + RECT 54.87 108.36 55.07 108.56 ; RECT 10.94 97.82 11.14 98.02 ; + RECT 1.05 62.12 1.25 62.32 ; + RECT 1.05 15.88 1.25 16.08 ; + RECT 19.91 11.12 20.11 11.32 ; + RECT 15.31 11.12 15.51 11.32 ; RECT 10.94 10.78 11.14 10.98 ; RECT 80.86 -0.1 81.06 0.1 ; RECT 51.42 -0.1 51.62 0.1 ; LAYER via3 ; RECT 80.86 108.7 81.06 108.9 ; RECT 51.42 108.7 51.62 108.9 ; + RECT 54.64 108.36 54.84 108.56 ; RECT 10.94 97.82 11.14 98.02 ; + RECT 8.64 11.12 8.84 11.32 ; RECT 10.94 10.78 11.14 10.98 ; RECT 80.86 -0.1 81.06 0.1 ; RECT 51.42 -0.1 51.62 0.1 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__2__icv_in_design.lef b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__2__icv_in_design.lef index 9f43a41..ba64680 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__2__icv_in_design.lef +++ b/FPGA1212_SOFA_HD_PNR/modules/lef/sb_2__2__icv_in_design.lef @@ -1298,6 +1298,11 @@ MACRO sb_2__2_ RECT 51.38 97.735 51.66 98.105 ; RECT 10.9 97.735 11.18 98.105 ; RECT 10.9 10.695 11.18 11.065 ; + POLYGON 71.6 9.25 71.6 0.24 71.64 0.24 71.64 0.1 71.46 0.1 71.46 9.25 ; + POLYGON 67 5 67 0.1 66.82 0.1 66.82 0.24 66.86 0.24 66.86 5 ; + POLYGON 33.42 3.13 33.42 0.24 33.46 0.24 33.46 0.1 33.28 0.1 33.28 3.13 ; + RECT 34.6 0.69 34.86 1.01 ; + RECT 30.92 0.69 31.18 1.01 ; RECT 80.82 -0.185 81.1 0.185 ; RECT 51.38 -0.185 51.66 0.185 ; POLYGON 91.72 97.64 91.72 0.28 82.92 0.28 82.92 0.765 82.22 0.765 82.22 0.28 82 0.28 82 0.765 81.3 0.765 81.3 0.28 80.62 0.28 80.62 0.765 79.92 0.765 79.92 0.28 79.7 0.28 79.7 0.765 79 0.765 79 0.28 78.78 0.28 78.78 0.765 78.08 0.765 78.08 0.28 77.86 0.28 77.86 0.765 77.16 0.765 77.16 0.28 76.94 0.28 76.94 0.765 76.24 0.765 76.24 0.28 76.02 0.28 76.02 0.765 75.32 0.765 75.32 0.28 75.1 0.28 75.1 0.765 74.4 0.765 74.4 0.28 74.18 0.28 74.18 0.765 73.48 0.765 73.48 0.28 73.26 0.28 73.26 0.765 72.56 0.765 72.56 0.28 72.34 0.28 72.34 0.765 71.64 0.765 71.64 0.28 71.42 0.28 71.42 0.765 70.72 0.765 70.72 0.28 70.5 0.28 70.5 0.765 69.8 0.765 69.8 0.28 69.58 0.28 69.58 0.765 68.88 0.765 68.88 0.28 68.66 0.28 68.66 0.765 67.96 0.765 67.96 0.28 67.74 0.28 67.74 0.765 67.04 0.765 67.04 0.28 66.82 0.28 66.82 0.765 66.12 0.765 66.12 0.28 65.9 0.28 65.9 0.765 65.2 0.765 65.2 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 62.68 0.28 62.68 0.765 61.98 0.765 61.98 0.28 61.76 0.28 61.76 0.765 61.06 0.765 61.06 0.28 60.38 0.28 60.38 0.765 59.68 0.765 59.68 0.28 59.46 0.28 59.46 0.765 58.76 0.765 58.76 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 55.78 0.28 55.78 0.765 55.08 0.765 55.08 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 53.48 0.28 53.48 0.765 52.78 0.765 52.78 0.28 52.56 0.28 52.56 0.765 51.86 0.765 51.86 0.28 50.72 0.28 50.72 0.765 50.02 0.765 50.02 0.28 49.8 0.28 49.8 0.765 49.1 0.765 49.1 0.28 48.42 0.28 48.42 0.765 47.72 0.765 47.72 0.28 47.5 0.28 47.5 0.765 46.8 0.765 46.8 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 35.54 0.28 35.54 0.765 34.84 0.765 34.84 0.28 34.16 0.28 34.16 0.765 33.46 0.765 33.46 0.28 32.78 0.28 32.78 0.765 32.08 0.765 32.08 0.28 31.86 0.28 31.86 0.765 31.16 0.765 31.16 0.28 28.64 0.28 28.64 0.765 27.94 0.765 27.94 0.28 26.04 0.28 26.04 11.16 23.58 11.16 23.58 11.645 22.88 11.645 22.88 11.16 15.76 11.16 15.76 11.645 15.06 11.645 15.06 11.16 14.84 11.16 14.84 11.645 14.14 11.645 14.14 11.16 13.92 11.16 13.92 11.645 13.22 11.645 13.22 11.16 13 11.16 13 11.645 12.3 11.645 12.3 11.16 12.08 11.16 12.08 11.645 11.38 11.645 11.38 11.16 10.7 11.16 10.7 11.645 10 11.645 10 11.16 9.32 11.16 9.32 11.645 8.62 11.645 8.62 11.16 8.4 11.16 8.4 11.645 7.7 11.645 7.7 11.16 7.48 11.16 7.48 11.645 6.78 11.645 6.78 11.16 6.56 11.16 6.56 11.645 5.86 11.645 5.86 11.16 5.64 11.16 5.64 11.645 4.94 11.645 4.94 11.16 4.72 11.16 4.72 11.645 4.02 11.645 4.02 11.16 3.34 11.16 3.34 11.645 2.64 11.645 2.64 11.16 0.28 11.16 0.28 97.64 ; @@ -1305,8 +1310,6 @@ MACRO sb_2__2_ POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; - POLYGON 17.17 58.97 17.17 58.67 0.65 58.67 0.65 58.95 1.2 58.95 1.2 58.97 ; - POLYGON 15.1 39.93 15.1 39.63 1.2 39.63 1.2 39.65 0.65 39.65 0.65 39.93 ; POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; @@ -1315,20 +1318,26 @@ MACRO sb_2__2_ POLYGON 91.6 97.52 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.29 11.28 9.29 12.08 8.19 12.08 8.19 11.28 7.45 11.28 7.45 12.08 6.35 12.08 6.35 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 36.1 97.52 36.1 96.92 37.5 96.92 37.5 97.52 50.82 97.52 50.82 96.92 52.22 96.92 52.22 97.52 65.54 97.52 65.54 96.92 66.94 96.92 66.94 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 ; LAYER met1 ; RECT 45.68 97.68 46.32 98.16 ; - POLYGON 37.65 11.52 37.65 11.26 37.33 11.26 37.33 11.32 36.715 11.32 36.715 11.275 36.425 11.275 36.425 11.505 36.715 11.505 36.715 11.46 37.33 11.46 37.33 11.52 ; + POLYGON 39.4 12.14 39.4 11.46 50.44 11.46 50.44 11.32 39.26 11.32 39.26 12.14 ; + POLYGON 34.89 11.52 34.89 11.26 34.57 11.26 34.57 11.32 33.955 11.32 33.955 11.275 33.665 11.275 33.665 11.505 33.955 11.505 33.955 11.46 34.57 11.46 34.57 11.52 ; + POLYGON 23.39 11.52 23.39 11.26 23.07 11.26 23.07 11.32 11.505 11.32 11.505 11.275 11.215 11.275 11.215 11.505 11.505 11.505 11.505 11.46 23.07 11.46 23.07 11.52 ; + POLYGON 45.47 10.5 45.47 10.44 46.3 10.44 46.3 10.3 45.47 10.3 45.47 10.24 45.15 10.24 45.15 10.5 ; + POLYGON 36.73 10.5 36.73 10.24 36.41 10.24 36.41 10.255 36.025 10.255 36.025 10.485 36.41 10.485 36.41 10.5 ; + RECT 31.81 10.24 32.13 10.5 ; + POLYGON 34.415 10.485 34.415 10.255 34.125 10.255 34.125 10.3 32.96 10.3 32.96 9.96 32.82 9.96 32.82 10.44 34.125 10.44 34.125 10.485 ; RECT 45.68 -0.24 46.32 0.24 ; POLYGON 46.32 97.64 46.32 97.4 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 91.24 11.4 91.24 10.36 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 46.32 0.52 46.32 0.28 45.68 0.28 45.68 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 45.68 10.36 45.68 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 45.68 97.4 45.68 97.64 ; LAYER met5 ; POLYGON 90.4 96.32 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; LAYER li1 ; - RECT 0 97.835 92 98.005 ; - RECT 88.32 95.115 92 95.285 ; + POLYGON 92 98.005 92 97.835 89.615 97.835 89.615 97.11 89.325 97.11 89.325 97.835 82.255 97.835 82.255 97.11 81.965 97.11 81.965 97.835 67.535 97.835 67.535 97.11 67.245 97.11 67.245 97.835 52.355 97.835 52.355 97.11 52.065 97.11 52.065 97.835 37.635 97.835 37.635 97.11 37.345 97.11 37.345 97.835 22.455 97.835 22.455 97.11 22.165 97.11 22.165 97.835 7.735 97.835 7.735 97.11 7.445 97.11 7.445 97.835 0 97.835 0 98.005 ; + RECT 91.54 95.115 92 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 88.32 92.395 92 92.565 ; + RECT 91.54 92.395 92 92.565 ; RECT 0 92.395 3.68 92.565 ; - RECT 88.32 89.675 92 89.845 ; + RECT 91.54 89.675 92 89.845 ; RECT 0 89.675 3.68 89.845 ; - RECT 88.32 86.955 92 87.125 ; + RECT 91.54 86.955 92 87.125 ; RECT 0 86.955 3.68 87.125 ; RECT 91.54 84.235 92 84.405 ; RECT 0 84.235 3.68 84.405 ; @@ -1336,78 +1345,87 @@ MACRO sb_2__2_ RECT 0 81.515 3.68 81.685 ; RECT 91.54 78.795 92 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 90.16 76.075 92 76.245 ; + RECT 91.54 76.075 92 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 90.16 73.355 92 73.525 ; + RECT 91.54 73.355 92 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 88.32 70.635 92 70.805 ; + RECT 91.54 70.635 92 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 88.32 67.915 92 68.085 ; + RECT 91.54 67.915 92 68.085 ; RECT 0 67.915 3.68 68.085 ; RECT 90.16 65.195 92 65.365 ; - RECT 0 65.195 1.84 65.365 ; + RECT 0 65.195 3.68 65.365 ; RECT 90.16 62.475 92 62.645 ; - RECT 0 62.475 3.68 62.645 ; + RECT 0 62.475 1.84 62.645 ; RECT 90.16 59.755 92 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 88.32 57.035 92 57.205 ; + RECT 90.16 57.035 92 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 88.32 54.315 92 54.485 ; + RECT 91.54 54.315 92 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 91.08 51.595 92 51.765 ; + RECT 91.54 51.595 92 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 91.08 48.875 92 49.045 ; + RECT 91.54 48.875 92 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 91.08 46.155 92 46.325 ; + RECT 91.54 46.155 92 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 91.08 43.435 92 43.605 ; + RECT 91.54 43.435 92 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 88.32 40.715 92 40.885 ; + RECT 91.54 40.715 92 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 88.32 37.995 92 38.165 ; + RECT 90.16 37.995 92 38.165 ; RECT 0 37.995 3.68 38.165 ; RECT 90.16 35.275 92 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 88.32 32.555 92 32.725 ; + RECT 91.54 32.555 92 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 88.32 29.835 92 30.005 ; + RECT 91.54 29.835 92 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 91.08 27.115 92 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 91.08 24.395 92 24.565 ; + RECT 90.16 27.115 92 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 90.16 24.395 92 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 91.08 21.675 92 21.845 ; + RECT 88.32 21.675 92 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 91.08 18.955 92 19.125 ; + RECT 88.32 18.955 92 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 91.54 16.235 92 16.405 ; + RECT 88.32 16.235 92 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 91.08 13.515 92 13.685 ; + RECT 88.32 13.515 92 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 91.08 10.795 92 10.965 ; - RECT 0 10.795 29.44 10.965 ; + POLYGON 17.445 11.765 17.445 10.965 17.955 10.965 17.955 11.445 18.285 11.445 18.285 10.965 18.795 10.965 18.795 11.445 19.125 11.445 19.125 10.965 19.715 10.965 19.715 11.445 19.885 11.445 19.885 10.965 20.555 10.965 20.555 11.445 20.725 11.445 20.725 10.965 22.165 10.965 22.165 11.69 22.455 11.69 22.455 10.965 29.44 10.965 29.44 10.795 0 10.795 0 10.965 3.315 10.965 3.315 11.765 3.645 11.765 3.645 10.965 4.155 10.965 4.155 11.445 4.485 11.445 4.485 10.965 4.995 10.965 4.995 11.445 5.325 11.445 5.325 10.965 5.915 10.965 5.915 11.445 6.085 11.445 6.085 10.965 6.755 10.965 6.755 11.445 6.925 11.445 6.925 10.965 7.445 10.965 7.445 11.69 7.735 11.69 7.735 10.965 9.175 10.965 9.175 11.445 9.345 11.445 9.345 10.965 10.015 10.965 10.015 11.445 10.185 11.445 10.185 10.965 10.775 10.965 10.775 11.445 11.105 11.445 11.105 10.965 11.615 10.965 11.615 11.445 11.945 11.445 11.945 10.965 12.455 10.965 12.455 11.765 12.785 11.765 12.785 10.965 17.115 10.965 17.115 11.765 ; + RECT 91.54 10.795 92 10.965 ; RECT 91.54 8.075 92 8.245 ; RECT 25.76 8.075 29.44 8.245 ; - RECT 91.08 5.355 92 5.525 ; + RECT 91.54 5.355 92 5.525 ; RECT 25.76 5.355 29.44 5.525 ; - RECT 88.32 2.635 92 2.805 ; + RECT 91.54 2.635 92 2.805 ; RECT 25.76 2.635 29.44 2.805 ; - RECT 25.76 -0.085 92 0.085 ; + POLYGON 87.305 0.885 87.305 0.085 89.325 0.085 89.325 0.81 89.615 0.81 89.615 0.085 92 0.085 92 -0.085 25.76 -0.085 25.76 0.085 29.525 0.085 29.525 0.81 29.815 0.81 29.815 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 38.235 0.085 38.235 0.465 38.565 0.465 38.565 0.085 39.175 0.085 39.175 0.545 39.425 0.545 39.425 0.085 41.12 0.085 41.12 0.585 41.49 0.585 41.49 0.085 43.345 0.085 43.345 0.615 43.515 0.615 43.515 0.085 44.345 0.085 44.345 0.565 44.515 0.565 44.515 0.085 45.215 0.085 45.215 0.56 45.385 0.56 45.385 0.085 46.065 0.085 46.065 0.56 46.235 0.56 46.235 0.085 47.355 0.085 47.355 0.565 47.525 0.565 47.525 0.085 48.195 0.085 48.195 0.565 48.365 0.565 48.365 0.085 48.955 0.085 48.955 0.565 49.285 0.565 49.285 0.085 49.795 0.085 49.795 0.565 50.125 0.565 50.125 0.085 50.635 0.085 50.635 0.885 50.965 0.885 50.965 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 52.575 0.085 52.575 0.545 52.88 0.545 52.88 0.085 53.55 0.085 53.55 0.545 53.72 0.545 53.72 0.085 54.39 0.085 54.39 0.545 54.56 0.545 54.56 0.085 55.23 0.085 55.23 0.545 55.4 0.545 55.4 0.085 56.07 0.085 56.07 0.545 56.325 0.545 56.325 0.085 61.315 0.085 61.315 0.545 61.62 0.545 61.62 0.085 62.29 0.085 62.29 0.545 62.46 0.545 62.46 0.085 63.13 0.085 63.13 0.545 63.3 0.545 63.3 0.085 63.97 0.085 63.97 0.545 64.14 0.545 64.14 0.085 64.81 0.085 64.81 0.545 65.065 0.545 65.065 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 72.275 0.085 72.275 0.465 72.605 0.465 72.605 0.085 73.215 0.085 73.215 0.545 73.465 0.545 73.465 0.085 75.16 0.085 75.16 0.585 75.53 0.585 75.53 0.085 77.385 0.085 77.385 0.615 77.555 0.615 77.555 0.085 78.385 0.085 78.385 0.565 78.555 0.565 78.555 0.085 79.255 0.085 79.255 0.56 79.425 0.56 79.425 0.085 80.105 0.085 80.105 0.56 80.275 0.56 80.275 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 83.695 0.085 83.695 0.565 83.865 0.565 83.865 0.085 84.535 0.085 84.535 0.565 84.705 0.565 84.705 0.085 85.295 0.085 85.295 0.565 85.625 0.565 85.625 0.085 86.135 0.085 86.135 0.565 86.465 0.565 86.465 0.085 86.975 0.085 86.975 0.885 ; POLYGON 91.83 97.75 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 ; LAYER mcon ; - RECT 36.485 11.305 36.655 11.475 ; + RECT 33.725 11.305 33.895 11.475 ; + RECT 11.275 11.305 11.445 11.475 ; + RECT 36.085 10.285 36.255 10.455 ; + RECT 34.185 10.285 34.355 10.455 ; + RECT 31.89 10.285 32.06 10.455 ; LAYER via ; RECT 80.885 97.845 81.035 97.995 ; RECT 51.445 97.845 51.595 97.995 ; RECT 10.965 97.845 11.115 97.995 ; - RECT 37.415 11.315 37.565 11.465 ; + RECT 34.655 11.315 34.805 11.465 ; + RECT 23.155 11.315 23.305 11.465 ; RECT 10.965 10.805 11.115 10.955 ; + RECT 45.235 10.295 45.385 10.445 ; + RECT 36.495 10.295 36.645 10.445 ; + RECT 31.895 10.295 32.045 10.445 ; RECT 80.885 -0.075 81.035 0.075 ; RECT 51.445 -0.075 51.595 0.075 ; LAYER via2 ; RECT 80.86 97.82 81.06 98.02 ; RECT 51.42 97.82 51.62 98.02 ; RECT 10.94 97.82 11.14 98.02 ; + RECT 1.05 45.8 1.25 46 ; RECT 10.94 10.78 11.14 10.98 ; RECT 80.86 -0.1 81.06 0.1 ; RECT 51.42 -0.1 51.62 0.1 ; diff --git a/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef b/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef index cd34696..fcf2841 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef +++ b/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2a39cc5220a3d0e2e31d0cbe384a751867337735e815717b51b8846c7d10cdaa -size 1121369 +oid sha256:7d651bbb7ebf5b602c5d080cf462972df8655a280817b8907bd6a2027cd0723e +size 1093457 diff --git a/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef b/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef index 1c9f159..e72308e 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef +++ b/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d1fbde00eeebe500884f2510d863a7f5f7ff5edaeb788aba3eb40578c5ca05e5 -size 1119370 +oid sha256:e188452d890aeab687d7a226e88cb422eb61769d71e07061654e3c904104f3a1 +size 1189070 diff --git a/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef b/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef index 00340ca..d5a1867 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef +++ b/FPGA1212_SOFA_HD_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid 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- + @@ -4979,24 +4804,24 @@ z - - + + - + - + - + @@ -5004,18 +4829,18 @@ z - + - - - + + - + - - + +" id="DejaVuSans-99"/> - + @@ -5098,48 +4940,48 @@ z - - + + - - - - - - - - - - - - + + + + + + + + + + + + - - + - - + - + - + @@ -5149,17 +4991,17 @@ z - - + - + - + @@ -5171,7 +5013,7 @@ z - + - + + - - + + - - + + - - + + - - + + - - + + diff --git a/FPGA1212_SOFA_HD_PNR/modules/timing/sb_2__2__timingPlots.svg b/FPGA1212_SOFA_HD_PNR/modules/timing/sb_2__2__timingPlots.svg index 690c972..baa5c75 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/timing/sb_2__2__timingPlots.svg +++ b/FPGA1212_SOFA_HD_PNR/modules/timing/sb_2__2__timingPlots.svg @@ -19,22 +19,22 @@ z - - - + - - - - - - - - - - - - - - - - - - + - + @@ -151,13 +109,13 @@ z - - - + + - + + - + @@ -201,15 +183,15 @@ z - - - + + - + - + @@ -217,13 +199,13 @@ L 142.265404 40.32 - - - + + - + - + @@ -265,13 +247,13 @@ z - - - + + - + - + @@ -322,13 +304,13 @@ z - - - + + - + - + @@ -370,15 +352,15 @@ z - - - + + - + - + @@ -389,64 +371,64 @@ L 266.549673 40.32 - - + - + - + - - + - + - + - - + - + - + - - + - + - + - - + - + - + + + + + + + + + + + + - - - - + + + - - +" style="fill:#1f77b4;opacity:0.4;stroke:#ffffff;stroke-linejoin:miter;"/> - - - - - - - - @@ -890,7 +885,7 @@ L 9.71875 75.984375 z " id="DejaVuSans-93"/> - + @@ -1036,7 +1031,7 @@ Q 15.875 39.890625 15.1875 32.171875 z " id="DejaVuSans-101"/> - + @@ -1047,7 +1042,7 @@ z - + - + - - + + @@ -1088,7 +1083,7 @@ L 44.28125 54.6875 z " id="DejaVuSans-120"/> - + @@ -1099,7 +1094,7 @@ z - + - + - - + + - + - - + + - + - + @@ -1262,7 +1257,7 @@ M 31.109375 56 z " id="DejaVuSans-117"/> - + @@ -1295,23 +1290,23 @@ z - - @@ -1359,7 +1354,7 @@ Q 50 49.953125 52 44.1875 z " id="DejaVuSans-109"/> - + @@ -1370,16 +1365,16 @@ z - - + @@ -1393,39 +1388,23 @@ z - - + - - - - - - - - - - - - - - - - + @@ -1433,15 +1412,15 @@ L 342.125197 40.32 - - - + + - + - + @@ -1449,15 +1428,15 @@ L 368.679042 40.32 - - - + + - + - + @@ -1465,15 +1444,15 @@ L 395.232887 40.32 - - - + + - + - + @@ -1481,15 +1460,15 @@ L 421.786732 40.32 - - - + + - + - + @@ -1497,15 +1476,15 @@ L 448.340576 40.32 - - - + + - + - + @@ -1513,15 +1492,15 @@ L 474.894421 40.32 - - - + + - + - + @@ -1529,15 +1508,15 @@ L 501.448266 40.32 - - - + + - + - + @@ -1545,15 +1524,15 @@ L 528.002111 40.32 - - - + + - + - + @@ -1563,425 +1542,399 @@ L 554.555956 40.32 - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - - - - - - - - - - - + - - - - - - - - - - - - - - - + + + + - - - - - - - - - - + - - + - - - - - + - - + @@ -1995,7 +1948,7 @@ z - + @@ -2006,24 +1959,24 @@ z - - + + - - + + - + - + @@ -2034,34 +1987,34 @@ z - - + + - - + + - + - - + + - + - + - + - + @@ -2126,29 +2079,29 @@ z - - - + - + @@ -2159,16 +2112,16 @@ z - - + - + @@ -2182,143 +2135,143 @@ z - - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + @@ -2327,342 +2280,355 @@ L 828.635846 40.32 - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + + + + + + + + + + + + - - - - - - - - + - - + - @@ -2671,16 +2637,16 @@ L 845.28 40.32 " style="fill:none;stroke:#ffffff;stroke-linecap:square;stroke-linejoin:miter;stroke-width:0.8;"/> - - - + - + - + @@ -2743,13 +2709,13 @@ z - + - + @@ -2759,20 +2725,20 @@ z - + - - + + - + - + @@ -2810,29 +2776,29 @@ z - - - + - + @@ -2843,16 +2809,16 @@ z - - + - + @@ -2866,509 +2832,551 @@ z - - - - + + - - - + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + - - + - - - + + - - + - - - + + - - + - - - + + - - + - - - + + - - + - - - - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - + - + - + - - + - - - - + + + + - - + - - - - + + + + - - + - - - - + + + + - - + - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - + - - + - - - - - + - - + @@ -3381,7 +3389,7 @@ z - + @@ -3392,13 +3400,13 @@ z - - + + - + @@ -3409,7 +3417,7 @@ z - + @@ -3420,8 +3428,8 @@ z - - + + @@ -3433,21 +3441,21 @@ z - + - - + + - - + + - + - + - + @@ -3509,29 +3517,29 @@ z - - - + - + @@ -3542,16 +3550,16 @@ z - - + - + @@ -3565,98 +3573,98 @@ z - - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + @@ -3665,90 +3673,90 @@ L 565.195938 296.037209 - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + @@ -3757,36 +3765,36 @@ L 565.195938 296.037209 - - - - - @@ -3794,96 +3802,96 @@ z - - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + @@ -3894,90 +3902,90 @@ L 845.28 296.037209 - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + - - - + + - + - + @@ -3986,8 +3994,8 @@ L 845.28 296.037209 - @@ -3996,25 +4004,25 @@ L 845.28 296.037209 " style="fill:none;stroke:#ffffff;stroke-linecap:square;stroke-linejoin:miter;stroke-width:0.8;"/> - - - + - - + - - + +" id="DejaVuSans-99"/> - + @@ -4097,40 +4122,40 @@ z - - + + - - - - - - - - - - - - + + + + + + + + + + + + - - + - + + - - + + - - + + - - + + - - + + - - + + diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v index f10c6db..beddc34 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v @@ -11,23 +11,21 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_124 ; +wire copt_net_122 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_124 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_122 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_119 ) , - .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_124 ) , - .X ( copt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_118 ) , - .X ( copt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_122 ) , +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1346 ( .A ( copt_net_124 ) , .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , - .X ( copt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_120 ) , - .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( copt_net_125 ) , + .X ( copt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_126 ) , + .X ( copt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_127 ) , + .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_122 ) , + .X ( copt_net_127 ) ) ; endmodule @@ -42,17 +40,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_511_ ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_88 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( BUF_net_88 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_112 ( .A ( BUF_net_90 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_90 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -132,16 +130,13 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_85 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_85 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( BUF_net_85 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_87 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_87 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; endmodule @@ -222,15 +217,16 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_82 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_87 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_86 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_86 ( .A ( BUF_net_88 ) , .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_88 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_88 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -311,16 +307,14 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_508_ ) , - .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_84 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_81 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -400,16 +394,13 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_76 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( net_net_80 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_76 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_76 ( .A ( BUF_net_78 ) , .Y ( BUF_net_76 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_78 ) ) ; + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( SOC_DIR ) ) ; endmodule @@ -489,16 +480,19 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_73 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_507_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_73 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_73 ( .A ( BUF_net_75 ) , .Y ( BUF_net_73 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_75 ) ) ; + .TE_B ( BUF_net_77 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_77 ( .A ( BUF_net_79 ) , .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( BUF_net_78 ) , .Y ( BUF_net_107 ) ) ; endmodule @@ -568,7 +562,7 @@ endmodule module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_184_0 ) ; + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_211_0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -576,22 +570,22 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_211_0 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( ZBUF_184_0 ) , .Z ( SOC_OUT ) ) ; + .TE_B ( ZBUF_211_0 ) , .Z ( SOC_OUT ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , - iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_184_0 ) ; + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -601,7 +595,7 @@ input [0:0] iopad_outpad ; input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; wire [0:0] EMBEDDED_IO_HD_0_en ; @@ -611,7 +605,7 @@ cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , - .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .ZBUF_211_0 ( ZBUF_211_0 ) ) ; cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; @@ -621,7 +615,7 @@ endmodule module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , ZBUF_184_0 ) ; + ccff_tail , ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -631,7 +625,7 @@ input [0:0] io_outpad ; input [0:0] ccff_head ; output [0:0] io_inpad ; output [0:0] ccff_tail ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , @@ -640,7 +634,7 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .ZBUF_211_0 ( ZBUF_211_0 ) ) ; endmodule @@ -668,16 +662,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_70 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_506_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_72 ) ) ; + .TE_B ( BUF_net_74 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_76 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_74 ( .A ( BUF_net_76 ) , .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -757,13 +752,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( net_net_69 ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__buf_8 BUFT_RR_69 ( .A ( net_net_69 ) , .X ( SOC_DIR ) ) ; + .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -978,7 +977,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_136 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -987,6 +986,20 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( ccff_head[0] ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_117 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_118 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_120 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_121 ) , + .X ( ropt_net_136 ) ) ; endmodule @@ -1147,6 +1160,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1176,8 +1191,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1239,9 +1252,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -1303,7 +1316,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1366,9 +1379,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -1430,9 +1443,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_96 ) ) ; endmodule @@ -1494,9 +1507,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1558,7 +1570,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1676,7 +1688,7 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1685,7 +1697,7 @@ cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1694,7 +1706,7 @@ cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1703,7 +1715,7 @@ cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -1712,7 +1724,7 @@ cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1721,7 +1733,7 @@ cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1730,7 +1742,7 @@ cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1739,7 +1751,7 @@ cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -1748,7 +1760,7 @@ cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1814,12 +1826,12 @@ cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_511_ } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_5_lower ) , .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , - .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; + .ZBUF_211_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , @@ -1874,10 +1886,10 @@ cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_17_lower ) , .ccff_tail ( ccff_tail ) ) ; -sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1117 ) ) ; + .X ( ctsbuf_net_1115 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -1987,15 +1999,15 @@ sky130_fd_sc_hd__buf_6 FTB_67__66 ( .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , - .HI ( optlc_net_116 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_211_inst_119 ( .A ( aps_rename_511_ ) , .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3521246 ( .A ( ctsbuf_net_1115 ) , .X ( prog_clk_0_W_out ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v index a216339..b908920 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v @@ -13,27 +13,25 @@ output [0:0] mem_out ; input VDD ; input VSS ; -wire copt_net_124 ; +wire copt_net_122 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_124 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_119 ) , - .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_124 ) , - .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_118 ) , - .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_122 ) , +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1346 ( .A ( copt_net_124 ) , .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , - .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_120 ) , - .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( copt_net_125 ) , + .X ( copt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_126 ) , + .X ( copt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_127 ) , + .X ( copt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_122 ) , + .X ( copt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -53,19 +51,19 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) , .VPWR ( VDD ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_511_ ) , +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_88 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( BUF_net_88 ) , + .TE_B ( BUF_net_90 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_112 ( .A ( BUF_net_90 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -169,19 +167,14 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_85 ) , .Y ( SOC_DIR_N ) , + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_85 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( BUF_net_85 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_87 ) , .Y ( SOC_DIR ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -287,17 +280,19 @@ supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_82 ) , .Y ( SOC_DIR_N ) , +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_87 ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) , + .TE_B ( BUF_net_86 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_86 ( .A ( BUF_net_88 ) , .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( BUF_net_87 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_88 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -403,18 +398,16 @@ supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_508_ ) , - .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .TE_B ( BUF_net_84 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) , + .TE_B ( BUF_net_81 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -517,20 +510,15 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_76 ) , .Y ( SOC_DIR_N ) , + .B ( IO_ISOL_N ) , .Y ( net_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_76 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_76 ( .A ( BUF_net_78 ) , .Y ( BUF_net_76 ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -633,20 +621,24 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) , .VPWR ( VDD ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_73 ) , .Y ( SOC_DIR_N ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_507_ ) , + .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_73 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_73 ( .A ( BUF_net_75 ) , .Y ( BUF_net_73 ) , + .TE_B ( BUF_net_77 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_77 ( .A ( BUF_net_79 ) , .Y ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( BUF_net_78 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( BUF_net_78 ) , .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -734,7 +726,7 @@ endmodule module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_184_0 ) ; + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_211_0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -744,19 +736,19 @@ input FPGA_DIR ; input IO_ISOL_N ; input VDD ; input VSS ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_211_0 ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( ZBUF_184_0 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .TE_B ( ZBUF_211_0 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -764,7 +756,7 @@ module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , - ZBUF_184_0 ) ; + ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -776,7 +768,7 @@ output [0:0] iopad_inpad ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; wire [0:0] EMBEDDED_IO_HD_0_en ; supply1 VDD ; @@ -788,7 +780,7 @@ cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_211_0 ( ZBUF_211_0 ) ) ; cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , @@ -799,7 +791,7 @@ endmodule module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , ZBUF_184_0 ) ; + ccff_tail , VDD , VSS , ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -811,7 +803,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; supply1 VDD ; supply0 VSS ; @@ -823,7 +815,7 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .VSS ( VSS ) , .ZBUF_211_0 ( ZBUF_211_0 ) ) ; endmodule @@ -862,20 +854,20 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_70 ) , .Y ( SOC_DIR_N ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_506_ ) , + .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) , + .TE_B ( BUF_net_74 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_76 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_4 BINV_R_74 ( .A ( BUF_net_76 ) , .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -978,15 +970,20 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( net_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 BUFT_RR_69 ( .A ( net_net_69 ) , .X ( SOC_DIR ) , + .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1266,7 +1263,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_136 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1276,6 +1273,20 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( ccff_head[0] ) , + .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_117 ) , + .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_118 ) , + .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_120 ) , + .X ( copt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_121 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1430,6 +1441,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1464,8 +1478,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1526,10 +1538,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1590,7 +1602,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1652,10 +1664,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1716,10 +1728,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1780,10 +1792,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1844,7 +1854,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1967,7 +1977,7 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1977,7 +1987,7 @@ cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1987,7 +1997,7 @@ cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; + .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1997,7 +2007,7 @@ cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; + .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -2007,7 +2017,7 @@ cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; + .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -2017,7 +2027,7 @@ cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; + .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -2027,7 +2037,7 @@ cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -2037,7 +2047,7 @@ cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -2047,7 +2057,7 @@ cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( bottom_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; + .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2115,12 +2125,12 @@ cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_511_ } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_5_lower ) , .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; + .VSS ( VSS ) , .ZBUF_211_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , @@ -2180,10 +2190,10 @@ cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_17_lower ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_1115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -2304,16 +2314,16 @@ sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , - .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , - .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_211_inst_119 ( .A ( aps_rename_511_ ) , .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3521246 ( .A ( ctsbuf_net_1115 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v index cfe07fe..d5c9b65 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v @@ -11,23 +11,21 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_124 ; +wire copt_net_122 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_124 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_122 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_119 ) , - .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_124 ) , - .X ( copt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_118 ) , - .X ( copt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_122 ) , +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1346 ( .A ( copt_net_124 ) , .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , - .X ( copt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_120 ) , - .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( copt_net_125 ) , + .X ( copt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_126 ) , + .X ( copt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_127 ) , + .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_122 ) , + .X ( copt_net_127 ) ) ; endmodule @@ -42,17 +40,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_511_ ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_88 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( BUF_net_88 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_112 ( .A ( BUF_net_90 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_90 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -132,16 +130,13 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_85 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_85 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( BUF_net_85 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_87 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_87 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; endmodule @@ -222,15 +217,16 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_82 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_87 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_86 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_86 ( .A ( BUF_net_88 ) , .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_88 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_88 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -311,16 +307,14 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_508_ ) , - .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_84 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( BUF_net_81 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -400,16 +394,13 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_76 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( net_net_80 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_76 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_76 ( .A ( BUF_net_78 ) , .Y ( BUF_net_76 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_78 ) ) ; + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( SOC_DIR ) ) ; endmodule @@ -489,16 +480,19 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_73 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_507_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_73 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_73 ( .A ( BUF_net_75 ) , .Y ( BUF_net_73 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_75 ) ) ; + .TE_B ( BUF_net_77 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_77 ( .A ( BUF_net_79 ) , .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( BUF_net_78 ) , .Y ( BUF_net_107 ) ) ; endmodule @@ -568,7 +562,7 @@ endmodule module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_184_0 ) ; + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_211_0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -576,22 +570,22 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_211_0 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( ZBUF_184_0 ) , .Z ( SOC_OUT ) ) ; + .TE_B ( ZBUF_211_0 ) , .Z ( SOC_OUT ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , - iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_184_0 ) ; + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -601,7 +595,7 @@ input [0:0] iopad_outpad ; input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; wire [0:0] EMBEDDED_IO_HD_0_en ; @@ -611,7 +605,7 @@ cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , - .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .ZBUF_211_0 ( ZBUF_211_0 ) ) ; cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; @@ -621,7 +615,7 @@ endmodule module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , ZBUF_184_0 ) ; + ccff_tail , ZBUF_211_0 ) ; input [0:0] IO_ISOL_N ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; @@ -631,7 +625,7 @@ input [0:0] io_outpad ; input [0:0] ccff_head ; output [0:0] io_inpad ; output [0:0] ccff_tail ; -input ZBUF_184_0 ; +input ZBUF_211_0 ; cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , @@ -640,7 +634,7 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .ZBUF_184_0 ( ZBUF_184_0 ) ) ; + .ZBUF_211_0 ( ZBUF_211_0 ) ) ; endmodule @@ -668,16 +662,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_70 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_506_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_72 ) ) ; + .TE_B ( BUF_net_74 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_76 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_74 ( .A ( BUF_net_76 ) , .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -757,13 +752,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( net_net_69 ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__buf_8 BUFT_RR_69 ( .A ( net_net_69 ) , .X ( SOC_DIR ) ) ; + .TE_B ( BUF_net_70 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_72 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_70 ( .A ( BUF_net_72 ) , .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -978,7 +977,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_136 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -987,6 +986,20 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( ccff_head[0] ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_117 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_118 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_120 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_121 ) , + .X ( ropt_net_136 ) ) ; endmodule @@ -1114,6 +1127,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1143,8 +1158,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1195,9 +1208,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -1248,7 +1261,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1300,9 +1313,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -1353,9 +1366,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_96 ) ) ; endmodule @@ -1406,9 +1419,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1459,7 +1471,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1577,7 +1589,7 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1586,7 +1598,7 @@ cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1595,7 +1607,7 @@ cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1604,7 +1616,7 @@ cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -1613,7 +1625,7 @@ cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1622,7 +1634,7 @@ cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1631,7 +1643,7 @@ cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1640,7 +1652,7 @@ cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -1649,7 +1661,7 @@ cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1715,12 +1727,12 @@ cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_511_ } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_5_lower ) , .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , - .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; + .ZBUF_211_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , @@ -1775,10 +1787,10 @@ cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_17_lower ) , .ccff_tail ( ccff_tail ) ) ; -sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1117 ) ) ; + .X ( ctsbuf_net_1115 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -1888,15 +1900,15 @@ sky130_fd_sc_hd__buf_6 FTB_67__66 ( .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , - .HI ( optlc_net_116 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_211_inst_119 ( .A ( aps_rename_511_ ) , .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3521246 ( .A ( ctsbuf_net_1115 ) , .X ( prog_clk_0_W_out ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.top_only.pt.v index 42aaf98..55b6bb4 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.top_only.pt.v @@ -117,7 +117,7 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -126,7 +126,7 @@ cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -135,7 +135,7 @@ cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -144,7 +144,7 @@ cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -153,7 +153,7 @@ cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -162,7 +162,7 @@ cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -171,7 +171,7 @@ cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -180,7 +180,7 @@ cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_114 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_112 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -189,7 +189,7 @@ cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_115 ) ) ; + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -255,12 +255,12 @@ cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_511_ } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_5_lower ) , .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , - .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; + .ZBUF_211_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , @@ -315,10 +315,10 @@ cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , .io_inpad ( top_width_0_height_0__pin_17_lower ) , .ccff_tail ( ccff_tail ) ) ; -sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1117 ) ) ; + .X ( ctsbuf_net_1115 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -428,15 +428,15 @@ sky130_fd_sc_hd__buf_6 FTB_67__66 ( .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , - .HI ( optlc_net_116 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_211_inst_119 ( .A ( aps_rename_511_ ) , .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3521246 ( .A ( ctsbuf_net_1115 ) , .X ( prog_clk_0_W_out ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v index 4d1c581..ecfa1d5 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v @@ -13,11 +13,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -32,9 +32,9 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -72,7 +72,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -127,7 +127,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -293,8 +293,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -318,6 +316,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -371,7 +371,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -513,8 +513,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -538,6 +536,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -591,7 +591,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -603,29 +603,25 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -wire copt_net_81 ; +wire copt_net_84 ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_81 ) ) ; -sky130_fd_sc_hd__buf_4 FTB_8__7 ( .A ( copt_net_83 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_81 ) , - .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( mem_out[3] ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_84 ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_87 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , - .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_85 ) , + .X ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_84 ) , + .X ( copt_net_87 ) ) ; endmodule @@ -642,7 +638,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -750,7 +746,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_79 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_103 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -759,18 +755,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( ccff_head[0] ) , - .X ( copt_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_74 ) , - .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_75 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , .X ( copt_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_76 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( ccff_head[0] ) , .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_78 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1323 ( .A ( copt_net_81 ) , + .X ( ropt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1324 ( .A ( ropt_net_102 ) , + .X ( ropt_net_103 ) ) ; endmodule @@ -832,7 +832,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -866,8 +866,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -897,6 +895,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1348,7 +1348,6 @@ input clk_3_E_in ; output clk_3_E_out ; output clk_3_W_out ; -wire ropt_net_94 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -1408,7 +1407,7 @@ cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -1417,7 +1416,7 @@ cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1426,7 +1425,7 @@ cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -1444,7 +1443,7 @@ cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1462,7 +1461,7 @@ cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1499,9 +1498,8 @@ cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_100 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1509,7 +1507,7 @@ cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1517,7 +1515,7 @@ cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -1525,7 +1523,7 @@ cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -1533,7 +1531,7 @@ cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1541,7 +1539,7 @@ cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1557,7 +1555,7 @@ cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -1605,31 +1603,30 @@ cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_173 ) ) ; + .X ( ctsbuf_net_175 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( net_net_69 ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_70 ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_71 ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( clk_3_W_out ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , @@ -1713,34 +1710,29 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) , sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , .X ( REGOUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( prog_clk_1_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , - .Y ( prog_clk_1_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_67 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_69 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_70 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_71 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( net_net_69 ) , + .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( net_net_70 ) , .X ( clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , .HI ( optlc_net_72 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_73 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_79 ( .A ( aps_rename_507_ ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_506_ ) , + .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_175 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , - .X ( SC_OUT_TOP ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v index 3b5d288..1addeb6 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v @@ -18,11 +18,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -43,9 +43,9 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -95,7 +95,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -168,7 +168,7 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -333,9 +333,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -363,6 +360,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -414,7 +413,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -548,9 +547,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -578,6 +574,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -629,7 +627,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -643,33 +641,29 @@ output [0:3] mem_out ; input VDD ; input VSS ; -wire copt_net_81 ; +wire copt_net_84 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_81 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 FTB_8__7 ( .A ( copt_net_83 ) , .X ( ccff_tail[0] ) , +sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_81 ) , - .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( mem_out[3] ) , - .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_84 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_87 ) , .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , - .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_85 ) , + .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_84 ) , + .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -691,7 +685,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -835,7 +829,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_79 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_103 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -845,18 +839,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( ccff_head[0] ) , - .X ( copt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_74 ) , - .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_75 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_76 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( ccff_head[0] ) , .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_78 ) , + .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1323 ( .A ( copt_net_81 ) , + .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1324 ( .A ( ropt_net_102 ) , + .X ( ropt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -917,7 +915,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -945,9 +943,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -982,6 +977,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1433,7 +1430,6 @@ output clk_3_W_out ; input VDD ; input VSS ; -wire ropt_net_94 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -1497,7 +1493,7 @@ cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_71 ) ) ; + .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -1507,7 +1503,7 @@ cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_69 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1517,7 +1513,7 @@ cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_71 ) ) ; + .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -1537,7 +1533,7 @@ cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_70 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1557,7 +1553,7 @@ cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_70 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1594,9 +1590,9 @@ cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_100 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1605,7 +1601,7 @@ cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_71 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1614,7 +1610,7 @@ cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_69 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -1623,7 +1619,7 @@ cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_71 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -1632,7 +1628,7 @@ cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_69 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1641,7 +1637,7 @@ cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_70 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1659,7 +1655,7 @@ cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_70 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -1708,32 +1704,32 @@ cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( prog_clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( net_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_70 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) , +sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , @@ -1818,36 +1814,32 @@ sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) , +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , .X ( REGOUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( prog_clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , - .Y ( prog_clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( net_net_69 ) , + .X ( prog_clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( net_net_70 ) , .X ( clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( clk_2_E_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , .HI ( optlc_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_79 ( .A ( aps_rename_507_ ) , + .X ( clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_506_ ) , + .X ( clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_175 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , - .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v index 29bb84d..08f8f17 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v @@ -13,11 +13,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -32,9 +32,9 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -72,7 +72,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -127,7 +127,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -260,8 +260,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -285,6 +283,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -327,7 +327,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -436,8 +436,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -461,6 +459,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -503,7 +503,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -515,29 +515,25 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -wire copt_net_81 ; +wire copt_net_84 ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_81 ) ) ; -sky130_fd_sc_hd__buf_4 FTB_8__7 ( .A ( copt_net_83 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_81 ) , - .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( mem_out[3] ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_84 ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_87 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , - .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_85 ) , + .X ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_84 ) , + .X ( copt_net_87 ) ) ; endmodule @@ -554,7 +550,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -662,7 +658,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_79 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_103 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -671,18 +667,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( ccff_head[0] ) , - .X ( copt_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_74 ) , - .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_75 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , .X ( copt_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_76 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( ccff_head[0] ) , .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_78 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1323 ( .A ( copt_net_81 ) , + .X ( ropt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1324 ( .A ( ropt_net_102 ) , + .X ( ropt_net_103 ) ) ; endmodule @@ -733,7 +733,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -756,8 +756,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -787,6 +785,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1172,7 +1172,6 @@ input clk_3_E_in ; output clk_3_E_out ; output clk_3_W_out ; -wire ropt_net_94 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -1232,7 +1231,7 @@ cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -1241,7 +1240,7 @@ cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1250,7 +1249,7 @@ cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -1268,7 +1267,7 @@ cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1286,7 +1285,7 @@ cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1323,9 +1322,8 @@ cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_100 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1333,7 +1331,7 @@ cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1341,7 +1339,7 @@ cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -1349,7 +1347,7 @@ cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -1357,7 +1355,7 @@ cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1365,7 +1363,7 @@ cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1381,7 +1379,7 @@ cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -1429,31 +1427,30 @@ cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_173 ) ) ; + .X ( ctsbuf_net_175 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( net_net_69 ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_70 ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_71 ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( clk_3_W_out ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , @@ -1537,34 +1534,29 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) , sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , .X ( REGOUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( prog_clk_1_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , - .Y ( prog_clk_1_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_67 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_69 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_70 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_71 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( net_net_69 ) , + .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( net_net_70 ) , .X ( clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , .HI ( optlc_net_72 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_73 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_79 ( .A ( aps_rename_507_ ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_506_ ) , + .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_175 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , - .X ( SC_OUT_TOP ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.top_only.pt.v index 47a86f3..bccfb85 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.top_only.pt.v @@ -74,7 +74,6 @@ input clk_3_E_in ; output clk_3_E_out ; output clk_3_W_out ; -wire ropt_net_94 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -134,7 +133,7 @@ cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -143,7 +142,7 @@ cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -152,7 +151,7 @@ cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_74 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , @@ -170,7 +169,7 @@ cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -188,7 +187,7 @@ cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -225,9 +224,8 @@ cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_100 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -235,7 +233,7 @@ cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -243,7 +241,7 @@ cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -251,7 +249,7 @@ cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_71 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -259,7 +257,7 @@ cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_69 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -267,7 +265,7 @@ cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -283,7 +281,7 @@ cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_70 ) ) ; + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -331,31 +329,30 @@ cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_173 ) ) ; + .X ( ctsbuf_net_175 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( net_net_69 ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , - .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_70 ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) ) ; -sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_71 ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( clk_3_W_out ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , @@ -439,34 +436,29 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) , sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , .X ( REGOUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( prog_clk_1_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , - .Y ( prog_clk_1_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_67 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_69 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_70 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_71 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( net_net_69 ) , + .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( net_net_70 ) , .X ( clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , .HI ( optlc_net_72 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_73 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_79 ( .A ( aps_rename_507_ ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_506_ ) , + .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_175 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , - .X ( SC_OUT_TOP ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v index a37cd5b..d49f6ee 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v @@ -16,14 +16,14 @@ wire copt_net_86 ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( copt_net_86 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_88 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_84 ) , + .X ( copt_net_83 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , + .X ( copt_net_85 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1310 ( .A ( copt_net_84 ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_86 ) , - .X ( copt_net_88 ) ) ; endmodule @@ -39,15 +39,14 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_61 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_64 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_61 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_61 ( .A ( BUF_net_63 ) , .Y ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_63 ) ) ; + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_64 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -114,7 +113,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -447,6 +446,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -470,8 +471,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -635,7 +634,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -690,7 +689,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -706,7 +705,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -835,9 +834,9 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -854,7 +853,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_93 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_95 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -863,24 +862,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( ccff_head[0] ) , + .X ( copt_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_75 ) , + .X ( copt_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_78 ) , .X ( copt_net_79 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_79 ) , .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( copt_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_82 ) , - .X ( ropt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1315 ( .A ( ropt_net_92 ) , - .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_80 ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1314 ( .A ( ropt_net_94 ) , + .X ( ropt_net_95 ) ) ; endmodule @@ -942,7 +939,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1068,7 +1065,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1291,6 +1288,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1320,8 +1319,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1383,8 +1380,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -1555,7 +1553,7 @@ cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -1564,7 +1562,7 @@ cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1582,7 +1580,7 @@ cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -1591,7 +1589,7 @@ cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1609,7 +1607,7 @@ cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -1670,7 +1668,7 @@ cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1686,7 +1684,7 @@ cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , @@ -1702,7 +1700,7 @@ cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1710,7 +1708,7 @@ cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -1726,7 +1724,7 @@ cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -1778,10 +1776,10 @@ cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_176 ) ) ; + .X ( ctsbuf_net_174 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , +sky130_fd_sc_hd__buf_12 FTB_20__19 ( .A ( chanx_left_in[1] ) , .X ( chanx_right_out[1] ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , .X ( chanx_right_out[2] ) ) ; @@ -1823,7 +1821,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , .X ( chanx_left_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__buf_12 FTB_41__40 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; @@ -1868,11 +1866,7 @@ sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , .HI ( optlc_net_72 ) ) ; sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , .HI ( optlc_net_73 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_74 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521203 ( .A ( ctsbuf_net_174 ) , .X ( prog_clk_0_W_out ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v index 419d1f7..7417dde 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v @@ -22,14 +22,14 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_88 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_84 ) , + .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , + .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1310 ( .A ( copt_net_84 ) , - .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_86 ) , - .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51,18 +51,16 @@ supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_61 ) , .Y ( SOC_DIR_N ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .TE_B ( BUF_net_64 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_61 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_61 ( .A ( BUF_net_63 ) , .Y ( BUF_net_61 ) , + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_64 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -146,7 +144,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -512,6 +510,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -539,8 +540,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -700,7 +699,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -753,7 +752,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -774,7 +773,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -945,9 +944,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -970,7 +969,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_93 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_95 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -980,24 +979,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( ccff_head[0] ) , + .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_75 ) , + .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_78 ) , .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_79 ) , .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_82 ) , - .X ( ropt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1315 ( .A ( ropt_net_92 ) , - .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_80 ) , + .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1314 ( .A ( ropt_net_94 ) , + .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1058,7 +1055,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1183,7 +1180,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1400,6 +1397,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1434,8 +1434,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1496,8 +1494,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1674,7 +1674,7 @@ cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -1684,7 +1684,7 @@ cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1704,7 +1704,7 @@ cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -1714,7 +1714,7 @@ cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1734,7 +1734,7 @@ cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -1797,7 +1797,7 @@ cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1815,7 +1815,7 @@ cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , @@ -1833,7 +1833,7 @@ cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1842,7 +1842,7 @@ cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -1860,7 +1860,7 @@ cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; + .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -1912,10 +1912,10 @@ cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , +sky130_fd_sc_hd__buf_12 FTB_20__19 ( .A ( chanx_left_in[1] ) , .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1957,7 +1957,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__buf_12 FTB_41__40 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2005,11 +2005,7 @@ sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , .HI ( optlc_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , .HI ( optlc_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521203 ( .A ( ctsbuf_net_174 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v index d10e082..e530502 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v @@ -16,14 +16,14 @@ wire copt_net_86 ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( copt_net_86 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_88 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_84 ) , + .X ( copt_net_83 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , + .X ( copt_net_85 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_85 ) , .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1310 ( .A ( copt_net_84 ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_86 ) , - .X ( copt_net_88 ) ) ; endmodule @@ -39,15 +39,14 @@ input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_61 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_64 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_61 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_61 ( .A ( BUF_net_63 ) , .Y ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_63 ) ) ; + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_64 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -114,7 +113,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -403,6 +402,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -426,8 +427,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -558,7 +557,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -602,7 +601,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -618,7 +617,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -747,9 +746,9 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -766,7 +765,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_93 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_95 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -775,24 +774,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_79 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( ccff_head[0] ) , + .X ( copt_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_75 ) , + .X ( copt_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_78 ) , .X ( copt_net_79 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_77 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_79 ) , .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_80 ) , - .X ( copt_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_82 ) , - .X ( ropt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1315 ( .A ( ropt_net_92 ) , - .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1313 ( .A ( copt_net_80 ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1314 ( .A ( ropt_net_94 ) , + .X ( ropt_net_95 ) ) ; endmodule @@ -843,7 +840,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -947,7 +944,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1126,6 +1123,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1155,8 +1154,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1207,8 +1204,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -1368,7 +1366,7 @@ cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -1377,7 +1375,7 @@ cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -1395,7 +1393,7 @@ cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -1404,7 +1402,7 @@ cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -1422,7 +1420,7 @@ cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -1483,7 +1481,7 @@ cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1499,7 +1497,7 @@ cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , @@ -1515,7 +1513,7 @@ cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -1523,7 +1521,7 @@ cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -1539,7 +1537,7 @@ cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -1591,10 +1589,10 @@ cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_176 ) ) ; + .X ( ctsbuf_net_174 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , +sky130_fd_sc_hd__buf_12 FTB_20__19 ( .A ( chanx_left_in[1] ) , .X ( chanx_right_out[1] ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , .X ( chanx_right_out[2] ) ) ; @@ -1636,7 +1634,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , .X ( chanx_left_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__buf_12 FTB_41__40 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; @@ -1681,11 +1679,7 @@ sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , .HI ( optlc_net_72 ) ) ; sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , .HI ( optlc_net_73 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_74 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521203 ( .A ( ctsbuf_net_174 ) , .X ( prog_clk_0_W_out ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.top_only.pt.v index 16552ea..9eeb69f 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.top_only.pt.v @@ -108,7 +108,7 @@ cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -117,7 +117,7 @@ cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , @@ -135,7 +135,7 @@ cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -144,7 +144,7 @@ cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , @@ -162,7 +162,7 @@ cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , @@ -223,7 +223,7 @@ cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -239,7 +239,7 @@ cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , @@ -255,7 +255,7 @@ cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , @@ -263,7 +263,7 @@ cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , @@ -279,7 +279,7 @@ cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_74 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -331,10 +331,10 @@ cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_176 ) ) ; + .X ( ctsbuf_net_174 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , +sky130_fd_sc_hd__buf_12 FTB_20__19 ( .A ( chanx_left_in[1] ) , .X ( chanx_right_out[1] ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , .X ( chanx_right_out[2] ) ) ; @@ -376,7 +376,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , .X ( chanx_left_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__buf_12 FTB_41__40 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; @@ -421,11 +421,7 @@ sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , .HI ( optlc_net_72 ) ) ; sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , .HI ( optlc_net_73 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_74 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521203 ( .A ( ctsbuf_net_174 ) , .X ( prog_clk_0_W_out ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v index 975243f..73414a1 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v @@ -11,23 +11,23 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_55 ; +wire copt_net_60 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , - .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_60 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_60 ) , + .X ( copt_net_55 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( copt_net_55 ) , .X ( copt_net_56 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_56 ) , .X ( copt_net_57 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , .X ( copt_net_58 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , - .X ( copt_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , - .X ( copt_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_61 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1193 ( .A ( copt_net_58 ) , + .X ( copt_net_61 ) ) ; endmodule @@ -123,17 +123,17 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( ccff_head[0] ) , .X ( copt_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_49 ) , .X ( copt_net_50 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_50 ) , .X ( copt_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( copt_net_51 ) , .X ( copt_net_52 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_52 ) , .X ( copt_net_53 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_53 ) , .X ( copt_net_54 ) ) ; endmodule @@ -224,10 +224,14 @@ output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; input prog_clk_0_E_in ; -wire ropt_net_73 ; -wire ropt_net_75 ; -wire ropt_net_74 ; -wire ropt_net_72 ; +wire ropt_net_67 ; +wire ropt_net_68 ; +wire ropt_net_66 ; +wire ropt_net_65 ; +wire ropt_net_63 ; +wire ropt_net_69 ; +wire ropt_net_64 ; +wire ropt_net_62 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -270,12 +274,12 @@ sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , +sky130_fd_sc_hd__buf_6 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_73 ) ) ; + .X ( ropt_net_67 ) ) ; sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_75 ) ) ; + .X ( ropt_net_68 ) ) ; sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , @@ -283,18 +287,18 @@ sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; + .X ( ropt_net_66 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_65 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_63 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__buf_6 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; @@ -305,7 +309,7 @@ sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_74 ) ) ; + .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , @@ -321,10 +325,10 @@ sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_69 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_64 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[13] ) ) ; sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) ) ; @@ -335,7 +339,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_72 ) ) ; + .X ( ropt_net_62 ) ) ; sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_43__42 ( @@ -343,14 +347,22 @@ sky130_fd_sc_hd__buf_6 FTB_43__42 ( .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_48 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1194 ( .A ( ropt_net_62 ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1195 ( .A ( ropt_net_63 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1196 ( .A ( ropt_net_64 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1197 ( .A ( ropt_net_65 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1198 ( .A ( ropt_net_66 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1199 ( .A ( ropt_net_67 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1200 ( .A ( ropt_net_68 ) , .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1201 ( .A ( ropt_net_69 ) , + .X ( chany_bottom_out[11] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v index 93eaeb1..43e4616 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v @@ -13,27 +13,27 @@ output [0:0] mem_out ; input VDD ; input VSS ; -wire copt_net_55 ; +wire copt_net_60 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) , +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , - .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_60 ) , + .X ( copt_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( copt_net_55 ) , .X ( copt_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_56 ) , .X ( copt_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , .X ( copt_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , - .X ( copt_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , - .X ( copt_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_61 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1193 ( .A ( copt_net_58 ) , + .X ( copt_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -156,17 +156,17 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( ccff_head[0] ) , .X ( copt_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_49 ) , .X ( copt_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_50 ) , .X ( copt_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( copt_net_51 ) , .X ( copt_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_52 ) , .X ( copt_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_53 ) , .X ( copt_net_54 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -259,10 +259,14 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; -wire ropt_net_73 ; -wire ropt_net_75 ; -wire ropt_net_74 ; -wire ropt_net_72 ; +wire ropt_net_67 ; +wire ropt_net_68 ; +wire ropt_net_66 ; +wire ropt_net_65 ; +wire ropt_net_63 ; +wire ropt_net_69 ; +wire ropt_net_64 ; +wire ropt_net_62 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -308,12 +312,12 @@ sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , +sky130_fd_sc_hd__buf_6 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , @@ -321,18 +325,18 @@ sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__buf_6 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -343,7 +347,7 @@ sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , @@ -359,10 +363,10 @@ sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -373,7 +377,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_43__42 ( @@ -382,14 +386,22 @@ sky130_fd_sc_hd__buf_6 FTB_43__42 ( .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1194 ( .A ( ropt_net_62 ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1195 ( .A ( ropt_net_63 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1196 ( .A ( ropt_net_64 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1197 ( .A ( ropt_net_65 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1198 ( .A ( ropt_net_66 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1199 ( .A ( ropt_net_67 ) , .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1200 ( .A ( ropt_net_68 ) , .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1201 ( .A ( ropt_net_69 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v index 0b8883f..80e835e 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v @@ -11,23 +11,23 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_55 ; +wire copt_net_60 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , - .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_60 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_60 ) , + .X ( copt_net_55 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( copt_net_55 ) , .X ( copt_net_56 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_56 ) , .X ( copt_net_57 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , .X ( copt_net_58 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , - .X ( copt_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , - .X ( copt_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_61 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1193 ( .A ( copt_net_58 ) , + .X ( copt_net_61 ) ) ; endmodule @@ -123,17 +123,17 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( ccff_head[0] ) , .X ( copt_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_49 ) , .X ( copt_net_50 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_50 ) , .X ( copt_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( copt_net_51 ) , .X ( copt_net_52 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_52 ) , .X ( copt_net_53 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_53 ) , .X ( copt_net_54 ) ) ; endmodule @@ -213,10 +213,14 @@ output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; input prog_clk_0_E_in ; -wire ropt_net_73 ; -wire ropt_net_75 ; -wire ropt_net_74 ; -wire ropt_net_72 ; +wire ropt_net_67 ; +wire ropt_net_68 ; +wire ropt_net_66 ; +wire ropt_net_65 ; +wire ropt_net_63 ; +wire ropt_net_69 ; +wire ropt_net_64 ; +wire ropt_net_62 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -259,12 +263,12 @@ sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , +sky130_fd_sc_hd__buf_6 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_73 ) ) ; + .X ( ropt_net_67 ) ) ; sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_75 ) ) ; + .X ( ropt_net_68 ) ) ; sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , @@ -272,18 +276,18 @@ sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; + .X ( ropt_net_66 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_65 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_63 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__buf_6 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; @@ -294,7 +298,7 @@ sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_74 ) ) ; + .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , @@ -310,10 +314,10 @@ sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_69 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_64 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[13] ) ) ; sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) ) ; @@ -324,7 +328,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_72 ) ) ; + .X ( ropt_net_62 ) ) ; sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_43__42 ( @@ -332,14 +336,22 @@ sky130_fd_sc_hd__buf_6 FTB_43__42 ( .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_48 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1194 ( .A ( ropt_net_62 ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1195 ( .A ( ropt_net_63 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1196 ( .A ( ropt_net_64 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1197 ( .A ( ropt_net_65 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1198 ( .A ( ropt_net_66 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1199 ( .A ( ropt_net_67 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1200 ( .A ( ropt_net_68 ) , .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1201 ( .A ( ropt_net_69 ) , + .X ( chany_bottom_out[11] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.top_only.pt.v index 3d69c25..4ed9ae1 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.top_only.pt.v @@ -26,10 +26,14 @@ output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; input prog_clk_0_E_in ; -wire ropt_net_73 ; -wire ropt_net_75 ; -wire ropt_net_74 ; -wire ropt_net_72 ; +wire ropt_net_67 ; +wire ropt_net_68 ; +wire ropt_net_66 ; +wire ropt_net_65 ; +wire ropt_net_63 ; +wire ropt_net_69 ; +wire ropt_net_64 ; +wire ropt_net_62 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -72,12 +76,12 @@ sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , +sky130_fd_sc_hd__buf_6 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_73 ) ) ; + .X ( ropt_net_67 ) ) ; sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_75 ) ) ; + .X ( ropt_net_68 ) ) ; sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , @@ -85,18 +89,18 @@ sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; + .X ( ropt_net_66 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_65 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_63 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__buf_6 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; @@ -107,7 +111,7 @@ sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_74 ) ) ; + .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , @@ -123,10 +127,10 @@ sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_69 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_64 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[13] ) ) ; sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) ) ; @@ -137,7 +141,7 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_72 ) ) ; + .X ( ropt_net_62 ) ) ; sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_43__42 ( @@ -145,14 +149,22 @@ sky130_fd_sc_hd__buf_6 FTB_43__42 ( .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_48 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1194 ( .A ( ropt_net_62 ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1195 ( .A ( ropt_net_63 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1196 ( .A ( ropt_net_64 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1197 ( .A ( ropt_net_65 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1198 ( .A ( ropt_net_66 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1199 ( .A ( ropt_net_67 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1200 ( .A ( ropt_net_68 ) , .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1201 ( .A ( ropt_net_69 ) , + .X ( chany_bottom_out[11] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v index 3a8570c..e028a82 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v @@ -11,13 +11,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -34,9 +34,9 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -68,13 +68,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -87,11 +87,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -106,7 +106,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -125,7 +125,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -148,7 +148,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -183,6 +183,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -206,8 +208,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -238,8 +238,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -263,6 +261,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -371,8 +371,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -403,8 +404,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -428,6 +427,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -568,8 +569,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -593,6 +592,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -603,15 +604,29 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +wire copt_net_84 ; + +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_84 ) , + .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1316 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1317 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_81 ) , + .X ( copt_net_82 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_82 ) , + .X ( copt_net_83 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_83 ) , + .X ( mem_out[3] ) ) ; endmodule @@ -622,7 +637,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -643,7 +658,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -660,13 +675,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -679,13 +694,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -698,11 +713,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -717,13 +732,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -736,35 +751,25 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_100 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_91 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( ccff_head[0] ) , - .X ( copt_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1314 ( .A ( copt_net_82 ) , - .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_83 ) , - .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1324 ( .A ( copt_net_85 ) , - .X ( copt_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1334 ( .A ( ropt_net_97 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1335 ( .A ( ropt_net_98 ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1336 ( .A ( copt_net_86 ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1339 ( .A ( ropt_net_96 ) , - .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( ropt_net_88 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_92 ) , + .X ( ropt_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_88 ) , + .X ( ropt_net_90 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1362 ( .A ( ropt_net_89 ) , + .X ( ropt_net_91 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1363 ( .A ( ropt_net_90 ) , + .X ( ropt_net_92 ) ) ; endmodule @@ -797,6 +802,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cby_1__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -826,9 +833,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_75 ) ) ; endmodule @@ -1079,8 +1083,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_59 ) ) ; endmodule @@ -1268,8 +1273,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_57 ) ) ; endmodule @@ -1384,7 +1390,7 @@ cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1393,7 +1399,7 @@ cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1402,7 +1408,7 @@ cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1411,7 +1417,7 @@ cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -1420,7 +1426,7 @@ cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1484,9 +1490,8 @@ cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { copt_net_87 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1502,7 +1507,7 @@ cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1518,7 +1523,7 @@ cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1526,7 +1531,7 @@ cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1534,7 +1539,7 @@ cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1550,7 +1555,7 @@ cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1593,31 +1598,32 @@ cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , - .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_W_out ) ) ; sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , - .X ( net_net_67 ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( net_net_68 ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) ) ; + .X ( ctsbuf_net_177 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) ) ; + .X ( ctsbuf_net_278 ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ropt_net_93 ) ) ; + .X ( ropt_net_87 ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ZBUF_6_f_1 ) ) ; + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( prog_clk_3_N_out ) ) ; + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( ropt_net_95 ) ) ; + .X ( prog_clk_3_S_out ) ) ; sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , .X ( clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) ) ; -sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , - .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_509_ ) ) ; sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_506_ ) ) ; + .X ( aps_rename_510_ ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , @@ -1698,43 +1704,31 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_66 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( clk_3_S_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_75 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , - .X ( clk_2_N_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , - .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , - .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , - .X ( prog_clk_2_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_509_ ) , .X ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , - .X ( copt_net_92 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_585 ( .A ( aps_rename_508_ ) , + .X ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_586 ( .A ( aps_rename_507_ ) , + .X ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_587 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1358 ( .A ( ropt_net_87 ) , .X ( prog_clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , - .X ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , - .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_177 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_278 ) , + .X ( prog_clk_0_N_out ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v index 940d0a2..e3ccbc6 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v @@ -16,13 +16,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -45,9 +45,9 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -91,13 +91,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -116,11 +116,11 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -141,7 +141,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -166,7 +166,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -195,7 +195,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -225,59 +225,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -311,6 +258,59 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; @@ -413,8 +413,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -439,9 +441,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -469,6 +468,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -601,9 +602,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -631,6 +629,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -643,19 +643,33 @@ output [0:3] mem_out ; input VDD ; input VSS ; +wire copt_net_84 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_84 ) , + .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1316 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1317 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_81 ) , + .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_82 ) , + .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_83 ) , + .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -671,7 +685,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -698,7 +712,7 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -721,13 +735,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -746,13 +760,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -771,11 +785,11 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -796,13 +810,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -821,36 +835,26 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_100 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_91 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( ccff_head[0] ) , - .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1314 ( .A ( copt_net_82 ) , - .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_83 ) , - .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1324 ( .A ( copt_net_85 ) , - .X ( copt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1334 ( .A ( ropt_net_97 ) , - .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1335 ( .A ( ropt_net_98 ) , - .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1336 ( .A ( copt_net_86 ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1339 ( .A ( ropt_net_96 ) , - .X ( ropt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( ropt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_92 ) , + .X ( ropt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_88 ) , + .X ( ropt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1362 ( .A ( ropt_net_89 ) , + .X ( ropt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1363 ( .A ( ropt_net_90 ) , + .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -877,6 +881,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -911,10 +918,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1163,8 +1166,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1351,8 +1356,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1472,7 +1479,7 @@ cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1482,7 +1489,7 @@ cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1492,7 +1499,7 @@ cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1502,7 +1509,7 @@ cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -1512,7 +1519,7 @@ cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1579,9 +1586,9 @@ cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { copt_net_87 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1599,7 +1606,7 @@ cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1617,7 +1624,7 @@ cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1626,7 +1633,7 @@ cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1635,7 +1642,7 @@ cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1653,7 +1660,7 @@ cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1696,32 +1703,32 @@ cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , - .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , - .X ( net_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( net_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_278 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ZBUF_6_f_1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( prog_clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , .X ( clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , - .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , @@ -1802,46 +1809,34 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) , +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) , +sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , - .X ( clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , - .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , - .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , - .X ( prog_clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_509_ ) , .X ( clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , - .X ( copt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_585 ( .A ( aps_rename_508_ ) , + .X ( clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_586 ( .A ( aps_rename_507_ ) , + .X ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_587 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1358 ( .A ( ropt_net_87 ) , .X ( prog_clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , - .X ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , - .X ( prog_clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_177 ) , + .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_278 ) , + .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v index 82186fb..9241c81 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v @@ -11,13 +11,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -34,9 +34,9 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -68,13 +68,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -87,11 +87,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -106,7 +106,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -125,7 +125,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -148,7 +148,7 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -172,50 +172,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -244,6 +200,50 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -327,8 +327,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -348,8 +349,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -373,6 +372,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -480,8 +481,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -505,6 +504,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -515,15 +516,29 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +wire copt_net_84 ; + +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_84 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_84 ) , + .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1316 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1317 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_81 ) , + .X ( copt_net_82 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_82 ) , + .X ( copt_net_83 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_83 ) , + .X ( mem_out[3] ) ) ; endmodule @@ -534,7 +549,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -555,7 +570,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -572,13 +587,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -591,13 +606,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -610,11 +625,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -629,13 +644,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -648,35 +663,25 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_100 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_91 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( ccff_head[0] ) , - .X ( copt_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_81 ) , - .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1314 ( .A ( copt_net_82 ) , - .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1315 ( .A ( copt_net_83 ) , - .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1324 ( .A ( copt_net_85 ) , - .X ( copt_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1334 ( .A ( ropt_net_97 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1335 ( .A ( ropt_net_98 ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1336 ( .A ( copt_net_86 ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1339 ( .A ( ropt_net_96 ) , - .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( ropt_net_88 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_92 ) , + .X ( ropt_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_88 ) , + .X ( ropt_net_90 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1362 ( .A ( ropt_net_89 ) , + .X ( ropt_net_91 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1363 ( .A ( ropt_net_90 ) , + .X ( ropt_net_92 ) ) ; endmodule @@ -698,6 +703,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -727,9 +734,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_75 ) ) ; endmodule @@ -936,8 +940,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_59 ) ) ; endmodule @@ -1092,8 +1097,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_57 ) ) ; endmodule @@ -1208,7 +1214,7 @@ cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1217,7 +1223,7 @@ cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1226,7 +1232,7 @@ cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1235,7 +1241,7 @@ cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -1244,7 +1250,7 @@ cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1308,9 +1314,8 @@ cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { copt_net_87 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1326,7 +1331,7 @@ cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1342,7 +1347,7 @@ cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1350,7 +1355,7 @@ cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1358,7 +1363,7 @@ cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1374,7 +1379,7 @@ cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1417,31 +1422,32 @@ cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , - .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_W_out ) ) ; sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , - .X ( net_net_67 ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( net_net_68 ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) ) ; + .X ( ctsbuf_net_177 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) ) ; + .X ( ctsbuf_net_278 ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ropt_net_93 ) ) ; + .X ( ropt_net_87 ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ZBUF_6_f_1 ) ) ; + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( prog_clk_3_N_out ) ) ; + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( ropt_net_95 ) ) ; + .X ( prog_clk_3_S_out ) ) ; sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , .X ( clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) ) ; -sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , - .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_509_ ) ) ; sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_506_ ) ) ; + .X ( aps_rename_510_ ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , @@ -1522,43 +1528,31 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_66 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( clk_3_S_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_75 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , - .X ( clk_2_N_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , - .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , - .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , - .X ( prog_clk_2_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_509_ ) , .X ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , - .X ( copt_net_92 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_585 ( .A ( aps_rename_508_ ) , + .X ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_586 ( .A ( aps_rename_507_ ) , + .X ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_587 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1358 ( .A ( ropt_net_87 ) , .X ( prog_clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , - .X ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , - .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_177 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_278 ) , + .X ( prog_clk_0_N_out ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.top_only.pt.v index 0eff2e7..23397cd 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.top_only.pt.v @@ -115,7 +115,7 @@ cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -124,7 +124,7 @@ cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -133,7 +133,7 @@ cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -142,7 +142,7 @@ cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -151,7 +151,7 @@ cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -215,9 +215,8 @@ cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { copt_net_87 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -233,7 +232,7 @@ cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -249,7 +248,7 @@ cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -257,7 +256,7 @@ cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -265,7 +264,7 @@ cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_76 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -281,7 +280,7 @@ cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -324,31 +323,32 @@ cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , - .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_W_out ) ) ; sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , - .X ( net_net_67 ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( net_net_68 ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) ) ; + .X ( ctsbuf_net_177 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) ) ; + .X ( ctsbuf_net_278 ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ropt_net_93 ) ) ; + .X ( ropt_net_87 ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( ZBUF_6_f_1 ) ) ; + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( prog_clk_3_N_out ) ) ; + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( ropt_net_95 ) ) ; + .X ( prog_clk_3_S_out ) ) ; sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , .X ( clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) ) ; -sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , - .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_509_ ) ) ; sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_506_ ) ) ; + .X ( aps_rename_510_ ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , @@ -429,43 +429,31 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_66 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( clk_3_S_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_75 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , - .X ( clk_2_N_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , - .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , - .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , - .X ( prog_clk_2_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_509_ ) , .X ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , - .X ( copt_net_92 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_585 ( .A ( aps_rename_508_ ) , + .X ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_586 ( .A ( aps_rename_507_ ) , + .X ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_587 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1358 ( .A ( ropt_net_87 ) , .X ( prog_clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , - .X ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , - .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_177 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_278 ) , + .X ( prog_clk_0_N_out ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v index c542fbf..b8aa8cb 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v @@ -11,12 +11,19 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; +wire copt_net_88 ; + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( copt_net_90 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( mem_out[0] ) , - .X ( copt_net_90 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_88 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_89 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_88 ) , + .X ( copt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_86 ) , + .X ( copt_net_87 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_87 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1311 ( .A ( mem_out[0] ) , + .X ( copt_net_89 ) ) ; endmodule @@ -30,17 +37,17 @@ input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , - .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_59 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_60 ) ) ; + .TE_B ( BUF_net_59 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_59 ( .A ( BUF_net_61 ) , .Y ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_61 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -105,11 +112,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -122,11 +129,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -143,7 +150,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -181,11 +188,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -198,13 +205,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -219,11 +226,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -236,13 +243,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -440,6 +447,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_2__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -463,8 +472,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -495,8 +502,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_2__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -520,6 +525,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -697,11 +704,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -714,13 +721,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -752,13 +759,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -773,11 +780,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -796,7 +803,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -809,13 +816,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -828,13 +835,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -847,31 +854,33 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_92 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_86 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ropt_net_94 ) , + .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( ccff_head[0] ) , .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1305 ( .A ( copt_net_85 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1308 ( .A ( ccff_head[0] ) , - .X ( copt_net_86 ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1309 ( .A ( copt_net_82 ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_83 ) , - .X ( copt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1311 ( .A ( copt_net_88 ) , - .X ( copt_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( copt_net_84 ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_82 ) , + .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_93 ) , + .X ( ropt_net_94 ) ) ; endmodule @@ -967,6 +976,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cby_2__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -996,9 +1007,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_67 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; endmodule @@ -1060,9 +1068,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_67 ) ) ; endmodule @@ -1187,9 +1195,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_65 ) ) ; endmodule @@ -1251,7 +1259,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1348,8 +1356,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cby_2__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1379,6 +1385,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1537,7 +1545,7 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1546,7 +1554,7 @@ cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1555,7 +1563,7 @@ cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1564,7 +1572,7 @@ cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -1573,7 +1581,7 @@ cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1582,7 +1590,7 @@ cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1591,7 +1599,7 @@ cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1600,7 +1608,7 @@ cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1609,7 +1617,7 @@ cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1661,7 +1669,7 @@ cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1669,7 +1677,7 @@ cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1677,7 +1685,7 @@ cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1685,7 +1693,7 @@ cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1693,7 +1701,7 @@ cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1701,7 +1709,7 @@ cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1709,7 +1717,7 @@ cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1717,7 +1725,7 @@ cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -1765,14 +1773,14 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( { ropt_net_91 } ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) ) ; + .X ( ctsbuf_net_177 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) ) ; + .X ( ctsbuf_net_278 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , @@ -1856,22 +1864,18 @@ sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) , sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( left_width_0_height_0__pin_1_lower[0] ) , .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_73 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3471203 ( .A ( ctsbuf_net_177 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521208 ( .A ( ctsbuf_net_278 ) , .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v index 0959695..8c06629 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v @@ -13,15 +13,23 @@ output [0:0] mem_out ; input VDD ; input VSS ; +wire copt_net_88 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( copt_net_90 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( mem_out[0] ) , - .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_88 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_89 ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_88 ) , + .X ( copt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_86 ) , + .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_87 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1311 ( .A ( mem_out[0] ) , + .X ( copt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40,19 +48,21 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , - .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_59 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( SOC_DIR ) , + .TE_B ( BUF_net_59 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_59 ( .A ( BUF_net_61 ) , .Y ( BUF_net_59 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_61 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -134,11 +144,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -157,11 +167,11 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -184,7 +194,7 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -234,11 +244,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -257,13 +267,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -284,11 +294,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -307,13 +317,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -503,59 +513,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -589,6 +546,59 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; @@ -764,11 +774,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -787,13 +797,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -837,13 +847,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -864,11 +874,11 @@ supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -893,7 +903,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -912,13 +922,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -937,13 +947,13 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -962,32 +972,34 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_92 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_86 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ropt_net_94 ) , + .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( ccff_head[0] ) , .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1305 ( .A ( copt_net_85 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1308 ( .A ( ccff_head[0] ) , - .X ( copt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1309 ( .A ( copt_net_82 ) , - .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_83 ) , - .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1311 ( .A ( copt_net_88 ) , - .X ( copt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( copt_net_84 ) , + .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_82 ) , + .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_93 ) , + .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1076,6 +1088,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1110,10 +1125,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1174,10 +1185,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1301,10 +1312,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1365,7 +1376,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1456,9 +1467,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1493,6 +1501,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1656,7 +1666,7 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1666,7 +1676,7 @@ cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1676,7 +1686,7 @@ cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1686,7 +1696,7 @@ cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -1696,7 +1706,7 @@ cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1706,7 +1716,7 @@ cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1716,7 +1726,7 @@ cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1726,7 +1736,7 @@ cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1736,7 +1746,7 @@ cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1789,7 +1799,7 @@ cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1798,7 +1808,7 @@ cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1807,7 +1817,7 @@ cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1816,7 +1826,7 @@ cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1825,7 +1835,7 @@ cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1834,7 +1844,7 @@ cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1843,7 +1853,7 @@ cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1852,7 +1862,7 @@ cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; + .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -1900,15 +1910,14 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( { ropt_net_91 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_278 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , @@ -1993,22 +2002,18 @@ sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( left_width_0_height_0__pin_1_lower[0] ) , .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3471203 ( .A ( ctsbuf_net_177 ) , .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521208 ( .A ( ctsbuf_net_278 ) , .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v index 8698628..1968373 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v @@ -11,12 +11,19 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; +wire copt_net_88 ; + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( copt_net_90 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( mem_out[0] ) , - .X ( copt_net_90 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_88 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_89 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1308 ( .A ( copt_net_88 ) , + .X ( copt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1309 ( .A ( copt_net_86 ) , + .X ( copt_net_87 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_87 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1311 ( .A ( mem_out[0] ) , + .X ( copt_net_89 ) ) ; endmodule @@ -30,17 +37,17 @@ input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , - .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_59 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_60 ) ) ; + .TE_B ( BUF_net_59 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_59 ( .A ( BUF_net_61 ) , .Y ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_61 ) , .Y ( SOC_DIR ) ) ; endmodule @@ -105,11 +112,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -122,11 +129,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; @@ -143,7 +150,7 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; @@ -181,11 +188,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -198,13 +205,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -219,11 +226,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -236,13 +243,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -396,50 +403,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -468,6 +431,50 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -609,11 +616,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -626,13 +633,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -664,13 +671,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -685,11 +692,11 @@ output [0:3] mem_out ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -708,7 +715,7 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -721,13 +728,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -740,13 +747,13 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -759,31 +766,33 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_92 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_86 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ropt_net_94 ) , + .X ( copt_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_79 ) , + .X ( copt_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_80 ) , + .X ( copt_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( ccff_head[0] ) , .X ( copt_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1305 ( .A ( copt_net_85 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_83 ) , .X ( copt_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_84 ) , - .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1308 ( .A ( ccff_head[0] ) , - .X ( copt_net_86 ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1309 ( .A ( copt_net_82 ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1310 ( .A ( copt_net_83 ) , - .X ( copt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1311 ( .A ( copt_net_88 ) , - .X ( copt_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1314 ( .A ( copt_net_84 ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_82 ) , + .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_93 ) , + .X ( ropt_net_94 ) ) ; endmodule @@ -857,6 +866,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -886,9 +897,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_67 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; endmodule @@ -939,9 +947,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_67 ) ) ; endmodule @@ -1044,9 +1052,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_65 ) ) ; endmodule @@ -1097,7 +1105,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1172,8 +1180,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1203,6 +1209,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1350,7 +1358,7 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1359,7 +1367,7 @@ cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1368,7 +1376,7 @@ cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -1377,7 +1385,7 @@ cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -1386,7 +1394,7 @@ cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1395,7 +1403,7 @@ cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1404,7 +1412,7 @@ cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1413,7 +1421,7 @@ cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -1422,7 +1430,7 @@ cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1474,7 +1482,7 @@ cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1482,7 +1490,7 @@ cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1490,7 +1498,7 @@ cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1498,7 +1506,7 @@ cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -1506,7 +1514,7 @@ cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -1514,7 +1522,7 @@ cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -1522,7 +1530,7 @@ cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -1530,7 +1538,7 @@ cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -1578,14 +1586,14 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( { ropt_net_91 } ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) ) ; + .X ( ctsbuf_net_177 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) ) ; + .X ( ctsbuf_net_278 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , @@ -1669,22 +1677,18 @@ sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) , sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( left_width_0_height_0__pin_1_lower[0] ) , .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_73 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3471203 ( .A ( ctsbuf_net_177 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521208 ( .A ( ctsbuf_net_278 ) , .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.top_only.pt.v index 45184b1..c05417c 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.top_only.pt.v @@ -96,7 +96,7 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -105,7 +105,7 @@ cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -114,7 +114,7 @@ cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , @@ -123,7 +123,7 @@ cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , @@ -132,7 +132,7 @@ cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -141,7 +141,7 @@ cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -150,7 +150,7 @@ cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -159,7 +159,7 @@ cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_75 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , @@ -168,7 +168,7 @@ cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -220,7 +220,7 @@ cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -228,7 +228,7 @@ cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -236,7 +236,7 @@ cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_78 ) ) ; + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -244,7 +244,7 @@ cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , @@ -252,7 +252,7 @@ cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , @@ -260,7 +260,7 @@ cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_77 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , @@ -268,7 +268,7 @@ cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 ( .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ; + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_74 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , @@ -276,7 +276,7 @@ cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_73 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -324,14 +324,14 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( { ropt_net_91 } ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_179 ) ) ; + .X ( ctsbuf_net_177 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_280 ) ) ; + .X ( ctsbuf_net_278 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , @@ -415,22 +415,18 @@ sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) , sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( left_width_0_height_0__pin_1_lower[0] ) , .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_73 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3471203 ( .A ( ctsbuf_net_177 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3521208 ( .A ( ctsbuf_net_278 ) , .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , - .X ( ropt_net_92 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v index 2d0391a..386b068 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v @@ -64,9 +64,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -206,8 +206,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_0__0__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -222,6 +220,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -348,9 +349,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -361,14 +362,14 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; +wire copt_net_92 ; + sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_91 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1251 ( .A ( mem_out[1] ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_87 ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_92 ) , .X ( copt_net_88 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_88 ) , .X ( copt_net_89 ) ) ; @@ -376,6 +377,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_89 ) , .X ( copt_net_90 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_90 ) , .X ( copt_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1256 ( .A ( copt_net_91 ) , + .X ( mem_out[1] ) ) ; endmodule @@ -626,27 +629,27 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_137 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1244 ( .A ( ccff_head[0] ) , - .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( copt_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( ccff_head[0] ) , .X ( copt_net_81 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1246 ( .A ( copt_net_85 ) , .X ( copt_net_82 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1247 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1249 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( copt_net_84 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1280 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( copt_net_82 ) , + .X ( copt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( copt_net_84 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1301 ( .A ( ropt_net_136 ) , + .X ( ropt_net_137 ) ) ; endmodule @@ -671,14 +674,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_69 ) ) ; endmodule @@ -708,9 +710,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -740,9 +742,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -772,9 +774,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -804,9 +806,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -836,9 +838,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) ) ; endmodule @@ -899,9 +901,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_58 ) ) ; endmodule @@ -931,9 +933,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_55 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_56 ) ) ; endmodule @@ -963,9 +965,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_53 ( .A ( BUF_net_54 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_54 ) ) ; endmodule @@ -995,9 +997,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_52 ) ) ; endmodule @@ -1027,9 +1029,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_48 ( .A ( BUF_net_49 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_50 ) ) ; endmodule @@ -1059,9 +1061,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_47 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_48 ) ) ; endmodule @@ -1091,9 +1093,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_45 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_46 ) ) ; endmodule @@ -1154,7 +1156,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1185,8 +1187,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; endmodule @@ -1247,6 +1250,7 @@ output [0:19] chanx_right_out ; output [0:0] ccff_tail ; input prog_clk_0_E_in ; +wire ropt_net_107 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -1303,92 +1307,92 @@ sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -1484,7 +1488,7 @@ sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , @@ -1492,7 +1496,7 @@ sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , @@ -1510,7 +1514,7 @@ sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , @@ -1518,7 +1522,7 @@ sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1534,13 +1538,13 @@ sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 ( right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -1567,8 +1571,8 @@ sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) , .X ( chany_top_out[7] ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) , .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_107 ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) , @@ -1585,14 +1589,16 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , +sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , .HI ( optlc_net_79 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , + .HI ( optlc_net_80 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[9] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v index dc78144..679d359 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v @@ -72,10 +72,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -216,9 +216,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -236,6 +233,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -369,10 +370,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -385,18 +386,18 @@ output [0:1] mem_out ; input VDD ; input VSS ; +wire copt_net_92 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_91 ) , .X ( ccff_tail[0] ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_92 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1251 ( .A ( mem_out[1] ) , - .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_92 ) , .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_88 ) , .X ( copt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -404,6 +405,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_89 ) , .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_90 ) , .X ( copt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1256 ( .A ( copt_net_91 ) , + .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -755,28 +758,28 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_137 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1244 ( .A ( ccff_head[0] ) , - .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( copt_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( ccff_head[0] ) , .X ( copt_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1246 ( .A ( copt_net_85 ) , .X ( copt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1247 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1249 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( copt_net_84 ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1280 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( copt_net_82 ) , + .X ( copt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( copt_net_84 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1301 ( .A ( ropt_net_136 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -795,16 +798,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -829,10 +831,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -857,10 +859,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -885,10 +887,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -913,10 +915,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -941,10 +943,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -996,10 +998,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1024,10 +1026,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_55 ( .A ( BUF_net_56 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1052,10 +1054,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_53 ( .A ( BUF_net_54 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_54 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1080,10 +1082,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1108,10 +1110,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_48 ( .A ( BUF_net_49 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1136,10 +1138,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_47 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1164,10 +1166,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_45 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1219,7 +1221,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1245,8 +1247,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_43 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_43 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1305,6 +1309,7 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; +wire ropt_net_107 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -1364,109 +1369,109 @@ sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -1564,7 +1569,7 @@ sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , @@ -1573,7 +1578,7 @@ sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , @@ -1592,7 +1597,7 @@ sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , @@ -1601,7 +1606,7 @@ sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1618,14 +1623,14 @@ sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -1652,8 +1657,8 @@ sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) , .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) , .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) , @@ -1670,14 +1675,16 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , +sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , .HI ( optlc_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , + .HI ( optlc_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v index a86c965..a67a026 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v @@ -53,9 +53,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -162,8 +162,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -178,6 +176,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -282,9 +283,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -295,14 +296,14 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; +wire copt_net_92 ; + sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_91 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1251 ( .A ( mem_out[1] ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_87 ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_92 ) , .X ( copt_net_88 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_88 ) , .X ( copt_net_89 ) ) ; @@ -310,6 +311,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_89 ) , .X ( copt_net_90 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_90 ) , .X ( copt_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1256 ( .A ( copt_net_91 ) , + .X ( mem_out[1] ) ) ; endmodule @@ -560,27 +563,27 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_137 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1244 ( .A ( ccff_head[0] ) , - .X ( copt_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( copt_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1245 ( .A ( ccff_head[0] ) , .X ( copt_net_81 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1246 ( .A ( copt_net_85 ) , .X ( copt_net_82 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1247 ( .A ( copt_net_81 ) , .X ( copt_net_83 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1248 ( .A ( copt_net_86 ) , .X ( copt_net_84 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1249 ( .A ( copt_net_83 ) , .X ( copt_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( copt_net_84 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1280 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( copt_net_82 ) , + .X ( copt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( copt_net_84 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1301 ( .A ( ropt_net_136 ) , + .X ( ropt_net_137 ) ) ; endmodule @@ -594,14 +597,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_69 ) ) ; endmodule @@ -620,9 +622,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -641,9 +643,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -662,9 +664,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -683,9 +685,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -704,9 +706,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_58 ( .A ( BUF_net_59 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) ) ; endmodule @@ -745,9 +747,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_58 ) ) ; endmodule @@ -766,9 +768,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_55 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_56 ) ) ; endmodule @@ -787,9 +789,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_53 ( .A ( BUF_net_54 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_54 ) ) ; endmodule @@ -808,9 +810,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_52 ) ) ; endmodule @@ -829,9 +831,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_48 ( .A ( BUF_net_49 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_50 ) ) ; endmodule @@ -850,9 +852,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_47 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_48 ) ) ; endmodule @@ -871,9 +873,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_45 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_46 ) ) ; endmodule @@ -912,7 +914,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -932,8 +934,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; endmodule @@ -983,6 +986,7 @@ output [0:19] chanx_right_out ; output [0:0] ccff_tail ; input prog_clk_0_E_in ; +wire ropt_net_107 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -1039,92 +1043,92 @@ sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -1220,7 +1224,7 @@ sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , @@ -1228,7 +1232,7 @@ sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , @@ -1246,7 +1250,7 @@ sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , @@ -1254,7 +1258,7 @@ sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1270,13 +1274,13 @@ sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 ( right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -1303,8 +1307,8 @@ sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) , .X ( chany_top_out[7] ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) , .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_107 ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) , @@ -1321,14 +1325,16 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , +sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , .HI ( optlc_net_79 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , + .HI ( optlc_net_80 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[9] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.top_only.pt.v index f92a7f4..1908b64 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.top_only.pt.v @@ -29,6 +29,7 @@ output [0:19] chanx_right_out ; output [0:0] ccff_tail ; input prog_clk_0_E_in ; +wire ropt_net_107 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -85,92 +86,92 @@ sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_78 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_79 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_77 ) ) ; sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -266,7 +267,7 @@ sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , @@ -274,7 +275,7 @@ sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , @@ -292,7 +293,7 @@ sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , @@ -300,7 +301,7 @@ sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -316,13 +317,13 @@ sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 ( right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_77 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_76 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -349,8 +350,8 @@ sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) , .X ( chany_top_out[7] ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) , .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_107 ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) , @@ -367,14 +368,16 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , +sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , +sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , +sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , .HI ( optlc_net_79 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) , + .HI ( optlc_net_80 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[9] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v index 9381cf8..cf1bf8c 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v @@ -151,9 +151,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; endmodule @@ -178,13 +178,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__1__const1_30 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -214,9 +214,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_107 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -246,9 +246,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -278,9 +278,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_91 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -291,25 +291,24 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_125 ; - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_125 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_125 ) , - .X ( copt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_120 ) , - .X ( copt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_121 ) , - .X ( copt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_122 ) , - .X ( copt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_123 ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( copt_net_129 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( mem_out[1] ) , .X ( copt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_124 ) , - .X ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( copt_net_124 ) , + .X ( copt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_125 ) , + .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_126 ) , + .X ( copt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_127 ) , + .X ( copt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_128 ) , + .X ( copt_net_129 ) ) ; endmodule @@ -403,9 +402,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -439,8 +438,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -466,6 +466,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_0__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -474,8 +476,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -509,9 +509,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -647,9 +647,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_81 ) ) ; endmodule @@ -699,9 +699,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) ) ; endmodule @@ -731,6 +731,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_0__1__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -751,8 +753,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -909,9 +909,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_77 ) ) ; endmodule @@ -949,9 +949,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_106 ) ) ; endmodule @@ -1028,9 +1028,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -1068,9 +1068,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_71 ) ) ; endmodule @@ -1097,8 +1097,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1110,6 +1108,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -1147,7 +1148,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1275,9 +1276,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -1391,6 +1392,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_0__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1405,9 +1408,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_67 ) ) ; endmodule @@ -1449,9 +1449,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1564,31 +1563,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_129 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_133 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_115 ) , - .X ( copt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_114 ) , - .X ( copt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_119 ) , - .X ( copt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_116 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_120 ) , .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_118 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_121 ) , .X ( copt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1289 ( .A ( copt_net_117 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1290 ( .A ( ropt_net_127 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1291 ( .A ( ropt_net_128 ) , - .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_123 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( ccff_head[0] ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1299 ( .A ( copt_net_118 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( ropt_net_131 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) ) ; endmodule @@ -1758,8 +1757,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1777,6 +1774,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1822,8 +1821,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -1869,9 +1869,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1900,6 +1899,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1917,8 +1918,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -2025,21 +2024,21 @@ sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , @@ -2047,28 +2046,28 @@ sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2109,35 +2108,35 @@ sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_top_out[9] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2169,49 +2168,49 @@ sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_top_out[11] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_bottom_out[9] , right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 ( .in ( { chany_bottom_out[13] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 ( .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] , chany_top_out[19] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -2255,7 +2254,7 @@ sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[6] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -2264,7 +2263,7 @@ sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -2273,7 +2272,7 @@ sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , @@ -2294,29 +2293,29 @@ sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 ( chany_top_out[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 ( .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 ( .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 ( .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -2345,32 +2344,32 @@ sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , @@ -2457,14 +2456,16 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_93 ) , + .HI ( optlc_net_117 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v index d31f87b..f30b0d8 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v @@ -178,10 +178,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -200,15 +200,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -233,10 +232,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -261,10 +260,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -289,10 +288,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -305,29 +304,27 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_125 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_125 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_125 ) , - .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_120 ) , - .X ( copt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_121 ) , - .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_122 ) , - .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_123 ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( copt_net_129 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( mem_out[1] ) , .X ( copt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_124 ) , - .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( copt_net_124 ) , + .X ( copt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_125 ) , + .X ( copt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_126 ) , + .X ( copt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_127 ) , + .X ( copt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_128 ) , + .X ( copt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -441,10 +438,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -474,8 +471,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -495,6 +494,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -505,8 +507,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -536,10 +536,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -688,10 +688,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -739,10 +739,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -766,6 +766,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -790,8 +793,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -986,10 +987,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1023,10 +1024,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1096,10 +1097,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1133,10 +1134,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1157,9 +1158,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1173,6 +1171,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1206,7 +1208,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1361,10 +1363,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1468,6 +1470,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1485,10 +1490,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1527,10 +1528,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1684,7 +1683,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_129 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_133 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1692,24 +1691,24 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_115 ) , - .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_114 ) , - .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_119 ) , - .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_116 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_120 ) , .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_118 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_121 ) , .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1289 ( .A ( copt_net_117 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1290 ( .A ( ropt_net_127 ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1291 ( .A ( ropt_net_128 ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_123 ) , + .X ( copt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( ccff_head[0] ) , + .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1299 ( .A ( copt_net_118 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( ropt_net_131 ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1867,9 +1866,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1890,6 +1886,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1932,8 +1930,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1976,10 +1976,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2002,6 +2000,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2022,8 +2023,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2135,7 +2134,7 @@ sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) , @@ -2143,7 +2142,7 @@ sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) , @@ -2151,7 +2150,7 @@ sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , @@ -2160,7 +2159,7 @@ sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , @@ -2168,7 +2167,7 @@ sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , @@ -2176,7 +2175,7 @@ sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , @@ -2184,7 +2183,7 @@ sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2226,7 +2225,7 @@ sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_top_out[9] , chany_top_out[18] } ) , @@ -2234,7 +2233,7 @@ sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , @@ -2242,7 +2241,7 @@ sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , @@ -2250,7 +2249,7 @@ sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , @@ -2258,7 +2257,7 @@ sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2291,7 +2290,7 @@ sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_top_out[11] } ) , @@ -2299,7 +2298,7 @@ sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_bottom_out[9] , right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) , @@ -2307,7 +2306,7 @@ sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) , @@ -2315,7 +2314,7 @@ sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) , @@ -2323,7 +2322,7 @@ sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 ( .in ( { chany_bottom_out[13] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) , @@ -2331,7 +2330,7 @@ sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 ( .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] , chany_top_out[19] , chany_bottom_in[19] } ) , @@ -2339,7 +2338,7 @@ sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -2384,7 +2383,7 @@ sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[6] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -2394,7 +2393,7 @@ sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -2404,7 +2403,7 @@ sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , @@ -2426,33 +2425,33 @@ sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 ( .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 ( .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 ( .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -2483,37 +2482,37 @@ sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , @@ -2600,14 +2599,16 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , + .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_93 ) , + .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v index aa363c2..92bedf5 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v @@ -129,9 +129,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; endmodule @@ -145,13 +145,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -170,9 +170,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_107 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -191,9 +191,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -212,9 +212,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_91 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -225,25 +225,24 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_125 ; - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_125 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_125 ) , - .X ( copt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_120 ) , - .X ( copt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_121 ) , - .X ( copt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_122 ) , - .X ( copt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_123 ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( copt_net_129 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( mem_out[1] ) , .X ( copt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_124 ) , - .X ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( copt_net_124 ) , + .X ( copt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_125 ) , + .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_126 ) , + .X ( copt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_127 ) , + .X ( copt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_128 ) , + .X ( copt_net_129 ) ) ; endmodule @@ -326,9 +325,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -351,8 +350,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -367,6 +367,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -375,8 +377,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -399,9 +399,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -515,9 +515,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_81 ) ) ; endmodule @@ -556,9 +556,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) ) ; endmodule @@ -577,6 +577,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -597,8 +599,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -744,9 +744,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_77 ) ) ; endmodule @@ -773,9 +773,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_106 ) ) ; endmodule @@ -830,9 +830,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -859,9 +859,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_71 ) ) ; endmodule @@ -877,8 +877,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -890,6 +888,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -916,7 +917,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1033,9 +1034,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -1116,6 +1117,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1130,9 +1133,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_67 ) ) ; endmodule @@ -1163,9 +1163,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1278,31 +1277,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_129 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_133 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_115 ) , - .X ( copt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_114 ) , - .X ( copt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_119 ) , - .X ( copt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_116 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_120 ) , .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_118 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_121 ) , .X ( copt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1289 ( .A ( copt_net_117 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1290 ( .A ( ropt_net_127 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1291 ( .A ( ropt_net_128 ) , - .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_123 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( ccff_head[0] ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1299 ( .A ( copt_net_118 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1300 ( .A ( ropt_net_131 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) ) ; endmodule @@ -1428,8 +1427,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1447,6 +1444,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1481,8 +1480,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -1517,9 +1517,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1537,6 +1536,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1554,8 +1555,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1662,21 +1661,21 @@ sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , @@ -1684,28 +1683,28 @@ sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1746,35 +1745,35 @@ sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_top_out[9] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1806,49 +1805,49 @@ sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_top_out[11] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_bottom_out[9] , right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 ( .in ( { chany_bottom_out[13] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 ( .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] , chany_top_out[19] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -1892,7 +1891,7 @@ sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[6] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -1901,7 +1900,7 @@ sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -1910,7 +1909,7 @@ sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , @@ -1931,29 +1930,29 @@ sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 ( chany_top_out[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 ( .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 ( .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 ( .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -1982,32 +1981,32 @@ sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , @@ -2094,14 +2093,16 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_93 ) , + .HI ( optlc_net_117 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.top_only.pt.v index f894582..d1f94c7 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.top_only.pt.v @@ -107,21 +107,21 @@ sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , @@ -129,28 +129,28 @@ sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -191,35 +191,35 @@ sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_top_out[9] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -251,49 +251,49 @@ sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_top_out[11] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_bottom_out[9] , right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 ( .in ( { chany_bottom_out[13] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_114 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 ( .in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] , chany_top_out[19] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -337,7 +337,7 @@ sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[6] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -346,7 +346,7 @@ sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -355,7 +355,7 @@ sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_113 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_115 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , @@ -376,29 +376,29 @@ sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 ( chany_top_out[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 ( .in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 ( .in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 ( .in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_117 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -427,32 +427,32 @@ sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_110 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_111 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_113 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , @@ -539,14 +539,16 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_93 ) , + .HI ( optlc_net_117 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v index bab76b8..3cd3cba 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v @@ -11,23 +11,21 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_79 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_79 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_79 ) , - .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_75 ) , - .X ( copt_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1240 ( .A ( copt_net_76 ) , - .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1241 ( .A ( copt_net_77 ) , - .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1242 ( .A ( copt_net_78 ) , - .X ( mem_out[1] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( copt_net_71 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( mem_out[1] ) , + .X ( copt_net_70 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_74 ) , + .X ( copt_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1237 ( .A ( copt_net_70 ) , + .X ( copt_net_72 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_72 ) , + .X ( copt_net_73 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_73 ) , + .X ( copt_net_74 ) ) ; endmodule @@ -312,7 +310,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -374,7 +372,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -405,7 +403,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -467,7 +465,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -529,9 +527,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_51 ) ) ; endmodule @@ -561,9 +559,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_58 ( .A ( BUF_net_49 ) , .Y ( out[0] ) ) ; endmodule @@ -588,13 +586,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -619,13 +617,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -681,14 +679,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) ) ; endmodule @@ -780,9 +777,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -807,13 +803,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -908,9 +904,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_45 ) ) ; endmodule @@ -936,6 +932,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_0__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -944,9 +942,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_46 ) ) ; endmodule @@ -1022,9 +1017,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_43 ) ) ; endmodule @@ -1052,6 +1047,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_0__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1066,8 +1063,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1095,29 +1090,29 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_131 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_118 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_69 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( ccff_head[0] ) , + .X ( copt_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_63 ) , + .X ( copt_net_64 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1230 ( .A ( copt_net_64 ) , + .X ( copt_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_68 ) , + .X ( copt_net_66 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_65 ) , + .X ( copt_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_67 ) , .X ( copt_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_71 ) , - .X ( copt_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_73 ) , - .X ( copt_net_70 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_70 ) , - .X ( copt_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( ccff_head[0] ) , - .X ( copt_net_72 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_72 ) , - .X ( copt_net_73 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1292 ( .A ( ropt_net_132 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1293 ( .A ( copt_net_68 ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1281 ( .A ( copt_net_66 ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1282 ( .A ( ropt_net_117 ) , + .X ( ropt_net_118 ) ) ; endmodule @@ -1242,8 +1237,8 @@ input SC_IN_TOP ; output SC_OUT_BOT ; input prog_clk_0_E_in ; -wire ropt_net_95 ; -wire ropt_net_96 ; +wire ropt_net_88 ; +wire ropt_net_87 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -1303,7 +1298,7 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , @@ -1311,7 +1306,7 @@ sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1328,7 +1323,7 @@ sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -1336,7 +1331,7 @@ sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1352,13 +1347,13 @@ sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 ( chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -1373,92 +1368,92 @@ sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -1558,20 +1553,20 @@ sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chanx_right_in[4] ) , .X ( chany_bottom_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) , .X ( chany_bottom_out[13] ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[8] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) ) ; sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_96 ) ) ; + .X ( ropt_net_88 ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) , @@ -1580,18 +1575,18 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) , .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_87 ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_65 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , - .HI ( optlc_net_66 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , - .HI ( optlc_net_67 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1257 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_96 ) , +sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , + .HI ( optlc_net_60 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , + .HI ( optlc_net_61 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , + .HI ( optlc_net_62 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1252 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1253 ( .A ( ropt_net_88 ) , .X ( chany_bottom_out[7] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v index 556fc2e..3130649 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v @@ -13,27 +13,25 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_79 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_79 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( copt_net_71 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_79 ) , - .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_75 ) , - .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1240 ( .A ( copt_net_76 ) , - .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1241 ( .A ( copt_net_77 ) , - .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1242 ( .A ( copt_net_78 ) , - .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( mem_out[1] ) , + .X ( copt_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_74 ) , + .X ( copt_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1237 ( .A ( copt_net_70 ) , + .X ( copt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_72 ) , + .X ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_73 ) , + .X ( copt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -415,7 +413,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -468,7 +466,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -494,7 +492,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -547,7 +545,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -600,10 +598,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -628,9 +626,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_56 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_58 ( .A ( BUF_net_49 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -650,32 +648,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -688,6 +660,32 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -730,16 +728,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -818,10 +815,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -840,14 +835,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -946,10 +942,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_45 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -969,6 +965,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -979,10 +978,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1067,10 +1062,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_44 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_43 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1092,6 +1087,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1109,8 +1107,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1149,7 +1145,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_131 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_118 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1157,22 +1153,22 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_69 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( ccff_head[0] ) , + .X ( copt_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_63 ) , + .X ( copt_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1230 ( .A ( copt_net_64 ) , + .X ( copt_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_68 ) , + .X ( copt_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_65 ) , + .X ( copt_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_67 ) , .X ( copt_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_71 ) , - .X ( copt_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_73 ) , - .X ( copt_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_70 ) , - .X ( copt_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( ccff_head[0] ) , - .X ( copt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_72 ) , - .X ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1292 ( .A ( ropt_net_132 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1293 ( .A ( copt_net_68 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1281 ( .A ( copt_net_66 ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1282 ( .A ( ropt_net_117 ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1294,8 +1290,8 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; -wire ropt_net_95 ; -wire ropt_net_96 ; +wire ropt_net_88 ; +wire ropt_net_87 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -1358,7 +1354,7 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , @@ -1367,7 +1363,7 @@ sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1385,7 +1381,7 @@ sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -1394,7 +1390,7 @@ sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1411,14 +1407,14 @@ sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -1434,109 +1430,109 @@ sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_65 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_66 ) ) ; + .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -1637,20 +1633,20 @@ sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chanx_right_in[4] ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) , .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[8] ) , .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) , @@ -1659,19 +1655,19 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , - .HI ( optlc_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , - .HI ( optlc_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1257 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_96 ) , +sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , + .HI ( optlc_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , + .HI ( optlc_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , + .HI ( optlc_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1252 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1253 ( .A ( ropt_net_88 ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v index c987235..cd4287e 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v @@ -11,23 +11,21 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_79 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_79 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_79 ) , - .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_75 ) , - .X ( copt_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1240 ( .A ( copt_net_76 ) , - .X ( copt_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1241 ( .A ( copt_net_77 ) , - .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1242 ( .A ( copt_net_78 ) , - .X ( mem_out[1] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( copt_net_71 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( mem_out[1] ) , + .X ( copt_net_70 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_74 ) , + .X ( copt_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1237 ( .A ( copt_net_70 ) , + .X ( copt_net_72 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1238 ( .A ( copt_net_72 ) , + .X ( copt_net_73 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1239 ( .A ( copt_net_73 ) , + .X ( copt_net_74 ) ) ; endmodule @@ -301,7 +299,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -341,7 +339,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -361,7 +359,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -401,7 +399,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_59 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_52 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -441,9 +439,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_57 ( .A ( BUF_net_58 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_51 ) ) ; endmodule @@ -462,9 +460,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_56 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_56 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_58 ( .A ( BUF_net_49 ) , .Y ( out[0] ) ) ; endmodule @@ -478,26 +476,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -508,6 +486,26 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_47 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -538,14 +536,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_52 ( .A ( BUF_net_53 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_53 ) ) ; endmodule @@ -604,9 +601,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_50 ( .A ( BUF_net_51 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -620,13 +616,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -699,9 +695,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_45 ) ) ; endmodule @@ -716,6 +712,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -724,9 +722,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_45 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_46 ) ) ; endmodule @@ -791,9 +786,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_43 ( .A ( BUF_net_44 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_44 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_43 ) ) ; endmodule @@ -810,6 +805,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -824,8 +821,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_42 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -853,29 +848,29 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_131 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_118 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_69 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( ccff_head[0] ) , + .X ( copt_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_63 ) , + .X ( copt_net_64 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1230 ( .A ( copt_net_64 ) , + .X ( copt_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_68 ) , + .X ( copt_net_66 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_65 ) , + .X ( copt_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_67 ) , .X ( copt_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_71 ) , - .X ( copt_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_73 ) , - .X ( copt_net_70 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_70 ) , - .X ( copt_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( ccff_head[0] ) , - .X ( copt_net_72 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_72 ) , - .X ( copt_net_73 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1292 ( .A ( ropt_net_132 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1293 ( .A ( copt_net_68 ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1281 ( .A ( copt_net_66 ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1282 ( .A ( ropt_net_117 ) , + .X ( ropt_net_118 ) ) ; endmodule @@ -978,8 +973,8 @@ input SC_IN_TOP ; output SC_OUT_BOT ; input prog_clk_0_E_in ; -wire ropt_net_95 ; -wire ropt_net_96 ; +wire ropt_net_88 ; +wire ropt_net_87 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -1039,7 +1034,7 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , @@ -1047,7 +1042,7 @@ sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1064,7 +1059,7 @@ sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -1072,7 +1067,7 @@ sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1088,13 +1083,13 @@ sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 ( chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -1109,92 +1104,92 @@ sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -1294,20 +1289,20 @@ sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chanx_right_in[4] ) , .X ( chany_bottom_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) , .X ( chany_bottom_out[13] ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[8] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) ) ; sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_96 ) ) ; + .X ( ropt_net_88 ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) , @@ -1316,18 +1311,18 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) , .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_87 ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_65 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , - .HI ( optlc_net_66 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , - .HI ( optlc_net_67 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1257 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_96 ) , +sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , + .HI ( optlc_net_60 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , + .HI ( optlc_net_61 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , + .HI ( optlc_net_62 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1252 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1253 ( .A ( ropt_net_88 ) , .X ( chany_bottom_out[7] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.top_only.pt.v index 4713a1f..6984798 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.top_only.pt.v @@ -31,8 +31,8 @@ input SC_IN_TOP ; output SC_OUT_BOT ; input prog_clk_0_E_in ; -wire ropt_net_95 ; -wire ropt_net_96 ; +wire ropt_net_88 ; +wire ropt_net_87 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -92,7 +92,7 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , @@ -100,7 +100,7 @@ sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -117,7 +117,7 @@ sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -125,7 +125,7 @@ sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -141,13 +141,13 @@ sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 ( chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -162,92 +162,92 @@ sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_60 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_67 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_62 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_65 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_66 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_61 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -347,20 +347,20 @@ sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chanx_right_in[4] ) , .X ( chany_bottom_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) , .X ( chany_bottom_out[13] ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[8] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) ) ; sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_96 ) ) ; + .X ( ropt_net_88 ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) , @@ -369,18 +369,18 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) , .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_87 ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , - .HI ( optlc_net_65 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , - .HI ( optlc_net_66 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , - .HI ( optlc_net_67 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1257 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_96 ) , +sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) , + .HI ( optlc_net_60 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) , + .HI ( optlc_net_61 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) , + .HI ( optlc_net_62 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1252 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1253 ( .A ( ropt_net_88 ) , .X ( chany_bottom_out[7] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v index cb328a5..f36bbc4 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v @@ -93,20 +93,20 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -wire copt_net_107 ; +wire copt_net_106 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_107 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) ) ; sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_106 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_107 ) , - .X ( copt_net_106 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1288 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_106 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_109 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1290 ( .A ( copt_net_110 ) , .X ( mem_out[2] ) ) ; endmodule @@ -153,8 +153,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_1__0__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -172,6 +170,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -217,9 +217,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -414,9 +414,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -512,8 +511,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -617,8 +617,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; endmodule @@ -757,9 +758,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -821,6 +822,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -829,9 +832,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_76 ) ) ; endmodule @@ -865,9 +865,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -901,9 +901,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -937,9 +937,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -973,8 +973,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -1074,6 +1075,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_1__0__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1085,8 +1088,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1357,9 +1358,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -1389,8 +1390,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__0__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1411,6 +1410,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -1440,8 +1442,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1462,6 +1462,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1640,24 +1642,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_99 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_102 ) , .X ( copt_net_100 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_100 ) , .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_105 ) , .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( ccff_head[0] ) , .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_101 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( copt_net_104 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_131 ) , .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_132 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_132 ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( copt_net_103 ) , - .X ( ropt_net_134 ) ) ; endmodule @@ -1821,9 +1823,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1943,6 +1944,7 @@ output prog_clk_3_N_out ; input clk_3_S_in ; output clk_3_N_out ; +wire ropt_net_119 ; wire ropt_net_118 ; wire [0:0] prog_clk ; wire prog_clk_0 ; @@ -2012,7 +2014,7 @@ sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , @@ -2021,7 +2023,7 @@ sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ; sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] , chanx_left_out[14] , left_bottom_grid_pin_3_[0] , @@ -2030,7 +2032,7 @@ sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] , @@ -2038,7 +2040,7 @@ sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -2064,7 +2066,7 @@ sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -2072,7 +2074,7 @@ sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -2080,7 +2082,7 @@ sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , SYNOPSYS_UNCONNECTED_25 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , @@ -2088,7 +2090,7 @@ sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] , @@ -2104,7 +2106,7 @@ sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] , @@ -2112,7 +2114,7 @@ sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -2154,14 +2156,14 @@ sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 ( .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] , chanx_right_out[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , @@ -2176,43 +2178,43 @@ sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( chanx_right_out[11] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -2251,7 +2253,7 @@ sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[19] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -2273,7 +2275,7 @@ sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -2306,7 +2308,7 @@ sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , @@ -2324,7 +2326,7 @@ sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_left_out[11] , left_bottom_grid_pin_7_[0] , @@ -2332,7 +2334,7 @@ sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , @@ -2350,14 +2352,14 @@ sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_95 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , @@ -2402,8 +2404,8 @@ sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[7] ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_119 ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) , @@ -2418,8 +2420,8 @@ sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) , .X ( chanx_right_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) , @@ -2428,26 +2430,28 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( Test_en_S_in ) , .Y ( BUF_net_86 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( Test_en_S_in ) , .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( prog_clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_88 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_118 ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[17] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v index 34c4da4..ad9a9b6 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v @@ -101,7 +101,7 @@ output [0:2] mem_out ; input VDD ; input VSS ; -wire copt_net_107 ; +wire copt_net_106 ; supply1 VDD ; supply0 VSS ; @@ -110,15 +110,15 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_107 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_106 ) , - .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_107 ) , - .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1288 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_106 ) , + .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_109 ) , + .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1290 ( .A ( copt_net_110 ) , .X ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -165,9 +165,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -188,6 +185,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -230,10 +229,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -443,10 +442,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -553,8 +550,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -659,8 +658,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -837,10 +838,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -893,6 +894,38 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -910,7 +943,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -943,7 +976,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -976,7 +1009,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -1009,37 +1042,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; @@ -1139,6 +1141,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1152,8 +1157,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1462,10 +1465,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1489,9 +1492,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1516,6 +1516,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1539,9 +1543,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1566,6 +1567,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1766,24 +1769,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_99 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_102 ) , .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_100 ) , .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_105 ) , .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( ccff_head[0] ) , .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_101 ) , + .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( copt_net_104 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_131 ) , .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_132 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_132 ) , .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( copt_net_103 ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1943,10 +1946,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2067,6 +2068,7 @@ output clk_3_N_out ; input VDD ; input VSS ; +wire ropt_net_119 ; wire ropt_net_118 ; wire [0:0] prog_clk ; wire prog_clk_0 ; @@ -2139,7 +2141,7 @@ sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , @@ -2149,7 +2151,7 @@ sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] , chanx_left_out[14] , left_bottom_grid_pin_3_[0] , @@ -2159,7 +2161,7 @@ sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] , @@ -2168,7 +2170,7 @@ sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -2195,7 +2197,7 @@ sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -2204,7 +2206,7 @@ sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -2213,7 +2215,7 @@ sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , SYNOPSYS_UNCONNECTED_25 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , @@ -2222,7 +2224,7 @@ sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] , @@ -2240,7 +2242,7 @@ sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] , @@ -2249,7 +2251,7 @@ sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -2292,7 +2294,7 @@ sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 ( .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] , chanx_right_out[10] } ) , @@ -2300,7 +2302,7 @@ sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , @@ -2316,49 +2318,49 @@ sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -2398,7 +2400,7 @@ sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -2422,7 +2424,7 @@ sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -2457,7 +2459,7 @@ sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , @@ -2476,7 +2478,7 @@ sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_left_out[11] , left_bottom_grid_pin_7_[0] , @@ -2485,7 +2487,7 @@ sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , @@ -2505,14 +2507,14 @@ sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , @@ -2557,8 +2559,8 @@ sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[7] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) , @@ -2573,8 +2575,8 @@ sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) , .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) , @@ -2583,30 +2585,32 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) , .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( Test_en_N_out ) , +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( Test_en_S_in ) , .Y ( BUF_net_86 ) , +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( Test_en_S_in ) , .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( clk_3_N_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_118 ) , + .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v index d8a05c3..9969833 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v @@ -82,20 +82,20 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -wire copt_net_107 ; +wire copt_net_106 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_107 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) ) ; sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_106 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_107 ) , - .X ( copt_net_106 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1288 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_106 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_109 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1290 ( .A ( copt_net_110 ) , .X ( mem_out[2] ) ) ; endmodule @@ -131,8 +131,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -150,6 +148,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -184,9 +184,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -359,9 +359,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -446,8 +445,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -529,8 +529,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; endmodule @@ -658,9 +659,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -700,6 +701,30 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -714,7 +739,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -739,7 +764,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -764,7 +789,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -789,30 +814,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; @@ -887,6 +888,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -898,8 +901,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1137,9 +1138,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -1158,8 +1159,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1180,6 +1179,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -1198,8 +1200,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1220,6 +1220,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1376,24 +1378,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_99 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_102 ) , .X ( copt_net_100 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_100 ) , .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_105 ) , .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( ccff_head[0] ) , .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_101 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1308 ( .A ( copt_net_104 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_131 ) , .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( ropt_net_132 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_132 ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( copt_net_103 ) , - .X ( ropt_net_134 ) ) ; endmodule @@ -1524,9 +1526,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1635,6 +1636,7 @@ output prog_clk_3_N_out ; input clk_3_S_in ; output clk_3_N_out ; +wire ropt_net_119 ; wire ropt_net_118 ; wire [0:0] prog_clk ; wire prog_clk_0 ; @@ -1704,7 +1706,7 @@ sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , @@ -1713,7 +1715,7 @@ sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ; sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] , chanx_left_out[14] , left_bottom_grid_pin_3_[0] , @@ -1722,7 +1724,7 @@ sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] , @@ -1730,7 +1732,7 @@ sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -1756,7 +1758,7 @@ sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -1764,7 +1766,7 @@ sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -1772,7 +1774,7 @@ sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , SYNOPSYS_UNCONNECTED_25 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , @@ -1780,7 +1782,7 @@ sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] , @@ -1796,7 +1798,7 @@ sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] , @@ -1804,7 +1806,7 @@ sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -1846,14 +1848,14 @@ sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 ( .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] , chanx_right_out[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , @@ -1868,43 +1870,43 @@ sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( chanx_right_out[11] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -1943,7 +1945,7 @@ sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[19] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -1965,7 +1967,7 @@ sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -1998,7 +2000,7 @@ sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , @@ -2016,7 +2018,7 @@ sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_left_out[11] , left_bottom_grid_pin_7_[0] , @@ -2024,7 +2026,7 @@ sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , @@ -2042,14 +2044,14 @@ sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_95 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , @@ -2094,8 +2096,8 @@ sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[7] ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_119 ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) , @@ -2110,8 +2112,8 @@ sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) , .X ( chanx_right_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) , @@ -2120,26 +2122,28 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( Test_en_S_in ) , .Y ( BUF_net_86 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( Test_en_S_in ) , .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( prog_clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_88 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_118 ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[17] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.top_only.pt.v index 5714919..c048e22 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.top_only.pt.v @@ -64,6 +64,7 @@ output prog_clk_3_N_out ; input clk_3_S_in ; output clk_3_N_out ; +wire ropt_net_119 ; wire ropt_net_118 ; wire [0:0] prog_clk ; wire prog_clk_0 ; @@ -133,7 +134,7 @@ sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , @@ -142,7 +143,7 @@ sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ; sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] , chanx_left_out[14] , left_bottom_grid_pin_3_[0] , @@ -151,7 +152,7 @@ sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] , @@ -159,7 +160,7 @@ sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -185,7 +186,7 @@ sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -193,7 +194,7 @@ sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .in ( { chany_top_out[13] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -201,7 +202,7 @@ sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , SYNOPSYS_UNCONNECTED_25 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , @@ -209,7 +210,7 @@ sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] , @@ -225,7 +226,7 @@ sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] , @@ -233,7 +234,7 @@ sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -275,14 +276,14 @@ sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 ( .in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] , chanx_right_out[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , @@ -297,43 +298,43 @@ sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( chanx_right_out[11] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_95 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -372,7 +373,7 @@ sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chany_top_out[19] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -394,7 +395,7 @@ sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -427,7 +428,7 @@ sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , @@ -445,7 +446,7 @@ sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_left_out[11] , left_bottom_grid_pin_7_[0] , @@ -453,7 +454,7 @@ sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , @@ -471,14 +472,14 @@ sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_98 ) ) ; sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_95 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , @@ -523,8 +524,8 @@ sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[7] ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_119 ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) , @@ -539,8 +540,8 @@ sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) , .X ( chanx_right_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) , @@ -549,26 +550,28 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( Test_en_S_in ) , .Y ( BUF_net_86 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( Test_en_S_in ) , .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( prog_clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_88 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_118 ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[17] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v index 7a82381..a05ef68 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v @@ -11,16 +11,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; +wire copt_net_120 ; + sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_119 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( mem_out[2] ) , - .X ( copt_net_119 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_120 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_120 ) , + .X ( mem_out[2] ) ) ; endmodule @@ -203,8 +204,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__1__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -225,6 +224,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -274,8 +276,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -536,8 +539,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -567,6 +568,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -628,7 +631,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -691,9 +694,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_94 ) ) ; endmodule @@ -944,9 +947,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_92 ) ) ; endmodule @@ -1008,9 +1011,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_90 ) ) ; endmodule @@ -1043,6 +1046,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1072,9 +1077,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) ) ; endmodule @@ -1107,6 +1109,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1136,8 +1140,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1170,6 +1172,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1199,8 +1203,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1262,9 +1264,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) ) ; endmodule @@ -1695,9 +1697,9 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , - .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -1841,7 +1843,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_124 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_125 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -1850,26 +1852,26 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_113 ) , - .X ( copt_net_108 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_108 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_114 ) , .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_109 ) , .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_110 ) , .X ( copt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_111 ) , .X ( copt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_112 ) , .X ( copt_net_113 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_122 ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1302 ( .A ( copt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( copt_net_113 ) , .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1303 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_122 ) , .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1304 ( .A ( ropt_net_123 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1311 ( .A ( ropt_net_123 ) , .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1312 ( .A ( ropt_net_124 ) , + .X ( ropt_net_125 ) ) ; endmodule @@ -2010,9 +2012,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -2047,8 +2048,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -2084,6 +2083,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -2153,7 +2154,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -2260,6 +2261,78 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_81 ) ) ; +endmodule + + +module sb_1__1__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -2300,78 +2373,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1__const1_1 ( const1 ) ; -output [0:0] const1 ; - -wire [0:0] const1_0 ; - -assign const1_0[0] = 1'b1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_82 ) ) ; -endmodule - - module sb_1__1__const1_0 ( const1 ) ; output [0:0] const1 ; @@ -2403,6 +2404,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -2438,8 +2441,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -2659,7 +2660,7 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -2679,7 +2680,7 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -2689,7 +2690,7 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] , chanx_left_out[13] , chanx_right_in[15] , @@ -2699,7 +2700,7 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] , chanx_right_in[11] , chanx_left_out[14] , @@ -2719,7 +2720,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] , chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , @@ -2729,7 +2730,7 @@ sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -2794,7 +2795,7 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] , @@ -2820,7 +2821,7 @@ sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , @@ -2858,7 +2859,7 @@ sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] , @@ -2867,7 +2868,7 @@ sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , @@ -2885,7 +2886,7 @@ sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , @@ -2894,7 +2895,7 @@ sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_107 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] , chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] , @@ -2921,7 +2922,7 @@ sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 ( .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] , chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] , @@ -2939,7 +2940,7 @@ sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] , chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] , @@ -2948,7 +2949,7 @@ sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -3016,7 +3017,7 @@ sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , @@ -3024,7 +3025,7 @@ sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , @@ -3040,7 +3041,7 @@ sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , @@ -3060,8 +3061,8 @@ sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , - .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , + .HI ( optlc_net_102 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) , @@ -3168,18 +3169,20 @@ sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , .HI ( optlc_net_103 ) ) ; sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) , .HI ( optlc_net_104 ) ) ; sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) , .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_108 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v index 4069db1..7d0ff64 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v @@ -13,6 +13,7 @@ output [0:2] mem_out ; input VDD ; input VSS ; +wire copt_net_120 ; supply1 VDD ; supply0 VSS ; @@ -21,11 +22,12 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_119 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( mem_out[2] ) , - .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_120 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_120 ) , + .X ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -218,9 +220,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -245,6 +244,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -292,8 +295,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -620,9 +625,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -657,6 +659,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -717,7 +721,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -779,10 +783,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1032,10 +1036,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1096,10 +1100,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1126,6 +1130,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1160,10 +1167,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1190,6 +1193,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1224,8 +1230,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1252,6 +1256,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1286,8 +1293,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1348,10 +1353,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1817,10 +1822,10 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , - .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2011,7 +2016,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_124 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_125 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2021,26 +2026,26 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_113 ) , - .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_108 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_114 ) , .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_109 ) , .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_110 ) , .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_111 ) , .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_112 ) , .X ( copt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_122 ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1302 ( .A ( copt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( copt_net_113 ) , .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1303 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_122 ) , .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1304 ( .A ( ropt_net_123 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1311 ( .A ( ropt_net_123 ) , .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1312 ( .A ( ropt_net_124 ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2182,10 +2187,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2214,9 +2217,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2258,6 +2258,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2327,7 +2329,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2429,6 +2431,79 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2476,79 +2551,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:11] in ; @@ -2574,6 +2576,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2615,8 +2620,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2841,7 +2844,7 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -2863,7 +2866,7 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -2874,7 +2877,7 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] , chanx_left_out[13] , chanx_right_in[15] , @@ -2885,7 +2888,7 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] , chanx_right_in[11] , chanx_left_out[14] , @@ -2907,7 +2910,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] , chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , @@ -2918,7 +2921,7 @@ sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -2985,7 +2988,7 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 ( SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] , @@ -3013,7 +3016,7 @@ sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 ( SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , @@ -3053,7 +3056,7 @@ sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] , @@ -3063,7 +3066,7 @@ sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , @@ -3083,7 +3086,7 @@ sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , @@ -3093,7 +3096,7 @@ sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; + .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] , chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] , @@ -3123,7 +3126,7 @@ sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 ( .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] , chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] , @@ -3143,7 +3146,7 @@ sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] , chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] , @@ -3153,7 +3156,7 @@ sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -3224,7 +3227,7 @@ sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , @@ -3233,7 +3236,7 @@ sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , @@ -3251,7 +3254,7 @@ sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , @@ -3272,8 +3275,8 @@ sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 ( .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , - .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) , @@ -3380,18 +3383,20 @@ sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) , .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) , .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v index a0e5561..a9e8cf6 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v @@ -11,16 +11,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; +wire copt_net_120 ; + sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_119 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( mem_out[2] ) , - .X ( copt_net_119 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_120 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_120 ) , + .X ( mem_out[2] ) ) ; endmodule @@ -170,8 +171,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -192,6 +191,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -230,8 +232,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -481,8 +484,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -512,6 +513,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -562,7 +565,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -614,9 +617,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_94 ) ) ; endmodule @@ -823,9 +826,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_92 ) ) ; endmodule @@ -876,9 +879,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_90 ) ) ; endmodule @@ -900,6 +903,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -929,9 +934,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_93 ) ) ; endmodule @@ -953,6 +955,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -982,8 +986,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1005,6 +1007,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1034,8 +1038,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1086,9 +1088,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) ) ; endmodule @@ -1475,9 +1477,9 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , - .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -1621,7 +1623,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_124 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_125 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -1630,26 +1632,26 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_113 ) , - .X ( copt_net_108 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_108 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_114 ) , .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_109 ) , .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_110 ) , .X ( copt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_111 ) , .X ( copt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_112 ) , .X ( copt_net_113 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1301 ( .A ( ropt_net_122 ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1302 ( .A ( copt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1309 ( .A ( copt_net_113 ) , .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1303 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1310 ( .A ( ropt_net_122 ) , .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1304 ( .A ( ropt_net_123 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1311 ( .A ( ropt_net_123 ) , .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1312 ( .A ( ropt_net_124 ) , + .X ( ropt_net_125 ) ) ; endmodule @@ -1768,9 +1770,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1794,8 +1795,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1831,6 +1830,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1889,7 +1890,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1974,6 +1975,67 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_81 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -2014,67 +2076,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_82 ) ) ; -endmodule - - module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; @@ -2095,6 +2096,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -2130,8 +2133,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -2351,7 +2352,7 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -2371,7 +2372,7 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -2381,7 +2382,7 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] , chanx_left_out[13] , chanx_right_in[15] , @@ -2391,7 +2392,7 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] , chanx_right_in[11] , chanx_left_out[14] , @@ -2411,7 +2412,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] , chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , @@ -2421,7 +2422,7 @@ sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -2486,7 +2487,7 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] , @@ -2512,7 +2513,7 @@ sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , @@ -2550,7 +2551,7 @@ sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] , @@ -2559,7 +2560,7 @@ sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , @@ -2577,7 +2578,7 @@ sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , @@ -2586,7 +2587,7 @@ sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_107 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] , chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] , @@ -2613,7 +2614,7 @@ sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 ( .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] , chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] , @@ -2631,7 +2632,7 @@ sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] , chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] , @@ -2640,7 +2641,7 @@ sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -2708,7 +2709,7 @@ sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , @@ -2716,7 +2717,7 @@ sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , @@ -2732,7 +2733,7 @@ sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , @@ -2752,8 +2753,8 @@ sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , - .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , + .HI ( optlc_net_102 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) , @@ -2860,18 +2861,20 @@ sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , .HI ( optlc_net_103 ) ) ; sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) , .HI ( optlc_net_104 ) ) ; sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) , .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_108 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.top_only.pt.v index 1a1df73..a01d3ce 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.top_only.pt.v @@ -220,7 +220,7 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -240,7 +240,7 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -250,7 +250,7 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] , chanx_left_out[13] , chanx_right_in[15] , @@ -260,7 +260,7 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] , chanx_right_in[11] , chanx_left_out[14] , @@ -280,7 +280,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] , chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , @@ -290,7 +290,7 @@ sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -355,7 +355,7 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] , @@ -381,7 +381,7 @@ sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , @@ -419,7 +419,7 @@ sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] , @@ -428,7 +428,7 @@ sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_107 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , @@ -446,7 +446,7 @@ sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , @@ -455,7 +455,7 @@ sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_107 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] , chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] , @@ -482,7 +482,7 @@ sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_106 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 ( .in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] , chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] , @@ -500,7 +500,7 @@ sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] , chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] , @@ -509,7 +509,7 @@ sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_105 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -577,7 +577,7 @@ sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_108 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .in ( { chany_bottom_out[11] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , @@ -585,7 +585,7 @@ sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , @@ -601,7 +601,7 @@ sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_104 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , @@ -621,8 +621,8 @@ sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , - .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , + .HI ( optlc_net_102 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) , @@ -729,18 +729,20 @@ sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) , .HI ( optlc_net_103 ) ) ; sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) , .HI ( optlc_net_104 ) ) ; sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) , .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) , .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) , .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_108 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v index 34c6fbb..aa120e4 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v @@ -11,27 +11,20 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -wire copt_net_105 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_105 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_104 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_105 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_103 ) , - .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_101 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_100 ) , - .X ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_109 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( mem_out[2] ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1295 ( .A ( copt_net_108 ) , + .X ( copt_net_109 ) ) ; endmodule @@ -60,8 +53,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_1__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -79,6 +70,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -248,7 +241,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -275,6 +268,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__2__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -283,9 +278,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_80 ) ) ; endmodule @@ -319,9 +311,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -347,8 +339,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -357,6 +347,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -543,8 +536,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_1__2__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -556,6 +547,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -653,9 +646,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -841,9 +833,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -873,8 +865,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -895,6 +885,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) ) ; endmodule @@ -944,7 +937,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1046,9 +1039,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1078,8 +1070,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1100,6 +1090,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -1149,8 +1142,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -1293,9 +1287,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_71 ) ) ; endmodule @@ -1466,9 +1460,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -1505,8 +1499,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1548,6 +1540,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1662,9 +1656,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -1722,9 +1716,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -1756,8 +1750,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; sb_1__2__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1784,6 +1776,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -1794,7 +1789,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_99 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_130 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -1803,18 +1798,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_96 ) , - .X ( copt_net_94 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_97 ) , - .X ( copt_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_94 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( ccff_head[0] ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_100 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_104 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_105 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_131 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1317 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) ) ; endmodule @@ -1935,7 +1936,8 @@ input SC_IN_BOT ; output SC_OUT_BOT ; input prog_clk_0_S_in ; -wire ropt_net_115 ; +wire ropt_net_118 ; +wire ropt_net_119 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -2005,7 +2007,7 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2018,7 +2020,7 @@ sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , @@ -2027,7 +2029,7 @@ sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -2036,7 +2038,7 @@ sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2062,7 +2064,7 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -2073,7 +2075,7 @@ sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , @@ -2092,7 +2094,7 @@ sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , @@ -2100,7 +2102,7 @@ sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -2117,7 +2119,7 @@ sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -2125,7 +2127,7 @@ sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -2133,7 +2135,7 @@ sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -2141,7 +2143,7 @@ sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -2149,7 +2151,7 @@ sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -2157,7 +2159,7 @@ sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , @@ -2165,7 +2167,7 @@ sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , @@ -2173,7 +2175,7 @@ sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -2220,7 +2222,7 @@ sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -2232,21 +2234,21 @@ sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 ( .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] , chanx_right_out[10] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_99 ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 ( .in ( { chanx_left_out[19] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , @@ -2267,37 +2269,37 @@ sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( chanx_right_out[11] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -2332,7 +2334,7 @@ sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , @@ -2345,18 +2347,17 @@ sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_118 ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) , @@ -2367,7 +2368,7 @@ sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[7] ) , +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) , .X ( chanx_left_out[9] ) ) ; @@ -2417,22 +2418,22 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_88 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_89 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1314 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_115 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_118 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_119 ) , .X ( SC_OUT_BOT ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v index 1a9debc..d6a6d62 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v @@ -13,7 +13,6 @@ output [0:2] mem_out ; input VDD ; input VSS ; -wire copt_net_105 ; supply1 VDD ; supply0 VSS ; @@ -21,23 +20,16 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_105 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_104 ) , - .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_105 ) , - .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_103 ) , - .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_101 ) , - .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_100 ) , - .X ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_109 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( mem_out[2] ) , + .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1295 ( .A ( copt_net_108 ) , + .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60,9 +52,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -83,6 +72,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -286,7 +277,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -307,6 +298,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -317,10 +311,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -350,10 +340,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -373,9 +363,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -386,6 +373,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -575,9 +566,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -591,6 +579,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -688,10 +678,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -923,10 +911,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -950,9 +938,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -977,6 +962,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1024,7 +1013,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1123,10 +1112,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1150,9 +1137,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1177,6 +1161,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1224,8 +1212,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1377,10 +1367,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1563,10 +1553,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1597,9 +1587,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1648,6 +1635,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1748,6 +1737,66 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1786,7 +1835,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , endmodule -module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:8] in ; input [0:3] sram ; @@ -1846,65 +1895,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , endmodule -module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; @@ -1917,7 +1907,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_99 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_130 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1927,18 +1917,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_96 ) , - .X ( copt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_97 ) , - .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_94 ) , - .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( ccff_head[0] ) , + .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_100 ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_104 ) , + .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_105 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_131 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1317 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2061,7 +2057,8 @@ input prog_clk_0_S_in ; input VDD ; input VSS ; -wire ropt_net_115 ; +wire ropt_net_118 ; +wire ropt_net_119 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -2134,7 +2131,7 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2148,7 +2145,7 @@ sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , @@ -2158,7 +2155,7 @@ sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -2168,7 +2165,7 @@ sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2195,7 +2192,7 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -2207,7 +2204,7 @@ sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , @@ -2227,7 +2224,7 @@ sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , @@ -2236,7 +2233,7 @@ sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -2254,7 +2251,7 @@ sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -2263,7 +2260,7 @@ sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -2272,7 +2269,7 @@ sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -2281,7 +2278,7 @@ sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -2290,7 +2287,7 @@ sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -2299,7 +2296,7 @@ sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , @@ -2308,7 +2305,7 @@ sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , @@ -2317,7 +2314,7 @@ sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -2365,7 +2362,7 @@ sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -2378,7 +2375,7 @@ sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 ( .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] , chanx_right_out[10] , chanx_left_in[19] } ) , @@ -2386,7 +2383,7 @@ sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 ( .in ( { chanx_left_out[19] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) , @@ -2394,7 +2391,7 @@ sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , @@ -2416,42 +2413,42 @@ sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -2487,7 +2484,7 @@ sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_89 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , @@ -2501,18 +2498,18 @@ sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_88 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) , @@ -2523,7 +2520,7 @@ sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[7] ) , +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) , .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2573,23 +2570,23 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_115 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1314 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_115 ) , +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , + .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , + .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_118 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_119 ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v index 8f5e6fb..490a2f5 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v @@ -11,27 +11,20 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -wire copt_net_105 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_105 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_104 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_105 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_103 ) , - .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_101 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_100 ) , - .X ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( copt_net_109 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( mem_out[2] ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 copt_h_inst_1295 ( .A ( copt_net_108 ) , + .X ( copt_net_109 ) ) ; endmodule @@ -49,8 +42,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -68,6 +59,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -215,7 +208,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -231,6 +224,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -239,9 +234,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_80 ) ) ; endmodule @@ -264,9 +256,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -281,8 +273,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -291,6 +281,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -433,8 +426,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -446,6 +437,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -521,9 +514,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -698,9 +690,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -719,8 +711,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -741,6 +731,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_79 ) ) ; endmodule @@ -779,7 +772,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -859,9 +852,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -880,8 +872,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -902,6 +892,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -940,8 +933,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -1062,9 +1056,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_71 ) ) ; endmodule @@ -1213,9 +1207,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .Y ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -1241,8 +1235,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1284,6 +1276,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1361,6 +1355,55 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1393,7 +1436,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , endmodule -module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1442,54 +1485,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , endmodule -module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; @@ -1497,7 +1492,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_99 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_130 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -1506,18 +1501,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_96 ) , - .X ( copt_net_94 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_97 ) , - .X ( copt_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( ccff_head[0] ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_94 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( ccff_head[0] ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_100 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_104 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_103 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1315 ( .A ( copt_net_105 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1316 ( .A ( ropt_net_131 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1317 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) ) ; endmodule @@ -1627,7 +1628,8 @@ input SC_IN_BOT ; output SC_OUT_BOT ; input prog_clk_0_S_in ; -wire ropt_net_115 ; +wire ropt_net_118 ; +wire ropt_net_119 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -1697,7 +1699,7 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1710,7 +1712,7 @@ sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , @@ -1719,7 +1721,7 @@ sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -1728,7 +1730,7 @@ sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1754,7 +1756,7 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -1765,7 +1767,7 @@ sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , @@ -1784,7 +1786,7 @@ sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , @@ -1792,7 +1794,7 @@ sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -1809,7 +1811,7 @@ sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -1817,7 +1819,7 @@ sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -1825,7 +1827,7 @@ sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -1833,7 +1835,7 @@ sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -1841,7 +1843,7 @@ sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -1849,7 +1851,7 @@ sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , @@ -1857,7 +1859,7 @@ sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , @@ -1865,7 +1867,7 @@ sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -1912,7 +1914,7 @@ sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -1924,21 +1926,21 @@ sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 ( .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] , chanx_right_out[10] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_99 ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 ( .in ( { chanx_left_out[19] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , @@ -1959,37 +1961,37 @@ sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( chanx_right_out[11] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -2024,7 +2026,7 @@ sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , @@ -2037,18 +2039,17 @@ sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_118 ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) , @@ -2059,7 +2060,7 @@ sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[7] ) , +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) , .X ( chanx_left_out[9] ) ) ; @@ -2109,22 +2110,22 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_88 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_89 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1314 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_115 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_118 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_119 ) , .X ( SC_OUT_BOT ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.top_only.pt.v index 6f52cd6..59fd876 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.top_only.pt.v @@ -58,7 +58,8 @@ input SC_IN_BOT ; output SC_OUT_BOT ; input prog_clk_0_S_in ; -wire ropt_net_115 ; +wire ropt_net_118 ; +wire ropt_net_119 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -128,7 +129,7 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -141,7 +142,7 @@ sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , @@ -150,7 +151,7 @@ sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -159,7 +160,7 @@ sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -185,7 +186,7 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -196,7 +197,7 @@ sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , @@ -215,7 +216,7 @@ sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , @@ -223,7 +224,7 @@ sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -240,7 +241,7 @@ sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , @@ -248,7 +249,7 @@ sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -256,7 +257,7 @@ sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -264,7 +265,7 @@ sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -272,7 +273,7 @@ sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -280,7 +281,7 @@ sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , @@ -288,7 +289,7 @@ sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , @@ -296,7 +297,7 @@ sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -343,7 +344,7 @@ sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -355,21 +356,21 @@ sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 ( .in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] , chanx_right_out[10] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_99 ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 ( .in ( { chanx_left_out[19] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , @@ -390,37 +391,37 @@ sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( chanx_right_out[11] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] , chanx_right_out[13] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] , chanx_right_out[14] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] , chanx_right_out[18] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , @@ -455,7 +456,7 @@ sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_89 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_95 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , @@ -468,18 +469,17 @@ sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_118 ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) , @@ -490,7 +490,7 @@ sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[7] ) , +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) , .X ( chanx_left_out[9] ) ) ; @@ -540,22 +540,22 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_88 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_89 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , - .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1314 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_115 ) , +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_118 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_119 ) , .X ( SC_OUT_BOT ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v index e9e57e7..4f9f9ac 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v @@ -11,19 +11,19 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_97 ; +wire copt_net_104 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_97 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_104 ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_98 ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_102 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_104 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) ) ; endmodule @@ -368,9 +368,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -395,14 +395,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_66 ) ) ; endmodule @@ -494,9 +493,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -526,9 +525,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -558,9 +557,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -585,13 +584,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -616,13 +616,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -652,9 +652,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -746,9 +746,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -804,13 +804,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -866,13 +867,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; endmodule @@ -902,8 +904,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -928,13 +931,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) ) ; endmodule @@ -959,13 +963,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1156,9 +1160,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_57 ) ) ; endmodule @@ -1184,8 +1188,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__0__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -1194,6 +1196,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1219,8 +1223,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__0__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -1229,6 +1231,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1338,9 +1342,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1382,9 +1385,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_52 ) ) ; endmodule @@ -1412,8 +1415,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_2__0__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1428,6 +1429,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_50 ) ) ; endmodule @@ -1469,8 +1473,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; endmodule @@ -1532,31 +1537,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_114 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_120 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( ccff_head[0] ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1251 ( .A ( copt_net_89 ) , - .X ( copt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_90 ) , - .X ( copt_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_88 ) , - .X ( copt_net_92 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( ropt_net_116 ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( copt_net_91 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_99 ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_98 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_97 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1282 ( .A ( copt_net_95 ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1283 ( .A ( ropt_net_121 ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1284 ( .A ( ropt_net_119 ) , + .X ( ropt_net_121 ) ) ; endmodule @@ -1602,9 +1607,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; endmodule @@ -1650,9 +1655,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1681,8 +1685,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_2__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1700,6 +1702,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_43 ) ) ; endmodule @@ -1787,7 +1792,7 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input prog_clk_0_N_in ; -wire ropt_net_104 ; +wire ropt_net_110 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -1867,7 +1872,7 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -1875,7 +1880,7 @@ sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -1883,7 +1888,7 @@ sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -1891,7 +1896,7 @@ sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1917,7 +1922,7 @@ sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -1925,7 +1930,7 @@ sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -1933,7 +1938,7 @@ sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -1941,7 +1946,7 @@ sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1966,25 +1971,25 @@ sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 ( chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -2009,112 +2014,112 @@ sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -2226,28 +2231,30 @@ sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[3] ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) ) ; sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[5] ) , +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_left_in[5] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , - .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , - .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_85 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_86 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[17] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v index 9277712..212b193 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v @@ -13,23 +13,23 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_97 ; +wire copt_net_104 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_97 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_98 ) , - .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_102 ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_104 ) , + .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -495,10 +495,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -517,16 +517,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -605,10 +604,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -633,10 +632,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -661,10 +660,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -683,6 +682,34 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -695,32 +722,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -742,10 +743,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -824,10 +825,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -873,15 +874,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -927,15 +929,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -960,8 +963,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -980,15 +985,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1007,15 +1013,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1215,10 +1220,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1238,9 +1243,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1251,6 +1253,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1270,9 +1274,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1283,6 +1284,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1413,10 +1416,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1455,10 +1456,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1480,9 +1481,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1500,6 +1498,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1538,8 +1540,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_48 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1624,7 +1628,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_114 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_120 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1632,24 +1636,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( ccff_head[0] ) , - .X ( copt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1251 ( .A ( copt_net_89 ) , - .X ( copt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_90 ) , - .X ( copt_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_88 ) , - .X ( copt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( ropt_net_116 ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( copt_net_91 ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_99 ) , + .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_98 ) , + .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , + .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_97 ) , + .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1282 ( .A ( copt_net_95 ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1283 ( .A ( ropt_net_121 ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1284 ( .A ( ropt_net_119 ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1692,10 +1696,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_46 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1738,10 +1742,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_43 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1764,9 +1766,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1787,6 +1786,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_43 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1874,7 +1877,7 @@ input prog_clk_0_N_in ; input VDD ; input VSS ; -wire ropt_net_104 ; +wire ropt_net_110 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -1957,7 +1960,7 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -1966,7 +1969,7 @@ sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -1975,7 +1978,7 @@ sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -1984,7 +1987,7 @@ sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2011,7 +2014,7 @@ sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -2020,7 +2023,7 @@ sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -2029,7 +2032,7 @@ sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -2038,7 +2041,7 @@ sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2064,28 +2067,28 @@ sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -2111,133 +2114,133 @@ sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_86 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_85 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -2350,28 +2353,30 @@ sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[3] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[5] ) , +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_left_in[5] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) , .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , - .HI ( optlc_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , - .HI ( optlc_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v index ca647ad..845eddd 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v @@ -11,19 +11,19 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_97 ; +wire copt_net_104 ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_97 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_104 ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_98 ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_102 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_104 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) ) ; endmodule @@ -357,9 +357,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -373,14 +373,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_66 ) ) ; endmodule @@ -439,9 +438,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -460,9 +459,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -481,9 +480,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -497,6 +496,27 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -507,26 +527,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -542,9 +542,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -603,9 +603,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_54 ( .A ( BUF_net_55 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_55 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -639,13 +639,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -679,13 +680,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; endmodule @@ -704,8 +706,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -719,13 +722,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_59 ( .A ( BUF_net_60 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_60 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_60 ) ) ; endmodule @@ -739,13 +743,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_58 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -892,9 +896,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_56 ( .A ( BUF_net_57 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_57 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_57 ) ) ; endmodule @@ -909,8 +913,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -919,6 +921,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_55 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -933,8 +937,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -943,6 +945,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_54 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1041,9 +1045,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_53 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1074,9 +1077,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_47 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_51 ( .A ( BUF_net_52 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_52 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_52 ) ) ; endmodule @@ -1093,8 +1096,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1109,6 +1110,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_49 ( .A ( BUF_net_50 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_50 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_50 ) ) ; endmodule @@ -1139,8 +1143,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_46 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_48 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_48 ) , .Y ( out[0] ) ) ; endmodule @@ -1202,31 +1207,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_114 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_120 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1250 ( .A ( ccff_head[0] ) , - .X ( copt_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1251 ( .A ( copt_net_89 ) , - .X ( copt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1252 ( .A ( copt_net_90 ) , - .X ( copt_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1253 ( .A ( copt_net_87 ) , - .X ( copt_net_90 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1254 ( .A ( copt_net_92 ) , - .X ( copt_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1255 ( .A ( copt_net_88 ) , - .X ( copt_net_92 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( ropt_net_116 ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( copt_net_91 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_99 ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_98 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_97 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1282 ( .A ( copt_net_95 ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1283 ( .A ( ropt_net_121 ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1284 ( .A ( ropt_net_119 ) , + .X ( ropt_net_121 ) ) ; endmodule @@ -1261,9 +1266,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_46 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_46 ) , .Y ( out[0] ) ) ; endmodule @@ -1298,9 +1303,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_44 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1318,8 +1322,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1337,6 +1339,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_42 ( .A ( BUF_net_43 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_43 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_43 ) ) ; endmodule @@ -1413,7 +1418,7 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input prog_clk_0_N_in ; -wire ropt_net_104 ; +wire ropt_net_110 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -1493,7 +1498,7 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -1501,7 +1506,7 @@ sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -1509,7 +1514,7 @@ sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -1517,7 +1522,7 @@ sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1543,7 +1548,7 @@ sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -1551,7 +1556,7 @@ sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -1559,7 +1564,7 @@ sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -1567,7 +1572,7 @@ sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1592,25 +1597,25 @@ sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 ( chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -1635,112 +1640,112 @@ sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -1852,28 +1857,30 @@ sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[3] ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) ) ; sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[5] ) , +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_left_in[5] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , - .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , - .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_85 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_86 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[17] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.top_only.pt.v index 64bf52f..7514188 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.top_only.pt.v @@ -40,7 +40,7 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input prog_clk_0_N_in ; -wire ropt_net_104 ; +wire ropt_net_110 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -120,7 +120,7 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -128,7 +128,7 @@ sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -136,7 +136,7 @@ sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , @@ -144,7 +144,7 @@ sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -170,7 +170,7 @@ sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , @@ -178,7 +178,7 @@ sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -186,7 +186,7 @@ sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , @@ -194,7 +194,7 @@ sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -219,25 +219,25 @@ sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 ( chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -262,112 +262,112 @@ sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_86 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_89 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ; sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_85 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_91 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_90 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -479,28 +479,30 @@ sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[3] ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) ) ; sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[5] ) , +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_left_in[5] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , - .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , - .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_85 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_86 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[17] ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v index 772e6bc..49721ab 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v @@ -11,25 +11,27 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_106 ; +wire copt_net_103 ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_103 ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_103 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_103 ) , .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_106 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_104 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( copt_net_105 ) , .X ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_107 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_104 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_108 ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , + .X ( copt_net_108 ) ) ; endmodule @@ -134,7 +136,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -160,13 +162,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__1__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -196,8 +198,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; endmodule @@ -222,13 +225,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__1__const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -258,9 +262,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) ) ; endmodule @@ -290,9 +294,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -393,8 +397,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__1__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -403,6 +405,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -436,8 +441,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -463,8 +469,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -473,6 +477,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -506,8 +512,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_82 ) ) ; endmodule @@ -687,8 +694,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -726,9 +734,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -755,8 +763,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_2__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -768,6 +774,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -844,9 +852,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -926,6 +934,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_2__1__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -943,9 +953,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) ) ; endmodule @@ -1021,6 +1028,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_2__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1038,9 +1047,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_69 ) ) ; endmodule @@ -1209,9 +1215,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -1261,7 +1267,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1292,8 +1298,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_2__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1314,6 +1318,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -1363,7 +1370,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1414,9 +1421,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_67 ) ) ; endmodule @@ -1466,9 +1473,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_65 ) ) ; endmodule @@ -1673,8 +1680,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_2__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1716,6 +1721,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_63 ) ) ; endmodule @@ -1803,8 +1811,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; sb_2__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1828,6 +1834,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_61 ) ) ; endmodule @@ -1967,7 +1976,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_112 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -1976,26 +1985,6 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( ccff_head[0] ) , - .X ( copt_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_97 ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_99 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1271 ( .A ( copt_net_100 ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1272 ( .A ( ropt_net_109 ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1273 ( .A ( ropt_net_110 ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , - .X ( ropt_net_112 ) ) ; endmodule @@ -2253,7 +2242,7 @@ sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , @@ -2263,7 +2252,7 @@ sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2281,7 +2270,7 @@ sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] , @@ -2289,7 +2278,7 @@ sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , @@ -2298,7 +2287,7 @@ sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2324,7 +2313,7 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , @@ -2336,7 +2325,7 @@ sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -2354,7 +2343,7 @@ sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] , @@ -2362,7 +2351,7 @@ sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , @@ -2370,7 +2359,7 @@ sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -2378,7 +2367,7 @@ sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -2386,7 +2375,7 @@ sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -2394,7 +2383,7 @@ sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -2402,7 +2391,7 @@ sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , @@ -2444,7 +2433,7 @@ sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , @@ -2452,7 +2441,7 @@ sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , @@ -2460,7 +2449,7 @@ sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -2484,7 +2473,7 @@ sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -2496,28 +2485,28 @@ sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 ( .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] , chanx_left_out[13] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 ( .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , @@ -2543,31 +2532,31 @@ sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_bottom_out[15] , chany_top_out[15] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_bottom_out[17] , chany_top_out[17] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_bottom_out[18] , chany_top_out[18] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_out[19] , chany_top_out[19] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , @@ -2597,32 +2586,32 @@ sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , @@ -2652,7 +2641,7 @@ sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) ) ; @@ -2708,14 +2697,14 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , - .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , + .HI ( optlc_net_101 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v index 9f48e31..da86adb 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v @@ -13,29 +13,31 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_106 ; +wire copt_net_103 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) , .VPWR ( VDD ) , + .CLK ( prog_clk[0] ) , .Q ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_103 ) , - .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_103 ) , .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_106 ) , - .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_104 ) , - .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( copt_net_105 ) , .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_107 ) , + .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_104 ) , + .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_108 ) , + .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , + .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -165,7 +167,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -185,15 +187,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -218,8 +219,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -238,15 +241,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -271,10 +275,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -299,10 +303,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -427,9 +431,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -440,6 +441,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -469,8 +474,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -490,9 +497,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -503,6 +507,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -532,8 +538,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -727,8 +735,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -762,10 +772,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -786,9 +796,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -802,6 +809,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -883,10 +892,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -978,6 +987,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -998,10 +1010,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1069,6 +1077,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1089,10 +1100,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1301,10 +1308,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1352,7 +1359,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1377,9 +1384,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1404,6 +1408,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1451,7 +1459,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1500,10 +1508,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1551,10 +1559,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1766,9 +1774,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1817,6 +1822,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1916,9 +1925,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1946,6 +1952,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2094,7 +2104,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_112 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2104,26 +2114,6 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( ccff_head[0] ) , - .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_97 ) , - .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_99 ) , - .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , - .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1271 ( .A ( copt_net_100 ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1272 ( .A ( ropt_net_109 ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1273 ( .A ( ropt_net_110 ) , - .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2386,7 +2376,7 @@ sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , @@ -2397,7 +2387,7 @@ sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2416,7 +2406,7 @@ sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] , @@ -2425,7 +2415,7 @@ sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , @@ -2435,7 +2425,7 @@ sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2462,7 +2452,7 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , @@ -2475,7 +2465,7 @@ sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -2494,7 +2484,7 @@ sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] , @@ -2503,7 +2493,7 @@ sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , @@ -2512,7 +2502,7 @@ sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -2521,7 +2511,7 @@ sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -2530,7 +2520,7 @@ sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -2539,7 +2529,7 @@ sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -2548,7 +2538,7 @@ sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , @@ -2591,7 +2581,7 @@ sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , @@ -2600,7 +2590,7 @@ sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , @@ -2609,7 +2599,7 @@ sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -2634,7 +2624,7 @@ sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -2647,7 +2637,7 @@ sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 ( .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] , chanx_left_out[13] } ) , @@ -2655,7 +2645,7 @@ sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , @@ -2663,7 +2653,7 @@ sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 ( .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , @@ -2671,7 +2661,7 @@ sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , @@ -2698,35 +2688,35 @@ sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_bottom_out[15] , chany_top_out[15] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_bottom_out[17] , chany_top_out[17] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_bottom_out[18] , chany_top_out[18] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_out[19] , chany_top_out[19] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , @@ -2757,37 +2747,37 @@ sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , @@ -2818,7 +2808,7 @@ sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2874,14 +2864,14 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) , .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , - .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , - .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , - .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v index eae86ad..fe91aff 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v @@ -11,25 +11,27 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_106 ; +wire copt_net_103 ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_106 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( copt_net_103 ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_103 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_103 ) , .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_106 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_104 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1277 ( .A ( copt_net_105 ) , .X ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( copt_net_107 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_104 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_108 ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1282 ( .A ( copt_net_102 ) , + .X ( copt_net_108 ) ) ; endmodule @@ -123,7 +125,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -138,13 +140,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -163,8 +165,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; endmodule @@ -178,13 +181,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -203,9 +207,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) ) ; endmodule @@ -224,9 +228,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -316,8 +320,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -326,6 +328,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -348,8 +353,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -364,8 +370,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -374,6 +378,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -396,8 +402,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_82 ) ) ; endmodule @@ -544,8 +551,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -572,9 +580,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -590,8 +598,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -603,6 +609,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -668,9 +676,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -739,6 +747,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -756,9 +766,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_71 ) ) ; endmodule @@ -812,6 +819,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -829,9 +838,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_69 ) ) ; endmodule @@ -989,9 +995,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_73 ) ) ; endmodule @@ -1030,7 +1036,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1050,8 +1056,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1072,6 +1076,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -1110,7 +1117,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1150,9 +1157,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_67 ) ) ; endmodule @@ -1191,9 +1198,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_65 ) ) ; endmodule @@ -1365,8 +1372,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1408,6 +1413,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .Y ( BUF_net_63 ) ) ; endmodule @@ -1484,8 +1492,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1509,6 +1515,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_61 ) ) ; endmodule @@ -1626,7 +1635,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_112 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; @@ -1635,26 +1644,6 @@ sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( ccff_head[0] ) , - .X ( copt_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_97 ) , - .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_98 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_99 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_96 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1271 ( .A ( copt_net_100 ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1272 ( .A ( ropt_net_109 ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1273 ( .A ( ropt_net_110 ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , - .X ( ropt_net_112 ) ) ; endmodule @@ -1890,7 +1879,7 @@ sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , @@ -1900,7 +1889,7 @@ sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1918,7 +1907,7 @@ sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] , @@ -1926,7 +1915,7 @@ sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , @@ -1935,7 +1924,7 @@ sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1961,7 +1950,7 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , @@ -1973,7 +1962,7 @@ sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -1991,7 +1980,7 @@ sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] , @@ -1999,7 +1988,7 @@ sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , @@ -2007,7 +1996,7 @@ sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -2015,7 +2004,7 @@ sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -2023,7 +2012,7 @@ sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -2031,7 +2020,7 @@ sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -2039,7 +2028,7 @@ sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , @@ -2081,7 +2070,7 @@ sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , @@ -2089,7 +2078,7 @@ sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , @@ -2097,7 +2086,7 @@ sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -2121,7 +2110,7 @@ sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -2133,28 +2122,28 @@ sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 ( .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] , chanx_left_out[13] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 ( .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , @@ -2180,31 +2169,31 @@ sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_bottom_out[15] , chany_top_out[15] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_bottom_out[17] , chany_top_out[17] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_bottom_out[18] , chany_top_out[18] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_out[19] , chany_top_out[19] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , @@ -2234,32 +2223,32 @@ sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , @@ -2289,7 +2278,7 @@ sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) ) ; @@ -2345,14 +2334,14 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , - .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , + .HI ( optlc_net_101 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.top_only.pt.v index ca4919d..3aad7b2 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.top_only.pt.v @@ -132,7 +132,7 @@ sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .in ( { chany_bottom_out[3] , chany_bottom_out[13] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , @@ -142,7 +142,7 @@ sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -160,7 +160,7 @@ sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] , @@ -168,7 +168,7 @@ sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .in ( { chany_bottom_out[7] , chany_bottom_out[17] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , @@ -177,7 +177,7 @@ sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -203,7 +203,7 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_out[15] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , @@ -215,7 +215,7 @@ sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -233,7 +233,7 @@ sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] , @@ -241,7 +241,7 @@ sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .in ( { chany_bottom_out[9] , chany_bottom_out[18] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , @@ -249,7 +249,7 @@ sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -257,7 +257,7 @@ sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -265,7 +265,7 @@ sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -273,7 +273,7 @@ sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] , chanx_left_out[13] , left_bottom_grid_pin_37_[0] , @@ -281,7 +281,7 @@ sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , @@ -323,7 +323,7 @@ sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .in ( { chany_bottom_out[10] , chany_bottom_out[19] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , @@ -331,7 +331,7 @@ sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , @@ -339,7 +339,7 @@ sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -363,7 +363,7 @@ sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_101 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , @@ -375,28 +375,28 @@ sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 ( .in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] , chanx_left_out[13] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( .in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 ( .in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , @@ -422,31 +422,31 @@ sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_bottom_out[15] , chany_top_out[15] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_bottom_out[17] , chany_top_out[17] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_bottom_out[18] , chany_top_out[18] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_out[19] , chany_top_out[19] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , @@ -476,32 +476,32 @@ sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_100 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_98 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , @@ -531,7 +531,7 @@ sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) ) ; @@ -587,14 +587,14 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , - .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) , + .HI ( optlc_net_101 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v index 3aae9b6..9512a4a 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v @@ -71,6 +71,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -79,9 +81,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_91 ) ) ; endmodule @@ -115,9 +114,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -151,7 +150,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -163,19 +162,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_102 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_102 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_107 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_105 ) , - .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( copt_net_102 ) , - .X ( copt_net_107 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( copt_net_99 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_102 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( mem_out[1] ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; endmodule @@ -581,9 +578,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; endmodule @@ -675,9 +672,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -707,8 +703,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -795,13 +792,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -826,14 +823,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_81 ) ) ; endmodule @@ -863,7 +859,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -894,9 +890,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -926,9 +921,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -953,13 +948,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1016,13 +1011,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -1047,13 +1042,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1583,31 +1578,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_109 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1257 ( .A ( copt_net_95 ) , + .X ( copt_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_91 ) , + .X ( copt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_93 ) , .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_96 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_100 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_98 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_99 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( copt_net_101 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( ropt_net_117 ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1275 ( .A ( copt_net_92 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1276 ( .A ( ropt_net_110 ) , + .X ( ropt_net_111 ) ) ; endmodule @@ -1923,7 +1918,7 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -1931,7 +1926,7 @@ sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -1939,7 +1934,7 @@ sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -1947,7 +1942,7 @@ sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1973,7 +1968,7 @@ sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , @@ -1981,7 +1976,7 @@ sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -1989,7 +1984,7 @@ sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -1997,7 +1992,7 @@ sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2021,122 +2016,122 @@ sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -2261,19 +2256,19 @@ sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -2302,14 +2297,14 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[18] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) , .X ( chany_bottom_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , - .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_87 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_88 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , + .HI ( optlc_net_90 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v index b2dab06..6a6a974 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v @@ -83,6 +83,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -93,10 +96,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -126,10 +125,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -159,7 +158,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -173,23 +172,21 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_102 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_102 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( copt_net_99 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_107 ) , - .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_105 ) , - .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( copt_net_102 ) , - .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_102 ) , + .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( mem_out[1] ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -724,10 +721,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -806,10 +803,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -834,8 +829,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -908,15 +905,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -935,16 +931,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -969,7 +964,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -995,10 +990,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1023,10 +1016,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1045,14 +1038,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1099,15 +1093,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1126,14 +1119,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1674,7 +1668,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_109 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1682,24 +1676,24 @@ sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1257 ( .A ( copt_net_95 ) , + .X ( copt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_91 ) , + .X ( copt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_93 ) , .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_96 ) , - .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_100 ) , - .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_98 ) , - .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_99 ) , - .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( copt_net_101 ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( ropt_net_117 ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , + .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1275 ( .A ( copt_net_92 ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1276 ( .A ( ropt_net_110 ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2012,7 +2006,7 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -2021,7 +2015,7 @@ sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -2030,7 +2024,7 @@ sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -2039,7 +2033,7 @@ sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2066,7 +2060,7 @@ sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , @@ -2075,7 +2069,7 @@ sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -2084,7 +2078,7 @@ sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -2093,7 +2087,7 @@ sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2118,145 +2112,145 @@ sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -2383,21 +2377,21 @@ sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -2427,14 +2421,14 @@ sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , - .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , - .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , + .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v index 57e0e57..c0e4f01 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v @@ -60,6 +60,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -68,9 +70,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_91 ) ) ; endmodule @@ -93,9 +92,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -118,7 +117,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -130,19 +129,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_102 ; - sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( copt_net_102 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_107 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_105 ) , - .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( copt_net_102 ) , - .X ( copt_net_107 ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( copt_net_99 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_102 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( mem_out[1] ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; endmodule @@ -526,9 +523,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; endmodule @@ -587,9 +584,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -608,8 +604,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -663,13 +660,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -683,14 +680,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_81 ) ) ; endmodule @@ -709,7 +705,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -729,9 +725,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -750,9 +745,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) ) ; endmodule @@ -766,13 +761,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -807,13 +802,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -827,13 +822,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -1242,31 +1237,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_116 ) , +sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ropt_net_109 ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1257 ( .A ( copt_net_95 ) , + .X ( copt_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_91 ) , + .X ( copt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( ccff_head[0] ) , + .X ( copt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_93 ) , .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_96 ) , - .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_100 ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_98 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_99 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1277 ( .A ( copt_net_101 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1278 ( .A ( ropt_net_117 ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1279 ( .A ( ropt_net_115 ) , - .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1274 ( .A ( ropt_net_111 ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1275 ( .A ( copt_net_92 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1276 ( .A ( ropt_net_110 ) , + .X ( ropt_net_111 ) ) ; endmodule @@ -1538,7 +1533,7 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -1546,7 +1541,7 @@ sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -1554,7 +1549,7 @@ sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -1562,7 +1557,7 @@ sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1588,7 +1583,7 @@ sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , @@ -1596,7 +1591,7 @@ sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -1604,7 +1599,7 @@ sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -1612,7 +1607,7 @@ sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1636,122 +1631,122 @@ sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -1876,19 +1871,19 @@ sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -1917,14 +1912,14 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[18] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) , .X ( chany_bottom_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , - .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_87 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_88 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , + .HI ( optlc_net_90 ) ) ; endmodule diff --git a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.top_only.pt.v b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.top_only.pt.v index 6b643cc..2313b24 100644 --- a/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.top_only.pt.v @@ -124,7 +124,7 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , @@ -132,7 +132,7 @@ sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -140,7 +140,7 @@ sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -148,7 +148,7 @@ sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -174,7 +174,7 @@ sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , @@ -182,7 +182,7 @@ sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -190,7 +190,7 @@ sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , @@ -198,7 +198,7 @@ sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -222,122 +222,122 @@ sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_95 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_90 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_87 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -462,19 +462,19 @@ sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -503,14 +503,14 @@ sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[18] ) , sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) , .X ( chany_bottom_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , - .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_87 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_88 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) , + .HI ( optlc_net_90 ) ) ; endmodule