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[Script] Update script due to deprecation of 'write_verilog_testbench'

This commit is contained in:
tangxifan 2021-06-09 19:43:28 -06:00
parent 51a00d4612
commit 56dd34da86
1 changed files with 5 additions and 8 deletions
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13
FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga
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@ -44,13 +44,10 @@ build_fabric_bitstream
write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
write_fabric_bitstream --format xml --file fabric_bitstream.xml
write_verilog_testbench \
--file ./SRC \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ./SimulationDeck/simulation_deck.ini \
--explicit_port_mapping
write_full_testbench --file ./SRC \
--bitstream fabric_bitstream.bit
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--explicit_port_mapping
# Finish and exit OpenFPGA
exit
exit