Updated design with new GDS nad updated verilog netlist

FPGA1212_SOFA_CHD_PNR/config.sh

@@ -2,7 +2,7 @@
 # = = = = = = = = = = = = = = Variables Sections  = = = = = = = = = = = = = = =
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 
-export PROJ_NAME=FPGA1212_SOFA_CHD # Project Name
+export PROJ_NAME=FPGA1212_QLSOFA_CHD # Project Name
 export FPGA_SIZE_X=12        # Grid X Size
 export FPGA_SIZE_Y=12        # Grid Y Size
 # Design Style [hier/flat], mostly hier
@@ -24,7 +24,7 @@ export DIE_DIMENSION=3200
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 # Derived Or Fixed Variables
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-export OPENFPGA_ENGINE_PATH=/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip
+export OPENFPGA_ENGINE_PATH=${OPENFPGA_PATH}
 export TASK_DIR_NAME=${PROJ_NAME}_task
 export VERILOG_PROJ_DIR=${PROJ_NAME}_Verilog
 export SPY_HACK_FILE=${TASK_DIR_NAME}/spy_hack.txt
@@ -33,6 +33,8 @@ export RESTRUCT_NETLIST=../utils/RestructureNetlistSkywater.py
 export POST_GENERATION_SCRIPT=./generate_scandef_and_case_analysis.sh
 export MODULE_ADJUST=./adjust_module.sh
 
+export TAPEOUT_DIRECTORY=/research/ece/lnis/USERS/DARPA_ERI/Tapeout/SOFA
+export TAPEOUT_SCRIPT=
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 # Restructure Netlist Varaibles
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v

@@ -9362,15 +9362,15 @@ wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign Test_en_S_in = Test_en_E_in ;
+assign Test_en_E_in = Test_en_S_in ;
-assign Test_en_W_in = Test_en_E_in ;
+assign Test_en_E_in = Test_en_W_in ;
-assign Reset_S_in = Reset_E_in ;
+assign Reset_E_in = Reset_S_in ;
-assign Reset_W_in = Reset_E_in ;
+assign Reset_E_in = Reset_W_in ;
 assign prog_clk_0 = prog_clk[0] ;
-assign prog_clk_2_N_in = prog_clk_2_S_in ;
+assign prog_clk_2_S_in = prog_clk_2_N_in ;
-assign prog_clk_3_S_in = prog_clk_3_N_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
-assign clk_2_N_in = clk_2_S_in ;
+assign clk_2_S_in = clk_2_N_in ;
-assign clk_3_S_in = clk_3_N_in ;
+assign clk_3_N_in = clk_3_S_in ;
 
 cby_1__1__mux_2level_size12_0 mux_right_ipin_0 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
@@ -15172,7 +15172,7 @@ wire [0:0] mux_2level_size12_mem_8_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign pReset_E_in = pReset_W_in ;
+assign pReset_W_in = pReset_E_in ;
 assign prog_clk_0 = prog_clk[0] ;
 
 cbx_1__2__mux_2level_size12_0 mux_bottom_ipin_0 (
@@ -19906,14 +19906,14 @@ wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign pReset_E_in = pReset_W_in ;
+assign pReset_W_in = pReset_E_in ;
 assign prog_clk_0 = prog_clk[0] ;
-assign prog_clk_1_W_in = prog_clk_1_E_in ;
+assign prog_clk_1_E_in = prog_clk_1_W_in ;
-assign prog_clk_2_E_in = prog_clk_2_W_in ;
+assign prog_clk_2_W_in = prog_clk_2_E_in ;
-assign prog_clk_3_W_in = prog_clk_3_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
-assign clk_1_W_in = clk_1_E_in ;
+assign clk_1_E_in = clk_1_W_in ;
-assign clk_2_E_in = clk_2_W_in ;
+assign clk_2_W_in = clk_2_E_in ;
-assign clk_3_W_in = clk_3_E_in ;
+assign clk_3_E_in = clk_3_W_in ;
 
 cbx_1__1__mux_2level_size12_0 mux_top_ipin_0 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
@@ -23925,7 +23925,7 @@ wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign pReset_E_in = pReset_W_in ;
+assign pReset_W_in = pReset_E_in ;
 assign prog_clk_0 = prog_clk[0] ;
 
 cbx_1__0__mux_2level_size12_0 mux_top_ipin_0 (
@@ -56568,8 +56568,8 @@ wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign pReset_S_in = pReset_E_in ;
+assign pReset_E_in = pReset_S_in ;
-assign pReset_W_in = pReset_E_in ;
+assign pReset_E_in = pReset_W_in ;
 assign prog_clk_0 = prog_clk[0] ;
 
 sb_1__2__mux_2level_tapbuf_size7_0 mux_right_track_0 (
@@ -68255,23 +68255,23 @@ assign clk_3_E_out = clk_3_E_in ;
 assign clk_3_W_out = clk_3_E_in ;
 assign clk_3_N_out = clk_3_E_in ;
 assign clk_3_S_out = clk_3_E_in ;
-assign pReset_S_in = pReset_E_in ;
+assign pReset_E_in = pReset_S_in ;
-assign pReset_W_in = pReset_E_in ;
+assign pReset_E_in = pReset_W_in ;
 assign prog_clk_0 = prog_clk[0] ;
-assign prog_clk_1_N_in = prog_clk_1_S_in ;
+assign prog_clk_1_S_in = prog_clk_1_N_in ;
-assign prog_clk_2_N_in = prog_clk_2_E_in ;
+assign prog_clk_2_E_in = prog_clk_2_N_in ;
-assign prog_clk_2_S_in = prog_clk_2_E_in ;
+assign prog_clk_2_E_in = prog_clk_2_S_in ;
-assign prog_clk_2_W_in = prog_clk_2_E_in ;
+assign prog_clk_2_E_in = prog_clk_2_W_in ;
-assign prog_clk_3_W_in = prog_clk_3_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
-assign prog_clk_3_S_in = prog_clk_3_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_S_in ;
-assign prog_clk_3_N_in = prog_clk_3_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_N_in ;
-assign clk_1_N_in = clk_1_S_in ;
+assign clk_1_S_in = clk_1_N_in ;
-assign clk_2_N_in = clk_2_E_in ;
+assign clk_2_E_in = clk_2_N_in ;
-assign clk_2_S_in = clk_2_E_in ;
+assign clk_2_E_in = clk_2_S_in ;
-assign clk_2_W_in = clk_2_E_in ;
+assign clk_2_E_in = clk_2_W_in ;
-assign clk_3_W_in = clk_3_E_in ;
+assign clk_3_E_in = clk_3_W_in ;
-assign clk_3_S_in = clk_3_E_in ;
+assign clk_3_E_in = clk_3_S_in ;
-assign clk_3_N_in = clk_3_E_in ;
+assign clk_3_E_in = clk_3_N_in ;
 
 sb_1__1__mux_2level_tapbuf_size11_0 mux_top_track_0 (
     .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , 
@@ -77795,8 +77795,8 @@ wire [0:0] mux_2level_tapbuf_size9_mem_2_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign pReset_S_in = pReset_E_in ;
+assign pReset_E_in = pReset_S_in ;
-assign pReset_W_in = pReset_E_in ;
+assign pReset_E_in = pReset_W_in ;
 assign prog_clk_0 = prog_clk[0] ;
 
 sb_1__0__mux_2level_tapbuf_size7_0 mux_top_track_0 (
@@ -106236,13 +106236,13 @@ wire [0:0] Test_en ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign SC_IN_TOP = SC_IN_BOT ;
+assign SC_IN_BOT = SC_IN_TOP ;
-assign Test_en_E_in = Test_en_W_in ;
+assign Test_en_W_in = Test_en_E_in ;
-assign Reset_E_in = Reset_W_in ;
+assign Reset_W_in = Reset_E_in ;
 assign prog_clk[0] = prog_clk_0 ;
-assign prog_clk_0_N_in = prog_clk_0_S_in ;
+assign prog_clk_0_S_in = prog_clk_0_N_in ;
 assign clk_0 = clk[0] ;
-assign clk_0_N_in = clk_0_S_in ;
+assign clk_0_S_in = clk_0_N_in ;
 
 grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( 
     .pReset ( pReset ) ,

FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v

@@ -3475,13 +3475,13 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign Test_en_S_in = Test_en_E_in ;
+assign Test_en_E_in = Test_en_S_in ;
-assign Test_en_W_in = Test_en_E_in ;
+assign Test_en_E_in = Test_en_W_in ;
 assign prog_clk_0 = prog_clk[0] ;
-assign prog_clk_2_N_in = prog_clk_2_S_in ;
+assign prog_clk_2_S_in = prog_clk_2_N_in ;
-assign prog_clk_3_S_in = prog_clk_3_N_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
-assign clk_2_N_in = clk_2_S_in ;
+assign clk_2_S_in = clk_2_N_in ;
-assign clk_3_S_in = clk_3_N_in ;
+assign clk_3_N_in = clk_3_S_in ;
 
 cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
@@ -7723,12 +7723,12 @@ supply1 VDD ;
 supply0 VSS ;
 
 assign prog_clk_0 = prog_clk[0] ;
-assign prog_clk_1_W_in = prog_clk_1_E_in ;
+assign prog_clk_1_E_in = prog_clk_1_W_in ;
-assign prog_clk_2_E_in = prog_clk_2_W_in ;
+assign prog_clk_2_W_in = prog_clk_2_E_in ;
-assign prog_clk_3_W_in = prog_clk_3_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
-assign clk_1_W_in = clk_1_E_in ;
+assign clk_1_E_in = clk_1_W_in ;
-assign clk_2_E_in = clk_2_W_in ;
+assign clk_2_W_in = clk_2_E_in ;
-assign clk_3_W_in = clk_3_E_in ;
+assign clk_3_E_in = clk_3_W_in ;
 
 cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
@@ -23500,20 +23500,20 @@ assign clk_3_W_out = clk_3_E_in ;
 assign clk_3_N_out = clk_3_E_in ;
 assign clk_3_S_out = clk_3_E_in ;
 assign prog_clk_0 = prog_clk[0] ;
-assign prog_clk_1_N_in = prog_clk_1_S_in ;
+assign prog_clk_1_S_in = prog_clk_1_N_in ;
-assign prog_clk_2_N_in = prog_clk_2_E_in ;
+assign prog_clk_2_E_in = prog_clk_2_N_in ;
-assign prog_clk_2_S_in = prog_clk_2_E_in ;
+assign prog_clk_2_E_in = prog_clk_2_S_in ;
-assign prog_clk_2_W_in = prog_clk_2_E_in ;
+assign prog_clk_2_E_in = prog_clk_2_W_in ;
-assign prog_clk_3_W_in = prog_clk_3_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
-assign prog_clk_3_S_in = prog_clk_3_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_S_in ;
-assign prog_clk_3_N_in = prog_clk_3_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_N_in ;
-assign clk_1_N_in = clk_1_S_in ;
+assign clk_1_S_in = clk_1_N_in ;
-assign clk_2_N_in = clk_2_E_in ;
+assign clk_2_E_in = clk_2_N_in ;
-assign clk_2_S_in = clk_2_E_in ;
+assign clk_2_E_in = clk_2_S_in ;
-assign clk_2_W_in = clk_2_E_in ;
+assign clk_2_E_in = clk_2_W_in ;
-assign clk_3_W_in = clk_3_E_in ;
+assign clk_3_E_in = clk_3_W_in ;
-assign clk_3_S_in = clk_3_E_in ;
+assign clk_3_E_in = clk_3_S_in ;
-assign clk_3_N_in = clk_3_E_in ;
+assign clk_3_E_in = clk_3_N_in ;
 
 sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 (
     .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , 
@@ -38417,12 +38417,12 @@ wire [0:0] Test_en ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign SC_IN_TOP = SC_IN_BOT ;
+assign SC_IN_BOT = SC_IN_TOP ;
-assign Test_en_E_in = Test_en_W_in ;
+assign Test_en_W_in = Test_en_E_in ;
 assign prog_clk[0] = prog_clk_0 ;
-assign prog_clk_0_N_in = prog_clk_0_S_in ;
+assign prog_clk_0_S_in = prog_clk_0_N_in ;
 assign clk_0 = clk[0] ;
-assign clk_0_N_in = clk_0_S_in ;
+assign clk_0_S_in = clk_0_N_in ;
 
 grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
     .prog_clk ( { prog_clk_0 } ) ,