From 5474ff53c5ccf1b419b927d67ecc082f691ca19e Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Sun, 6 Dec 2020 21:41:06 -0700
Subject: [PATCH] [Fixup] Merge conflict with master

---
 ...n_chain_skywater130nm_fdhd_cc_openfpga.xml | 270 ------------------
 ...n_chain_skywater130nm_fdhs_cc_openfpga.xml | 270 ------------------
 ..._chain_skywater130nm_fdhvl_cc_openfpga.xml | 270 ------------------
 ...n_chain_skywater130nm_fdls_cc_openfpga.xml | 270 ------------------
 ...n_chain_skywater130nm_fdms_cc_openfpga.xml | 270 ------------------
 ...hain_skywater130nm_ndafdms_cc_openfpga.xml | 269 -----------------
 ...n_chain_skywater130nm_fdhd_cc_openfpga.xml | 255 -----------------
 ..._io_skywater130nm_customhd_cc_openfpga.xml |  30 +-
 README.md                                     |  16 +-
 9 files changed, 29 insertions(+), 1891 deletions(-)
 delete mode 100644 ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
 delete mode 100644 ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml
 delete mode 100644 ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml
 delete mode 100644 ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml
 delete mode 100644 ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
 delete mode 100644 ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml
 delete mode 100644 ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
deleted file mode 100644
index e6d1b24..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ /dev/null
@@ -1,270 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k4_frac_cc_sky130nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-     - Skywater 130nm PDK
-       - circuit models are binded to the opensource skywater 
-         foundry middle-speed (ms) standard cell library
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-   <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
-      <design_technology type="cmos" topology="buffer" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
-      <design_technology type="cmos" topology="OR"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <!-- Define a circuit model for the standard cell MUX2 
-         OpenFPGA requires the following truth table for the MUX2
-         When the select signal sel is enabled, the first input, i.e., in0 
-         will be propagated to the output, i.e., out
-         If your standard cell provider does not offer the exact truth table,
-         you can simply swap the inputs as shown in the example below
-      -->
-    <circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
-      <design_technology type="cmos" topology="MUX2"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in0" lib_name="A1" size="1"/>
-      <port type="input" prefix="in1" lib_name="A0" size="1"/>
-      <port type="input" prefix="sel" lib_name="S" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfrtp_1" prefix="sky130_fd_sc_hd__sdfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="DI" lib_name="SCD" size="1"/>
-       <port type="input" prefix="TESTEN" lib_name="SCE" size="1" is_global="true" default_val="0"/>
-       <port type="input" prefix="reset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
-      <lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
-      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
-      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrbp_1" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sky130_fd_sc_hd__dfrbp_1" prefix="sky130_fd_sc_hd__dfrbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrbp/sky130_fd_sc_hd__dfrbp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-       <port type="input" prefix="pReset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="QN" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrbp_1" default_val="1"/>
-      <port type="input" prefix="outpad" lib_name="A" size="1"/>
-      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="sky130_fd_sc_hd__fah_1" prefix="sky130_fd_sc_hd__fah_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fah/sky130_fd_sc_hd__fah_1.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="input" prefix="cin" lib_name="CI" size="1"/>
-      <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
-      <port type="output" prefix="cout" lib_name="COUT" size="1"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfrbp_1" num_regions="4"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L1" circuit_model_name="chan_segment"/>
-    <segment name="L2" circuit_model_name="chan_segment"/>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfrtp_1"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="sky130_fd_sc_hd__fah_1"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut4 to the first 3 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble4' -->
-    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- Binding operating pb_types in mode 'shift_register' -->
-    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- End physical pb_type binding in complex block IO -->
-  </pb_type_annotations>
-</openfpga_architecture>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml
deleted file mode 100644
index 9880c7a..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhs_cc_openfpga.xml
+++ /dev/null
@@ -1,270 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k4_frac_cc_sky130nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-     - Skywater 130nm PDK
-       - circuit models are binded to the opensource skywater 
-         foundry middle-speed (ms) standard cell library
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hs__inv_1" prefix="sky130_fd_sc_hs__inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/inv/sky130_fd_sc_hs__inv_1.v">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-   <circuit_model type="inv_buf" name="sky130_fd_sc_hs__buf_2" prefix="sky130_fd_sc_hs__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/buf/sky130_fd_sc_hs__buf_2.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hs__buf_4" prefix="sky130_fd_sc_hs__buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/buf/sky130_fd_sc_hs__buf_4.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hs__inv_2" prefix="sky130_fd_sc_hs__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/inv/sky130_fd_sc_hs__inv_2.v">
-      <design_technology type="cmos" topology="buffer" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="sky130_fd_sc_hs__or2_1" prefix="sky130_fd_sc_hs__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/or2/sky130_fd_sc_hs__or2_1.v">
-      <design_technology type="cmos" topology="OR"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <!-- Define a circuit model for the standard cell MUX2 
-         OpenFPGA requires the following truth table for the MUX2
-         When the select signal sel is enabled, the first input, i.e., in0 
-         will be propagated to the output, i.e., out
-         If your standard cell provider does not offer the exact truth table,
-         you can simply swap the inputs as shown in the example below
-      -->
-    <circuit_model type="gate" name="sky130_fd_sc_hs__mux2_1" prefix="sky130_fd_sc_hs__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/mux2/sky130_fd_sc_hs__mux2_1.v">
-      <design_technology type="cmos" topology="MUX2"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in0" lib_name="A1" size="1"/>
-      <port type="input" prefix="in1" lib_name="A0" size="1"/>
-      <port type="input" prefix="sel" lib_name="S" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hs__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__buf_4"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hs__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="sky130_fd_sc_hs__sdfrtp_1" prefix="sky130_fd_sc_hs__sdfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
-       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="DI" lib_name="SCD" size="1"/>
-       <port type="input" prefix="TESTEN" lib_name="SCE" size="1" is_global="true" default_val="0"/>
-       <port type="input" prefix="reset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__buf_2"/>
-      <lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
-      <lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__buf_2"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__buf_2" location_map="-1-"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hs__mux2_1"/>
-      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hs__or2_1"/>
-      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hs__dfrbp_1" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sky130_fd_sc_hs__dfrbp_1" prefix="sky130_fd_sc_hs__dfrbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
-       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
-       <port type="input" prefix="pReset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="QN" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hs__dfrbp_1" default_val="1"/>
-      <port type="input" prefix="outpad" lib_name="A" size="1"/>
-      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="sky130_fd_sc_hs__fah_1" prefix="sky130_fd_sc_hs__fah_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/fah/sky130_fd_sc_hs__fah_1.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hs__inv_1"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="input" prefix="cin" lib_name="CI" size="1"/>
-      <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
-      <port type="output" prefix="cout" lib_name="COUT" size="1"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sky130_fd_sc_hs__dfrbp_1" num_regions="4"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L1" circuit_model_name="chan_segment"/>
-    <segment name="L2" circuit_model_name="chan_segment"/>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hs__sdfrtp_1"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="sky130_fd_sc_hs__fah_1"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut4 to the first 3 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble4' -->
-    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- Binding operating pb_types in mode 'shift_register' -->
-    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- End physical pb_type binding in complex block IO -->
-  </pb_type_annotations>
-</openfpga_architecture>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml
deleted file mode 100644
index a5efd99..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdhvl_cc_openfpga.xml
+++ /dev/null
@@ -1,270 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k4_frac_cc_sky130nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-     - Skywater 130nm PDK
-       - circuit models are binded to the opensource skywater 
-         foundry middle-speed (ms) standard cell library
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hvl__inv_1" prefix="sky130_fd_sc_hvl__inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hvl/latest/cells/inv/sky130_fd_sc_hvl__inv_1.v">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-   <circuit_model type="inv_buf" name="sky130_fd_sc_hvl__buf_2" prefix="sky130_fd_sc_hvl__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hvl/latest/cells/buf/sky130_fd_sc_hvl__buf_2.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hvl__buf_4" prefix="sky130_fd_sc_hvl__buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hvl/latest/cells/buf/sky130_fd_sc_hvl__buf_4.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hvl__inv_2" prefix="sky130_fd_sc_hvl__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hvl/latest/cells/inv/sky130_fd_sc_hvl__inv_2.v">
-      <design_technology type="cmos" topology="buffer" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="sky130_fd_sc_hvl__or2_1" prefix="sky130_fd_sc_hvl__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hvl/latest/cells/or2/sky130_fd_sc_hvl__or2_1.v">
-      <design_technology type="cmos" topology="OR"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <!-- Define a circuit model for the standard cell MUX2 
-         OpenFPGA requires the following truth table for the MUX2
-         When the select signal sel is enabled, the first input, i.e., in0 
-         will be propagated to the output, i.e., out
-         If your standard cell provider does not offer the exact truth table,
-         you can simply swap the inputs as shown in the example below
-      -->
-    <circuit_model type="gate" name="sky130_fd_sc_hvl__mux2_1" prefix="sky130_fd_sc_hvl__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hvl/latest/cells/mux2/sky130_fd_sc_hvl__mux2_1.v">
-      <design_technology type="cmos" topology="MUX2"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in0" lib_name="A1" size="1"/>
-      <port type="input" prefix="in1" lib_name="A0" size="1"/>
-      <port type="input" prefix="sel" lib_name="S" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hvl__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__buf_4"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hvl__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="sky130_fd_sc_hvl__sdfrtp_1" prefix="sky130_fd_sc_hvl__sdfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hvl/latest/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
-       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="DI" lib_name="SCD" size="1"/>
-       <port type="input" prefix="TESTEN" lib_name="SCE" size="1" is_global="true" default_val="0"/>
-       <port type="input" prefix="reset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__buf_2"/>
-      <lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
-      <lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__buf_2"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__buf_2" location_map="-1-"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hvl__mux2_1"/>
-      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hvl__or2_1"/>
-      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hvl__dfrbp_1" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sky130_fd_sc_hvl__dfrbp_1" prefix="sky130_fd_sc_hvl__dfrbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hvl/latest/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
-       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
-       <port type="input" prefix="pReset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="QN" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hvl__dfrbp_1" default_val="1"/>
-      <port type="input" prefix="outpad" lib_name="A" size="1"/>
-      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="sky130_fd_sc_hvl__fah_1" prefix="sky130_fd_sc_hvl__fah_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hvl/latest/cells/fah/sky130_fd_sc_hvl__fah_1.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hvl__inv_1"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="input" prefix="cin" lib_name="CI" size="1"/>
-      <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
-      <port type="output" prefix="cout" lib_name="COUT" size="1"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sky130_fd_sc_hvl__dfrbp_1" num_regions="4"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L1" circuit_model_name="chan_segment"/>
-    <segment name="L2" circuit_model_name="chan_segment"/>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hvl__sdfrtp_1"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="sky130_fd_sc_hvl__fah_1"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut4 to the first 3 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble4' -->
-    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- Binding operating pb_types in mode 'shift_register' -->
-    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- End physical pb_type binding in complex block IO -->
-  </pb_type_annotations>
-</openfpga_architecture>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml
deleted file mode 100644
index 1ebbe06..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdls_cc_openfpga.xml
+++ /dev/null
@@ -1,270 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k4_frac_cc_sky130nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-     - Skywater 130nm PDK
-       - circuit models are binded to the opensource skywater 
-         foundry middle-speed (ms) standard cell library
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_ls__inv_1" prefix="sky130_fd_sc_ls__inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/inv/sky130_fd_sc_ls__inv_1.v">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-   <circuit_model type="inv_buf" name="sky130_fd_sc_ls__buf_2" prefix="sky130_fd_sc_ls__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/buf/sky130_fd_sc_ls__buf_2.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_ls__buf_4" prefix="sky130_fd_sc_ls__buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/buf/sky130_fd_sc_ls__buf_4.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_ls__inv_2" prefix="sky130_fd_sc_ls__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/inv/sky130_fd_sc_ls__inv_2.v">
-      <design_technology type="cmos" topology="buffer" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="sky130_fd_sc_ls__or2_1" prefix="sky130_fd_sc_ls__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/or2/sky130_fd_sc_ls__or2_1.v">
-      <design_technology type="cmos" topology="OR"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <!-- Define a circuit model for the standard cell MUX2 
-         OpenFPGA requires the following truth table for the MUX2
-         When the select signal sel is enabled, the first input, i.e., in0 
-         will be propagated to the output, i.e., out
-         If your standard cell provider does not offer the exact truth table,
-         you can simply swap the inputs as shown in the example below
-      -->
-    <circuit_model type="gate" name="sky130_fd_sc_ls__mux2_1" prefix="sky130_fd_sc_ls__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/mux2/sky130_fd_sc_ls__mux2_1.v">
-      <design_technology type="cmos" topology="MUX2"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in0" lib_name="A1" size="1"/>
-      <port type="input" prefix="in1" lib_name="A0" size="1"/>
-      <port type="input" prefix="sel" lib_name="S" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_ls__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__buf_4"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_ls__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="sky130_fd_sc_ls__sdfrtp_1" prefix="sky130_fd_sc_ls__sdfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
-       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="DI" lib_name="SCD" size="1"/>
-       <port type="input" prefix="TESTEN" lib_name="SCE" size="1" is_global="true" default_val="0"/>
-       <port type="input" prefix="reset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__buf_2"/>
-      <lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
-      <lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__buf_2"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__buf_2" location_map="-1-"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_ls__mux2_1"/>
-      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_ls__or2_1"/>
-      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_ls__dfrbp_1" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sky130_fd_sc_ls__dfrbp_1" prefix="sky130_fd_sc_ls__dfrbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
-       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
-       <port type="input" prefix="pReset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="QN" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_ls__dfrbp_1" default_val="1"/>
-      <port type="input" prefix="outpad" lib_name="A" size="1"/>
-      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="sky130_fd_sc_ls__fah_1" prefix="sky130_fd_sc_ls__fah_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/fah/sky130_fd_sc_ls__fah_1.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ls__inv_1"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="input" prefix="cin" lib_name="CI" size="1"/>
-      <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
-      <port type="output" prefix="cout" lib_name="COUT" size="1"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sky130_fd_sc_ls__dfrbp_1" num_regions="4"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L1" circuit_model_name="chan_segment"/>
-    <segment name="L2" circuit_model_name="chan_segment"/>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_ls__sdfrtp_1"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="sky130_fd_sc_ls__fah_1"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut4 to the first 3 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble4' -->
-    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- Binding operating pb_types in mode 'shift_register' -->
-    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- End physical pb_type binding in complex block IO -->
-  </pb_type_annotations>
-</openfpga_architecture>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
deleted file mode 100644
index 1bbf6d7..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_fdms_cc_openfpga.xml
+++ /dev/null
@@ -1,270 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k4_frac_cc_sky130nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-     - Skywater 130nm PDK
-       - circuit models are binded to the opensource skywater 
-         foundry middle-speed (ms) standard cell library
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_ms__inv_1" prefix="sky130_fd_sc_ms__inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ms/latest/cells/inv/sky130_fd_sc_ms__inv_1.v">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-   <circuit_model type="inv_buf" name="sky130_fd_sc_ms__buf_2" prefix="sky130_fd_sc_ms__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ms/latest/cells/buf/sky130_fd_sc_ms__buf_2.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_ms__buf_4" prefix="sky130_fd_sc_ms__buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ms/latest/cells/buf/sky130_fd_sc_ms__buf_4.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_ms__inv_2" prefix="sky130_fd_sc_ms__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ms/latest/cells/inv/sky130_fd_sc_ms__inv_2.v">
-      <design_technology type="cmos" topology="buffer" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="sky130_fd_sc_ms__or2_1" prefix="sky130_fd_sc_ms__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ms/latest/cells/or2/sky130_fd_sc_ms__or2_1.v">
-      <design_technology type="cmos" topology="OR"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <!-- Define a circuit model for the standard cell MUX2 
-         OpenFPGA requires the following truth table for the MUX2
-         When the select signal sel is enabled, the first input, i.e., in0 
-         will be propagated to the output, i.e., out
-         If your standard cell provider does not offer the exact truth table,
-         you can simply swap the inputs as shown in the example below
-      -->
-    <circuit_model type="gate" name="sky130_fd_sc_ms__mux2_1" prefix="sky130_fd_sc_ms__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ms/latest/cells/mux2/sky130_fd_sc_ms__mux2_1.v">
-      <design_technology type="cmos" topology="MUX2"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in0" lib_name="A1" size="1"/>
-      <port type="input" prefix="in1" lib_name="A0" size="1"/>
-      <port type="input" prefix="sel" lib_name="S" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_ms__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__buf_4"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_ms__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="sky130_fd_sc_ms__sdfrtp_1" prefix="sky130_fd_sc_ms__sdfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ms/latest/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
-       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="DI" lib_name="SCD" size="1"/>
-       <port type="input" prefix="TESTEN" lib_name="SCE" size="1" is_global="true" default_val="0"/>
-       <port type="input" prefix="reset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__buf_2"/>
-      <lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
-      <lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__buf_2"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__buf_2" location_map="-1-"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_ms__mux2_1"/>
-      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_ms__or2_1"/>
-      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_ms__dfrbp_1" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sky130_fd_sc_ms__dfrbp_1" prefix="sky130_fd_sc_ms__dfrbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ms/latest/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
-       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
-       <port type="input" prefix="pReset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="QN" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_ms__dfrbp_1" default_val="1"/>
-      <port type="input" prefix="outpad" lib_name="A" size="1"/>
-      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="sky130_fd_sc_ms__fah_1" prefix="sky130_fd_sc_ms__fah_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_ms/latest/cells/fah/sky130_fd_sc_ms__fah_1.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_ms__inv_1"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="input" prefix="cin" lib_name="CI" size="1"/>
-      <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
-      <port type="output" prefix="cout" lib_name="COUT" size="1"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sky130_fd_sc_ms__dfrbp_1" num_regions="4"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L1" circuit_model_name="chan_segment"/>
-    <segment name="L2" circuit_model_name="chan_segment"/>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_ms__sdfrtp_1"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="sky130_fd_sc_ms__fah_1"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut4 to the first 3 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble4' -->
-    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- Binding operating pb_types in mode 'shift_register' -->
-    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- End physical pb_type binding in complex block IO -->
-  </pb_type_annotations>
-</openfpga_architecture>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml
deleted file mode 100644
index a47ab93..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_adder_register_scan_chain_skywater130nm_ndafdms_cc_openfpga.xml
+++ /dev/null
@@ -1,269 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k4_frac_cc_sky130nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-     - Skywater 130nm PDK
-       - circuit models are binded to the skywater foundry middle-speed (ms) NDA standard cell library
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="scs8ms_inv_1" prefix="scs8ms_inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_inv_1.v">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-   <circuit_model type="inv_buf" name="scs8ms_buf_2" prefix="scs8ms_buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_buf_2.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="scs8ms_buf_4" prefix="scs8ms_buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_buf_4.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="scs8ms_inv_2" prefix="scs8ms_inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_inv_2.v">
-      <design_technology type="cmos" topology="buffer" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="scs8ms_or2_1" prefix="scs8ms_or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_or2_1.v">
-      <design_technology type="cmos" topology="OR"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <!-- Define a circuit model for the standard cell MUX2 
-         OpenFPGA requires the following truth table for the MUX2
-         When the select signal sel is enabled, the first input, i.e., in0 
-         will be propagated to the output, i.e., out
-         If your standard cell provider does not offer the exact truth table,
-         you can simply swap the inputs as shown in the example below
-      -->
-    <circuit_model type="gate" name="scs8ms_mux2_1" prefix="scs8ms_mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_mux2_1.v">
-      <design_technology type="cmos" topology="MUX2"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in0" lib_name="A1" size="1"/>
-      <port type="input" prefix="in1" lib_name="A0" size="1"/>
-      <port type="input" prefix="sel" lib_name="S" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <pass_gate_logic circuit_model_name="scs8ms_mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="scs8ms_buf_4"/>
-      <pass_gate_logic circuit_model_name="scs8ms_mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="scs8ms_sdfrtp_1" prefix="scs8ms_sdfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_sdfrtp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
-       <output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="DI" lib_name="SCD" size="1"/>
-       <port type="input" prefix="TESTEN" lib_name="SCE" size="1" is_global="true" default_val="0"/>
-       <port type="input" prefix="reset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="scs8ms_buf_2"/>
-      <lut_input_inverter exist="true" circuit_model_name="scs8ms_inv_1"/>
-      <lut_input_buffer exist="true" circuit_model_name="scs8ms_buf_2"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="scs8ms_buf_2" location_map="-1-"/>
-      <pass_gate_logic circuit_model_name="scs8ms_mux2_1"/>
-      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="scs8ms_or2_1"/>
-      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="scs8ms_dfrbp_1" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="scs8ms_dfrbp_1" prefix="scs8ms_dfrbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_dfrbp_1.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
-       <output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
-       <port type="input" prefix="pReset" lib_name="RESETB" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="QN" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
-      <output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="scs8ms_dfrbp_1" default_val="1"/>
-      <port type="input" prefix="outpad" lib_name="A" size="1"/>
-      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="scs8ms_fah_1" prefix="scs8ms_fah_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-src-nda/scs8ms/V0.0.1/verilog/scs8ms_fah_1.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
-      <output_buffer exist="true" circuit_model_name="scs8ms_inv_1"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="input" prefix="cin" lib_name="CI" size="1"/>
-      <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
-      <port type="output" prefix="cout" lib_name="COUT" size="1"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="scs8ms_dfrbp_1" num_regions="4"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L1" circuit_model_name="chan_segment"/>
-    <segment name="L2" circuit_model_name="chan_segment"/>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="scs8ms_sdfrtp_1"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="scs8ms_fah_1"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut4 to the first 3 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble4' -->
-    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- Binding operating pb_types in mode 'shift_register' -->
-    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- End physical pb_type binding in complex block IO -->
-  </pb_type_annotations>
-</openfpga_architecture>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
deleted file mode 100644
index ae31d83..0000000
--- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+++ /dev/null
@@ -1,255 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k4_frac_cc_sky130nm.xml
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-     - Skywater 130nm PDK
-       - circuit models are binded to the opensource skywater
-         foundry middle-speed (ms) standard cell library
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
-      <design_technology type="cmos" topology="buffer" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" lib_name="A" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
-      <design_technology type="cmos" topology="OR"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" lib_name="A" size="1"/>
-      <port type="input" prefix="b" lib_name="B" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <!-- Define a circuit model for the standard cell MUX2
-         OpenFPGA requires the following truth table for the MUX2
-         When the select signal sel is enabled, the first input, i.e., in0
-         will be propagated to the output, i.e., out
-         If your standard cell provider does not offer the exact truth table,
-         you can simply swap the inputs as shown in the example below
-      -->
-    <circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
-      <design_technology type="cmos" topology="MUX2"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in0" lib_name="A1" size="1"/>
-      <port type="input" prefix="in1" lib_name="A0" size="1"/>
-      <port type="input" prefix="sel" lib_name="S" size="1"/>
-      <port type="output" prefix="out" lib_name="X" size="1"/>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
-      <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/>
-      <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxbp_1" prefix="sky130_fd_sc_hd__sdfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <port type="input" prefix="D" size="1"/>
-      <port type="input" prefix="DI" lib_name="SCD" size="1"/>
-      <port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
-      <!-- <port type="input" prefix="reset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true"/> -->
-      <port type="output" prefix="Q" size="1"/>
-      <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
-      <lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
-      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
-      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
-      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sky130_fd_sc_hd__dfxbp_1" prefix="sky130_fd_sc_hd__dfxbp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrbp/sky130_fd_sc_hd__dfxbp_1.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <!-- <port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/> -->
-      <port type="input" prefix="D" size="1"/>
-      <port type="output" prefix="Q" size="1"/>
-      <port type="output" prefix="Q_N" size="1"/>
-      <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/sc_verilog/std_cell_extract.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <port type="inout" prefix="Y" lib_name="Y" size="1" is_global="true" is_io="true" />
-      <port type="output" prefix="A" lib_name="A" size="1" is_global="true" is_io="true" />
-      <port type="sram" prefix="en" lib_name="mem_out" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" default_val="1"/>
-      <port type="output" prefix="IE" lib_name="IE" size="1" is_global="true" is_io="true" />
-      <port type="output" prefix="OE" lib_name="OE" size="1" is_global="true" is_io="true" />
-      <port type="input" prefix="outpad" lib_name="in" size="1"/>
-      <port type="output" prefix="inpad" lib_name="out" size="1"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfxbp_1" num_regions="1"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
-    <switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L1" circuit_model_name="chan_segment"/>
-    <segment name="L2" circuit_model_name="chan_segment"/>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfxbp_1"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:2]"/>
-      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble4' -->
-    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- Binding operating pb_types in mode 'shift_register' -->
-    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- End physical pb_type binding in complex block IO -->
-  </pb_type_annotations>
-</openfpga_architecture>
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
index 6c7ef58..479c05b 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
@@ -43,6 +43,18 @@
         10e-12
       </delay_matrix>
     </circuit_model>
+    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_1" prefix="sky130_fd_sc_hd__buf_1" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v">
+      <design_technology type="cmos" topology="buffer" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" lib_name="A" size="1"/>
+      <port type="output" prefix="out" lib_name="X" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
     <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
       <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
       <device_technology device_model_name="logic"/>
@@ -160,11 +172,7 @@
     <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
       <input_buffer exist="false"/>
-<<<<<<< HEAD
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-=======
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_1"/>
->>>>>>> origin/master
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -173,11 +181,7 @@
     <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
       <input_buffer exist="false"/>
-<<<<<<< HEAD
-      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_4"/>
-=======
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
->>>>>>> origin/master
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -209,7 +213,7 @@
       <port type="input" prefix="D" size="1"/>
       <port type="input" prefix="DI" lib_name="SCD" size="1"/>
       <port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
-      <port type="input" prefix="reset" lib_name="RESET_B" size="1" default_val="1"/>
+      <port type="input" prefix="reset" lib_name="RESET_B" size="1" default_val="1"/> 
       <port type="output" prefix="Q" size="1"/>
       <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" />
     </circuit_model>
@@ -236,7 +240,7 @@
       <port type="input" prefix="D" size="1"/>
       <port type="output" prefix="Q" size="1"/>
       <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
-      <port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
+      <port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/> 
     </circuit_model>
     <circuit_model type="iopad" name="EMBEDDED_IO_HD" prefix="EMBEDDED_IO_HD" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
       <design_technology type="cmos"/>
@@ -290,9 +294,9 @@
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
     <!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
-    <pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/>
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
 
     <!-- physical pb_type binding in complex block CLB -->
diff --git a/README.md b/README.md
index 0d1671b..b7e40f0 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,10 @@
-# skywater-openfpga
-FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA
+# SOFA
+[![linux_build](https://github.com/LNIS-Projects/skywater-openfpga/workflows/linux_build/badge.svg)](https://github.com/LNIS-Projects/skywater-openfpga/actions)
+[![Documentation Status](https://readthedocs.org/projects/skywater-openfpga/badge/?version=latest)](https://skywater-openfpga.readthedocs.io/en/latest/?badge=latest)
+      
+## Introduction
+
+SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework
 
 ## Quick Start
 
@@ -8,13 +13,14 @@ FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA
 git clone https://github.com/LNIS-Projects/skywater-openfpga.git
 python3 SCRIPT/repo_setup.py --openfpga_root_path ${OPENFPGA_PROJECT_DIRECTORY}
 ```
+---
 
-* If you have openfpga repository cloned in the level of this project, you can simple call
+* If you have openfpga repository cloned at the same level of this project, you can simple call
 ```bash
   python3 SCRIPT/repo_setup.py
 ``` 
 
-Otherwise, you should provide full path for the --openfpga\root\_path
+Otherwise, you should provide full path using the option _--openfpga\_root\_path_ 
 
 ## Directory Organization
 
@@ -31,6 +37,8 @@ Otherwise, you should provide full path for the --openfpga\root\_path
                     Keep a README inside the folder about the ICC2 version and how-to-use.
   - **MSIM**: workspace of verification using Mentor ModelSim
 
+---
+
 * Note: 
   - Please **ONLY** place folders under this directory.
     README should be the **ONLY** file under this directory