From 51833269465eced42bd76e9ac4a7608a6bee6bde Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 24 Jul 2021 14:59:34 -0700 Subject: [PATCH] Update generate_testbench.openfpga Address #124 --- .../FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga index 49a224f..64d6fcc 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga @@ -55,7 +55,7 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC \ - --bitstream fabric_bitstream.bit + --bitstream fabric_bitstream.bit \ --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ --explicit_port_mapping # Exclude signal initialization since it does not help simulator converge