diff --git a/SNPS_PT/SCRIPT/report_timing_clb.tcl b/SNPS_PT/SCRIPT/report_timing_clb.tcl
index 80afddd..502a9bb 100644
--- a/SNPS_PT/SCRIPT/report_timing_clb.tcl
+++ b/SNPS_PT/SCRIPT/report_timing_clb.tcl
@@ -3,18 +3,24 @@
 # using Synopsys PrimeTime
 #####################################################################
  
-##################################
-# Ensure a clean start
-remove_design -all
-remove_lib -all
-
 ##################################
 # Define environment variables
 set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
-set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
-set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
-set DEVICE_NAME "SOFA"
+
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
+
+#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
+set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
+#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
+
+#set DEVICE_NAME "SOFA_HD"
+set DEVICE_NAME "QLSOFA_HD"
+#set DEVICE_NAME "SOFA_CHD"
+
 set TIMING_REPORT_HOME "../TIMING_REPORTS/";
+
 # Enable preprocessing in Verilog parser
 set_app_var svr_enable_vpp true
 # Enable reporting ALL the timing paths even those are NOT constrained
@@ -26,6 +32,11 @@ set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
 
 set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
 
+##################################
+# Ensure a clean start
+remove_design -all
+remove_lib -all
+
 ##################################
 # Read timing libraries
 read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
@@ -70,6 +81,8 @@ report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__
 report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
 report_timing -from logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out -to logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
 
+# TODO: Carry logic timing 
+
 ##################################
 # Finish and quit 
 # Comment it out if you want to debug