diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
index e40f43e..7ce38c4 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
@@ -1,3 +1,29 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:3140f41d14f1046308ebd07b6527c4ec781ab3c18e63b237aba9b435b9c044de
-size 1239
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_latch_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
index 2781b69..eac064e 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,31 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:9d2003a31c42e9558a77f3891b6284affed509e22d38dbb150f475db968c5f8e
-size 1343
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_latch_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
index 731e086..bab64ec 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
@@ -1,3 +1,29 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:6395e2f33f3dcb8dad1c92fa0659bc4b842b3495d683add90e50d942e28b6ef1
-size 1235
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Sun Nov 22 13:37:06 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_or2_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
index f9dd991..036f169 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,31 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:ec87f38ebc0e4f795a0a72b760f6181288ef6f7cc72f7708ec21d77a1ea8c28d
-size 1339
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_or2_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
index bf40134..ebca70c 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
@@ -1,3 +1,29 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:0168df4405980eb7be0f0231735794d86c514199126d0941f043ba38905d0c4f
-size 1227
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
index 1e21a4f..6ff54f2 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,31 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:3fc3f03b263ff267b9543c09f338222e9e9950978915a10a16825decd8deab4c
-size 1331
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
index 30a2005..5612ae8 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
@@ -1,3 +1,28 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:5b1dbfb9b52a4e87e544773b46710111d2a53c24922de3e10eefd82c7d280f0b
-size 1199
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// Design parameter for FPGA I/O sizes
+`define FPGA_IO_SIZE 144
+
+// Design parameter for FPGA bitstream sizes
+`define FPGA_BITSTREAM_SIZE 67960
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/ccff_test_post_pnr_v1.0.v"
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
index 386cac1..df51dfc 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,30 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:f5fe62252b7eae6cd437a4fde8a18dcdcc61e629ab847b6bffa2d8d0d8dc60b4
-size 1353
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// Design parameter for FPGA I/O sizes
+`define FPGA_IO_SIZE 144
+
+// Design parameter for FPGA bitstream sizes
+`define FPGA_BITSTREAM_SIZE 67960
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v"
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
index 79c523c..53baa59 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
@@ -1,3 +1,29 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:9a2a5d743a10211cd55496c15a559690e5a09a328edcb0942d901ba5e5df48b8
-size 1243
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Fri Nov 20 15:48:54 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "routing_test_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
index e440cab..8060803 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,31 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:a18b7fab25c736e3d465a51353672d7bc5dc7e693145fee2837afc1d11b78289
-size 1347
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "routing_test_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
index 1edcd07..5aff11c 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
@@ -1,3 +1,28 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:98d430047e77dd1e59a84fd4fdc368b229f29e27ae0354657e166db51e2f56a3
-size 1198
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// Design parameter for FPGA I/O sizes
+`define FPGA_IO_SIZE 144
+
+// Design parameter for FPGA bitstream sizes
+`define FPGA_SCANCHAIN_SIZE 2304
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr_v1.0.v"
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
index 8783bb0..6a4c5f4 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,30 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:5dd9f4ffe36c1f5ac05ff49da29ec5541913f2e2efce7cf7a4c7e1cb9120264e
-size 1352
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// Design parameter for FPGA I/O sizes
+`define FPGA_IO_SIZE 144
+
+// Design parameter for FPGA bitstream sizes
+`define FPGA_SCANCHAIN_SIZE 2304
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v"
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
index ca377b7..99b86b1 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
@@ -1,3 +1,29 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:32e7a27472ef1501fec8765f8a7beb44ab61c84c514a5f63801840cfdec20eb7
-size 1272
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_latch_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
index 5d0b93a..053831e 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,31 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:c2067d21d21d3666ebe52b8de512bf06020ab395b65304387709e166e1d43a23
-size 1376
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_latch_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
index b93bc4a..a5f794d 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
@@ -1,3 +1,29 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:ee2934fe5c3048ac3655a3cc6213f176d83c3495aef7428904ad229f39d424a0
-size 1268
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Sun Nov 22 13:37:06 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_or2_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
index c87613f..bfa6b74 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,31 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:1707e2d2da1c2eba04f17079d9d9144b71be24bf19b9d99c83ceefc5d46d6afd
-size 1372
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_or2_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
index 0fe63cd..51d25d3 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
@@ -1,3 +1,29 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:35a893d7106b66061ef6c45570ba26c5eb2cc31c1ba667193e01003e1a3c8294
-size 1260
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
index d6c6337..81727fe 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,31 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:3cfd0b49a75dbcc308f61212ed162d2c74c9343bffe35d78cb39fa553507b559
-size 1364
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "and2_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
index 114dfab..77e36fd 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
@@ -1,3 +1,28 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:fe32ecd75d97fefe74d1e1e01713ed38098f845cc37aad617b161e64a05a4e36
-size 1216
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// Design parameter for FPGA I/O sizes
+`define FPGA_IO_SIZE 144
+
+// Design parameter for FPGA bitstream sizes
+`define FPGA_BITSTREAM_SIZE 78765
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/ccff_test_post_pnr_v1.1.v"
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
index 222f122..0c74bfc 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,30 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:cedd3fbe2dc2158e46da28ab3b630b45571f7015b89f29391b092bb3860fdbcc
-size 1386
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// Design parameter for FPGA I/O sizes
+`define FPGA_IO_SIZE 144
+
+// Design parameter for FPGA bitstream sizes
+`define FPGA_BITSTREAM_SIZE 78765
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v"
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
index a37047e..26f8010 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
@@ -1,3 +1,29 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:7dbfbefcae891ea972982503967a7dc838843bd86ff134873a38da4a1c4b4a1f
-size 1276
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Fri Nov 20 15:48:54 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "routing_test_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
index d5bbb87..bab9671 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,31 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:b5388c9df5e22b40644563abea84f530445b17a43673499bcfcb9680acf5aa66
-size 1380
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "routing_test_output_verilog.v"
+`endif
+
+`ifdef AUTOCHECKED_SIMULATION
+	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_autocheck_top_tb.v"
+`endif
+
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
index 3c6c896..24708c9 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
@@ -1,3 +1,28 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:8cb80347043fd1a8fab62f8963bf174668951941f6a60e3ba6db9c2a0f439b07
-size 1215
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// Design parameter for FPGA I/O sizes
+`define FPGA_IO_SIZE 144
+
+// Design parameter for FPGA bitstream sizes
+`define FPGA_SCANCHAIN_SIZE 2304
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr_v1.1.v"
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
index 73ead6b..ef40b51 100644
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,30 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:e7a163317878eb9295a02108efc9a8e7c3f4a5485aa05e03bd29b40445d88d88
-size 1385
+//-------------------------------------------
+//	FPGA Synthesizable Verilog Netlist
+//	Description: Netlist Summary
+//	Author: Xifan TANG
+//	Organization: University of Utah
+//	Date: Wed Nov 11 16:01:30 2020
+//-------------------------------------------
+//----- Time scale -----
+`timescale 1ns / 1ps
+
+// Design parameter for FPGA I/O sizes
+`define FPGA_IO_SIZE 144
+
+// Design parameter for FPGA bitstream sizes
+`define FPGA_SCANCHAIN_SIZE 2304
+
+// ------ Include simulation defines -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
+
+// ------ Include Skywater cell netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
+
+// ------ Include fabric top-level netlists -----
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
+
+`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v"