diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
new file mode 100644
index 0000000..ae31d83
--- /dev/null
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
@@ -0,0 +1,255 @@
+
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+ 10e-12
+
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+ 10e-12
+
+
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+
+
+ 10e-12
+
+
+ 10e-12
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+
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+ 10e-12
+
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+ 10e-12
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+ 10e-12
+
+
+ 10e-12
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+
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+
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+
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+
+
+ 10e-12 5e-12
+
+
+ 10e-12 5e-12
+
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+
diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
new file mode 100644
index 0000000..5d865fd
--- /dev/null
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
@@ -0,0 +1,598 @@
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ clb.clk
+ clb.regin clb.scin
+ clb.O[7:0] clb.I0 clb.I1 clb.I2 clb.I3
+ clb.regout clb.scout clb.O[15:8] clb.I4 clb.I5 clb.I6 clb.I7
+
+
+
+
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+ 1 1
+ 1
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+ 1 1 1
+ 1 1
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+
+
+ 1 1 1 1 1
+ 1 1 1 1
+
+
+
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+
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+ 235e-12
+ 235e-12
+ 235e-12
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+
+
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+
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diff --git a/SCRIPT/repo_setup.py b/SCRIPT/repo_setup.py
index e555825..ee233f7 100644
--- a/SCRIPT/repo_setup.py
+++ b/SCRIPT/repo_setup.py
@@ -110,7 +110,7 @@ logging.info("Processed for " + str(num_task_config_file_processed) + "openfpga
#####################################################################
# Create symbolic link to OpenFPGA flow task directory
#####################################################################
-openfpga_task_src_dir = skywater_openfpga_homepath + "SCRIPT/skywater_openfpga_task";
+openfpga_task_src_dir = skywater_openfpga_homepath + "/SCRIPT/skywater_openfpga_task";
openfpga_task_des_dir = openfpga_root_path + "/openfpga_flow/tasks/skywater_openfpga_task";
if (os.path.isdir(openfpga_task_des_dir) or os.path.isfile(openfpga_task_des_dir)):
@@ -122,6 +122,38 @@ elif (os.path.islink(openfpga_task_des_dir)):
os.unlink(openfpga_task_des_dir);
logging.warning("Removed the symbolic link");
-os.symlink(openfpga_task_src_dir, openfpga_task_des_dir);
+os.symlink(openfpga_task_src_dir, openfpga_task_des_dir, True);
logging.info("Created OpenFPGA task symbolic link at " + openfpga_task_des_dir);
+
+#####################################################################
+# Execute openfpga task runs
+#####################################################################
+openfpga_task_path_prefix_to_remove = re.sub("/", "\/", skywater_openfpga_homepath + "/SCRIPT/");
+openfpga_task_list = [];
+for task_file in get_list_of_task_config_files(skywater_openfpga_task_dirpath, "task.conf"):
+ # Find all the task.conf and extract task name from the absolute paths:
+ # - Remove the skywater_openfpga_homepath + "/SCRIPT/" at the beginning
+ # - Remove the config/task.conf at the end
+ task_name = re.sub(openfpga_task_path_prefix_to_remove, "", task_file);
+ task_name = re.sub("/config\/task.conf$", "", task_name);
+ openfpga_task_list.append(task_name);
+
+# Execute openfpga task:
+# - Change directory to openfpga root directory
+# - Run openfpga flow task
+# - Go back
+os.chdir(openfpga_root_path);
+for task_name in openfpga_task_list:
+ # Remove all the previous runs in the openfpga task to ensure a clean start
+ logging.info("Clean up previous runs for openfpga task: " + task_name + "...");
+ cmd = "python3 openfpga_flow/scripts/run_fpga_task.py " + task_name + " --debug --show_thread_logs --remove_run_dir all";
+ os.system(cmd);
+ logging.info("Done");
+ # Execute new task run
+ cmd = "python3 openfpga_flow/scripts/run_fpga_task.py " + task_name + " --debug --show_thread_logs";
+ logging.info("Running openfpga task: " + task_name + "...");
+ os.system(cmd);
+ logging.info("Done");
+
+os.chdir(skywater_openfpga_homepath);
diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_fabric/config/task_template.conf
new file mode 100644
index 0000000..21ae463
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_fabric/config/task_template.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_FPGA_2x2_fdhd_cc
+openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_FPGA_2x2_fdhd_cc
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_sdc/config/task_template.conf
new file mode 100644
index 0000000..cd6665a
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_sdc/config/task_template.conf
@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_FPGA_2x2_fdhd_cc
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_testbench/config/task_template.conf
new file mode 100644
index 0000000..1a6a378
--- /dev/null
+++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_cc_fdhd_2x2/generate_testbench/config/task_template.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
+openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_FPGA_2x2_fdhd_cc
+openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v
+
+[ARCHITECTURES]
+arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=