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Fixed architecture files for new OpenFPGA version

This commit is contained in:
Ganesh Gore 2023-03-01 22:31:24 -07:00
parent e2f3839993
commit 4ab8440233
10 changed files with 293 additions and 257 deletions
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22
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml
View File

@ -73,7 +73,9 @@
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0">
<tile name="io_top" area="0">
<sub_tile name="io_top" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -83,9 +85,12 @@
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0">
<tile name="io_right" area="0">
<sub_tile name="io_right" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -95,9 +100,12 @@
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0">
<tile name="io_bottom" area="0">
<sub_tile name="io_bottom" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -107,9 +115,11 @@
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0">
<tile name="io_left" area="0">
<sub_tile name="io_left" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -119,9 +129,12 @@
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<sub_tile name="clb" capacity="1">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -167,6 +180,7 @@
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
</pinlocations>
</sub_tile>
</tile>
</tiles>
<!-- ODIN II specific config ends -->

2
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_fabric.openfpga
View File

@ -6,7 +6,7 @@
# - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints
#
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga
View File

@ -6,7 +6,7 @@
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
#
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

19
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/arch/vpr_arch.xml
View File

@ -73,7 +73,9 @@
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0">
<tile name="io_top" area="0">
<sub_tile name="io_top" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -83,9 +85,11 @@
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0">
<tile name="io_right" area="0">
<sub_tile name="io_right" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -95,9 +99,11 @@
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0">
<tile name="io_bottom" area="0">
<sub_tile name="io_bottom" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -107,9 +113,11 @@
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0">
<tile name="io_left" area="0">
<sub_tile name="io_left" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -119,9 +127,11 @@
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<sub_tile name="clb" capacity="1">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -167,6 +177,7 @@
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
</pinlocations>
</sub_tile>
</tile>
</tiles>
<!-- ODIN II specific config ends -->

2
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task.conf
View File

@ -1 +1 @@
task_generation.conf
task_simulation.conf

2
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_fabric.openfpga
View File

@ -6,7 +6,7 @@
# - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints
#
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga
View File

@ -6,7 +6,7 @@
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
#
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

19
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/arch/vpr_arch.xml
View File

@ -63,7 +63,8 @@
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0">
<tile name="io_top" area="0">
<sub_tile name="io_top" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -73,9 +74,11 @@
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0">
<tile name="io_right" area="0">
<sub_tile name="io_right" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -85,9 +88,11 @@
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0">
<tile name="io_bottom" area="0">
<sub_tile name="io_bottom" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -97,9 +102,12 @@
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0">
<tile name="io_left" area="0">
<sub_tile name="io_left" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -109,9 +117,11 @@
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</sub_tile>
</tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<sub_tile name="clb" capacity="1">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -151,6 +161,7 @@
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out</loc>
</pinlocations>
</sub_tile>
</tile>
</tiles>
<!-- ODIN II specific config ends -->

2
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_fabric.openfpga
View File

@ -6,7 +6,7 @@
# - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints
#
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga
View File

@ -6,7 +6,7 @@
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
#
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}