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Fixed architecture files for new OpenFPGA version

This commit is contained in:
Ganesh Gore 2023-03-01 22:31:24 -07:00
parent e2f3839993
commit 4ab8440233
10 changed files with 293 additions and 257 deletions
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184
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml
View File

@ -73,100 +73,114 @@
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<!-- Top-side has 1 I/O per tile --> <!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0"> <tile name="io_top" area="0">
<equivalent_sites> <sub_tile name="io_top" capacity="1">
<site pb_type="io"/>
</equivalent_sites> <equivalent_sites>
<input name="outpad" num_pins="1"/> <site pb_type="io"/>
<output name="inpad" num_pins="1"/> </equivalent_sites>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <input name="outpad" num_pins="1"/>
<pinlocations pattern="custom"> <output name="inpad" num_pins="1"/>
<loc side="bottom">io_top.outpad io_top.inpad</loc> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
</pinlocations> <pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- Right-side has 1 I/O per tile --> <!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0"> <tile name="io_right" area="0">
<equivalent_sites> <sub_tile name="io_right" capacity="1">
<site pb_type="io"/>
</equivalent_sites> <equivalent_sites>
<input name="outpad" num_pins="1"/> <site pb_type="io"/>
<output name="inpad" num_pins="1"/> </equivalent_sites>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <input name="outpad" num_pins="1"/>
<pinlocations pattern="custom"> <output name="inpad" num_pins="1"/>
<loc side="left">io_right.outpad io_right.inpad</loc> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
</pinlocations> <pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- Bottom-side has 9 I/O per tile --> <!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0"> <tile name="io_bottom" area="0">
<equivalent_sites> <sub_tile name="io_bottom" capacity="9">
<site pb_type="io"/>
</equivalent_sites> <equivalent_sites>
<input name="outpad" num_pins="1"/> <site pb_type="io"/>
<output name="inpad" num_pins="1"/> </equivalent_sites>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <input name="outpad" num_pins="1"/>
<pinlocations pattern="custom"> <output name="inpad" num_pins="1"/>
<loc side="top">io_bottom.outpad io_bottom.inpad</loc> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
</pinlocations> <pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- Left-side has 1 I/O per tile --> <!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0"> <tile name="io_left" area="0">
<equivalent_sites> <sub_tile name="io_left" capacity="1">
<site pb_type="io"/> <equivalent_sites>
</equivalent_sites> <site pb_type="io"/>
<input name="outpad" num_pins="1"/> </equivalent_sites>
<output name="inpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <output name="inpad" num_pins="1"/>
<pinlocations pattern="custom"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<loc side="right">io_left.outpad io_left.inpad</loc> <pinlocations pattern="custom">
</pinlocations> <loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- CLB has most pins on the top and right sides --> <!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894"> <tile name="clb" area="53894">
<equivalent_sites> <sub_tile name="clb" capacity="1">
<site pb_type="clb"/>
</equivalent_sites> <equivalent_sites>
<input name="I0" num_pins="2" equivalent="full"/> <site pb_type="clb"/>
<input name="I0i" num_pins="2" equivalent="none"/> </equivalent_sites>
<input name="I1" num_pins="2" equivalent="full"/> <input name="I0" num_pins="2" equivalent="full"/>
<input name="I1i" num_pins="2" equivalent="none"/> <input name="I0i" num_pins="2" equivalent="none"/>
<input name="I2" num_pins="2" equivalent="full"/> <input name="I1" num_pins="2" equivalent="full"/>
<input name="I2i" num_pins="2" equivalent="none"/> <input name="I1i" num_pins="2" equivalent="none"/>
<input name="I3" num_pins="2" equivalent="full"/> <input name="I2" num_pins="2" equivalent="full"/>
<input name="I3i" num_pins="2" equivalent="none"/> <input name="I2i" num_pins="2" equivalent="none"/>
<input name="I4" num_pins="2" equivalent="full"/> <input name="I3" num_pins="2" equivalent="full"/>
<input name="I4i" num_pins="2" equivalent="none"/> <input name="I3i" num_pins="2" equivalent="none"/>
<input name="I5" num_pins="2" equivalent="full"/> <input name="I4" num_pins="2" equivalent="full"/>
<input name="I5i" num_pins="2" equivalent="none"/> <input name="I4i" num_pins="2" equivalent="none"/>
<input name="I6" num_pins="2" equivalent="full"/> <input name="I5" num_pins="2" equivalent="full"/>
<input name="I6i" num_pins="2" equivalent="none"/> <input name="I5i" num_pins="2" equivalent="none"/>
<input name="I7" num_pins="2" equivalent="full"/> <input name="I6" num_pins="2" equivalent="full"/>
<input name="I7i" num_pins="2" equivalent="none"/> <input name="I6i" num_pins="2" equivalent="none"/>
<input name="reg_in" num_pins="1"/> <input name="I7" num_pins="2" equivalent="full"/>
<input name="sc_in" num_pins="1"/> <input name="I7i" num_pins="2" equivalent="none"/>
<input name="cin" num_pins="1"/> <input name="reg_in" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/> <input name="sc_in" num_pins="1"/>
<output name="O" num_pins="16" equivalent="none"/> <input name="cin" num_pins="1"/>
<output name="reg_out" num_pins="1"/> <input name="reset" num_pins="1" is_non_clock_global="true"/>
<output name="sc_out" num_pins="1"/> <output name="O" num_pins="16" equivalent="none"/>
<output name="cout" num_pins="1"/> <output name="reg_out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <output name="sc_out" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"> <output name="cout" num_pins="1"/>
<fc_override port_name="reg_in" fc_type="frac" fc_val="0"/> <clock name="clk" num_pins="1"/>
<fc_override port_name="reg_out" fc_type="frac" fc_val="0"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/> <fc_override port_name="reg_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/> <fc_override port_name="reg_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="cin" fc_type="frac" fc_val="0"/> <fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="cout" fc_type="frac" fc_val="0"/> <fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="clk" fc_type="frac" fc_val="0"/> <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/> <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
</fc> <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<!--pinlocations pattern="spread"/--> <fc_override port_name="reset" fc_type="frac" fc_val="0"/>
<pinlocations pattern="custom"> </fc>
<loc side="left">clb.clk clb.reset</loc> <!--pinlocations pattern="spread"/-->
<loc side="top">clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc> <pinlocations pattern="custom">
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc> <loc side="left">clb.clk clb.reset</loc>
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc> <loc side="top">clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc>
</pinlocations> <loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->

2
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_fabric.openfpga
View File

@ -6,7 +6,7 @@
# - fabric hierarchy description for ICC2's hierarchical flow # - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints # - Timing/Design constraints
# #
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/generate_testbench.openfpga
View File

@ -6,7 +6,7 @@
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime # - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
# #
#--write_rr_graph example_rr_graph.xml #--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

181
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/arch/vpr_arch.xml
View File

@ -73,100 +73,111 @@
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<!-- Top-side has 1 I/O per tile --> <!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0"> <tile name="io_top" area="0">
<equivalent_sites> <sub_tile name="io_top" capacity="1">
<site pb_type="io"/>
</equivalent_sites> <equivalent_sites>
<input name="outpad" num_pins="1"/> <site pb_type="io"/>
<output name="inpad" num_pins="1"/> </equivalent_sites>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <input name="outpad" num_pins="1"/>
<pinlocations pattern="custom"> <output name="inpad" num_pins="1"/>
<loc side="bottom">io_top.outpad io_top.inpad</loc> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
</pinlocations> <pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- Right-side has 1 I/O per tile --> <!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0"> <tile name="io_right" area="0">
<equivalent_sites> <sub_tile name="io_right" capacity="1">
<site pb_type="io"/> <equivalent_sites>
</equivalent_sites> <site pb_type="io"/>
<input name="outpad" num_pins="1"/> </equivalent_sites>
<output name="inpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <output name="inpad" num_pins="1"/>
<pinlocations pattern="custom"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<loc side="left">io_right.outpad io_right.inpad</loc> <pinlocations pattern="custom">
</pinlocations> <loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- Bottom-side has 9 I/O per tile --> <!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0"> <tile name="io_bottom" area="0">
<equivalent_sites> <sub_tile name="io_bottom" capacity="9">
<site pb_type="io"/> <equivalent_sites>
</equivalent_sites> <site pb_type="io"/>
<input name="outpad" num_pins="1"/> </equivalent_sites>
<output name="inpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <output name="inpad" num_pins="1"/>
<pinlocations pattern="custom"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<loc side="top">io_bottom.outpad io_bottom.inpad</loc> <pinlocations pattern="custom">
</pinlocations> <loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- Left-side has 1 I/O per tile --> <!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0"> <tile name="io_left" area="0">
<equivalent_sites> <sub_tile name="io_left" capacity="1">
<site pb_type="io"/> <equivalent_sites>
</equivalent_sites> <site pb_type="io"/>
<input name="outpad" num_pins="1"/> </equivalent_sites>
<output name="inpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <output name="inpad" num_pins="1"/>
<pinlocations pattern="custom"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<loc side="right">io_left.outpad io_left.inpad</loc> <pinlocations pattern="custom">
</pinlocations> <loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- CLB has most pins on the top and right sides --> <!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894"> <tile name="clb" area="53894">
<equivalent_sites> <sub_tile name="clb" capacity="1">
<site pb_type="clb"/> <equivalent_sites>
</equivalent_sites> <site pb_type="clb"/>
<input name="I0" num_pins="2" equivalent="full"/> </equivalent_sites>
<input name="I0i" num_pins="2" equivalent="none"/> <input name="I0" num_pins="2" equivalent="full"/>
<input name="I1" num_pins="2" equivalent="full"/> <input name="I0i" num_pins="2" equivalent="none"/>
<input name="I1i" num_pins="2" equivalent="none"/> <input name="I1" num_pins="2" equivalent="full"/>
<input name="I2" num_pins="2" equivalent="full"/> <input name="I1i" num_pins="2" equivalent="none"/>
<input name="I2i" num_pins="2" equivalent="none"/> <input name="I2" num_pins="2" equivalent="full"/>
<input name="I3" num_pins="2" equivalent="full"/> <input name="I2i" num_pins="2" equivalent="none"/>
<input name="I3i" num_pins="2" equivalent="none"/> <input name="I3" num_pins="2" equivalent="full"/>
<input name="I4" num_pins="2" equivalent="full"/> <input name="I3i" num_pins="2" equivalent="none"/>
<input name="I4i" num_pins="2" equivalent="none"/> <input name="I4" num_pins="2" equivalent="full"/>
<input name="I5" num_pins="2" equivalent="full"/> <input name="I4i" num_pins="2" equivalent="none"/>
<input name="I5i" num_pins="2" equivalent="none"/> <input name="I5" num_pins="2" equivalent="full"/>
<input name="I6" num_pins="2" equivalent="full"/> <input name="I5i" num_pins="2" equivalent="none"/>
<input name="I6i" num_pins="2" equivalent="none"/> <input name="I6" num_pins="2" equivalent="full"/>
<input name="I7" num_pins="2" equivalent="full"/> <input name="I6i" num_pins="2" equivalent="none"/>
<input name="I7i" num_pins="2" equivalent="none"/> <input name="I7" num_pins="2" equivalent="full"/>
<input name="reg_in" num_pins="1"/> <input name="I7i" num_pins="2" equivalent="none"/>
<input name="sc_in" num_pins="1"/> <input name="reg_in" num_pins="1"/>
<input name="cin" num_pins="1"/> <input name="sc_in" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/> <input name="cin" num_pins="1"/>
<output name="O" num_pins="16" equivalent="none"/> <input name="reset" num_pins="1" is_non_clock_global="true"/>
<output name="reg_out" num_pins="1"/> <output name="O" num_pins="16" equivalent="none"/>
<output name="sc_out" num_pins="1"/> <output name="reg_out" num_pins="1"/>
<output name="cout" num_pins="1"/> <output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <output name="cout" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"> <clock name="clk" num_pins="1"/>
<fc_override port_name="reg_in" fc_type="frac" fc_val="0"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="reg_out" fc_type="frac" fc_val="0"/> <fc_override port_name="reg_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/> <fc_override port_name="reg_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/> <fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="cin" fc_type="frac" fc_val="0"/> <fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="cout" fc_type="frac" fc_val="0"/> <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
<fc_override port_name="clk" fc_type="frac" fc_val="0"/> <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/> <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc> <fc_override port_name="reset" fc_type="frac" fc_val="0"/>
<!--pinlocations pattern="spread"/--> </fc>
<pinlocations pattern="custom"> <!--pinlocations pattern="spread"/-->
<loc side="left">clb.clk clb.reset</loc> <pinlocations pattern="custom">
<loc side="top">clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc> <loc side="left">clb.clk clb.reset</loc>
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc> <loc side="top">clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc>
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc> <loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
</pinlocations> <loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->

2
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/config/task.conf
View File

@ -1 +1 @@
task_generation.conf task_simulation.conf

2
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_fabric.openfpga
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@ -6,7 +6,7 @@
# - fabric hierarchy description for ICC2's hierarchical flow # - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints # - Timing/Design constraints
# #
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga
View File

@ -6,7 +6,7 @@
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime # - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
# #
#--write_rr_graph example_rr_graph.xml #--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

171
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/arch/vpr_arch.xml
View File

@ -63,94 +63,105 @@
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<!-- Top-side has 1 I/O per tile --> <!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0"> <tile name="io_top" area="0">
<equivalent_sites> <sub_tile name="io_top" capacity="1">
<site pb_type="io"/> <equivalent_sites>
</equivalent_sites> <site pb_type="io"/>
<input name="outpad" num_pins="1"/> </equivalent_sites>
<output name="inpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <output name="inpad" num_pins="1"/>
<pinlocations pattern="custom"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<loc side="bottom">io_top.outpad io_top.inpad</loc> <pinlocations pattern="custom">
</pinlocations> <loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- Right-side has 1 I/O per tile --> <!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0"> <tile name="io_right" area="0">
<equivalent_sites> <sub_tile name="io_right" capacity="1">
<site pb_type="io"/> <equivalent_sites>
</equivalent_sites> <site pb_type="io"/>
<input name="outpad" num_pins="1"/> </equivalent_sites>
<output name="inpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <output name="inpad" num_pins="1"/>
<pinlocations pattern="custom"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<loc side="left">io_right.outpad io_right.inpad</loc> <pinlocations pattern="custom">
</pinlocations> <loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- Bottom-side has 9 I/O per tile --> <!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0"> <tile name="io_bottom" area="0">
<equivalent_sites> <sub_tile name="io_bottom" capacity="9">
<site pb_type="io"/> <equivalent_sites>
</equivalent_sites> <site pb_type="io"/>
<input name="outpad" num_pins="1"/> </equivalent_sites>
<output name="inpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <output name="inpad" num_pins="1"/>
<pinlocations pattern="custom"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<loc side="top">io_bottom.outpad io_bottom.inpad</loc> <pinlocations pattern="custom">
</pinlocations> <loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- Left-side has 1 I/O per tile --> <!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0"> <tile name="io_left" area="0">
<equivalent_sites> <sub_tile name="io_left" capacity="1">
<site pb_type="io"/>
</equivalent_sites> <equivalent_sites>
<input name="outpad" num_pins="1"/> <site pb_type="io"/>
<output name="inpad" num_pins="1"/> </equivalent_sites>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <input name="outpad" num_pins="1"/>
<pinlocations pattern="custom"> <output name="inpad" num_pins="1"/>
<loc side="right">io_left.outpad io_left.inpad</loc> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
</pinlocations> <pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
<!-- CLB has most pins on the top and right sides --> <!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894"> <tile name="clb" area="53894">
<equivalent_sites> <sub_tile name="clb" capacity="1">
<site pb_type="clb"/> <equivalent_sites>
</equivalent_sites> <site pb_type="clb"/>
<input name="I0" num_pins="3" equivalent="full"/> </equivalent_sites>
<input name="I0i" num_pins="1" equivalent="none"/> <input name="I0" num_pins="3" equivalent="full"/>
<input name="I1" num_pins="3" equivalent="full"/> <input name="I0i" num_pins="1" equivalent="none"/>
<input name="I1i" num_pins="1" equivalent="none"/> <input name="I1" num_pins="3" equivalent="full"/>
<input name="I2" num_pins="3" equivalent="full"/> <input name="I1i" num_pins="1" equivalent="none"/>
<input name="I2i" num_pins="1" equivalent="none"/> <input name="I2" num_pins="3" equivalent="full"/>
<input name="I3" num_pins="3" equivalent="full"/> <input name="I2i" num_pins="1" equivalent="none"/>
<input name="I3i" num_pins="1" equivalent="none"/> <input name="I3" num_pins="3" equivalent="full"/>
<input name="I4" num_pins="3" equivalent="full"/> <input name="I3i" num_pins="1" equivalent="none"/>
<input name="I4i" num_pins="1" equivalent="none"/> <input name="I4" num_pins="3" equivalent="full"/>
<input name="I5" num_pins="3" equivalent="full"/> <input name="I4i" num_pins="1" equivalent="none"/>
<input name="I5i" num_pins="1" equivalent="none"/> <input name="I5" num_pins="3" equivalent="full"/>
<input name="I6" num_pins="3" equivalent="full"/> <input name="I5i" num_pins="1" equivalent="none"/>
<input name="I6i" num_pins="1" equivalent="none"/> <input name="I6" num_pins="3" equivalent="full"/>
<input name="I7" num_pins="3" equivalent="full"/> <input name="I6i" num_pins="1" equivalent="none"/>
<input name="I7i" num_pins="1" equivalent="none"/> <input name="I7" num_pins="3" equivalent="full"/>
<input name="reg_in" num_pins="1"/> <input name="I7i" num_pins="1" equivalent="none"/>
<input name="sc_in" num_pins="1"/> <input name="reg_in" num_pins="1"/>
<output name="O" num_pins="16" equivalent="none"/> <input name="sc_in" num_pins="1"/>
<output name="reg_out" num_pins="1"/> <output name="O" num_pins="16" equivalent="none"/>
<output name="sc_out" num_pins="1"/> <output name="reg_out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <output name="sc_out" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"> <clock name="clk" num_pins="1"/>
<fc_override port_name="reg_in" fc_type="frac" fc_val="0"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="reg_out" fc_type="frac" fc_val="0"/> <fc_override port_name="reg_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/> <fc_override port_name="reg_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/> <fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="clk" fc_type="frac" fc_val="0"/> <fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
</fc> <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<!--pinlocations pattern="spread"/--> </fc>
<pinlocations pattern="custom"> <!--pinlocations pattern="spread"/-->
<loc side="left">clb.clk</loc> <pinlocations pattern="custom">
<loc side="top">clb.reg_in clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc> <loc side="left">clb.clk</loc>
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc> <loc side="top">clb.reg_in clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc>
<loc side="bottom">clb.reg_out clb.sc_out</loc> <loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
</pinlocations> <loc side="bottom">clb.reg_out clb.sc_out</loc>
</pinlocations>
</sub_tile>
</tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
@ -496,7 +507,7 @@
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
<!-- Consider the delay of the MUX between LUT4 and FF --> <!-- Consider the delay of the MUX between LUT4 and FF -->
<delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/> <delay_constant max="${LUT_OUT0_TO_FF_D_DELAY}" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>

2
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_fabric.openfpga
View File

@ -6,7 +6,7 @@
# - fabric hierarchy description for ICC2's hierarchical flow # - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints # - Timing/Design constraints
# #
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga
View File

@ -6,7 +6,7 @@
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime # - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
# #
#--write_rr_graph example_rr_graph.xml #--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}