From 4ab69d925c0c87ad89b03fafd74edeb19a45ae5e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 20:46:50 -0700 Subject: [PATCH] [Testbench] Add include netlist for wrapper testbench --- .../verilog_testbench/and2_post_pnr_wrapper_include_netlists.v | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..f4ea781 --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fcc9a447188a16956ca8a53f0916e3b1763cd9aa376c522f51777ff8f8f840ab +size 1370